| Report Title |
Gowin Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\Gowin_PSRAM_HS_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\impl\gwsynthesis\psram_board_test.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\Gowin_PSRAM_HS_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\psram.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\Gowin_PSRAM_HS_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\psram.sdc |
| GOWIN Version |
V1.9.7.02Beta |
| Part Number |
GW1NR-LV9MG100PC7/I6 |
| Device |
GW1NR-9C |
| Created Time |
Wed Mar 10 15:40:56 2021
|
| Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
50.233 |
| Quiescent Power (mW) |
5.062 |
| Dynamic Power (mW) |
45.172 |
| Psram Power (mW) |
172.000 |
| Junction Temperature |
25.522 |
| Theta JA |
10.500 |
| Max Allowed Ambient Temperature |
84.478 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.200 |
35.406 |
2.632 |
45.646 |
| VCCX |
2.500 |
0.625 |
0.444 |
2.674 |
| VCCO18 |
1.800 |
0.623 |
0.440 |
1.913 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
4.401 |
NA |
6.181 |
| IO |
5.973
| 2.437
| 12.194
|
| BSRAM |
8.736
| NA |
NA |
| PLL |
2.790
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
| psram_syn_top |
41.637 |
15.927(15.927) |
25.710(25.680) |
| psram_syn_top/u_PSRAM_TOP/ |
32.046 |
12.037(12.036) |
20.008(19.970) |
| psram_syn_top/u_PSRAM_TOP/u_psram_sync/ |
0.414 |
0.067(0.000) |
0.347(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/ |
15.876 |
5.986(5.646) |
9.890(8.349) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_init/ |
4.601 |
0.873(0.000) |
3.728(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/ |
9.394 |
4.773(4.772) |
4.621(4.621) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
5.246 |
2.441(0.000) |
2.805(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
4.147 |
2.331(0.000) |
1.816(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/ |
15.716 |
5.984(5.644) |
9.732(8.044) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_init/ |
4.557 |
0.872(0.000) |
3.685(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/ |
9.131 |
4.772(4.771) |
4.359(4.359) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
5.017 |
2.439(0.000) |
2.578(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
4.113 |
2.332(0.000) |
1.781(0.000) |
| psram_syn_top/u_test0/ |
3.295 |
0.552(0.000) |
2.743(0.000) |
| psram_syn_top/u_test1/ |
3.326 |
0.548(0.000) |
2.778(0.000) |
| psram_syn_top/your_instance_name/ |
2.941 |
2.790(0.000) |
0.150(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| clk_x1 |
50.000 |
38.240 |
| clk_d |
30.000 |
0.443 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |
| clk |
50.000 |
2.820 |
| clk_x2 |
100.000 |
0.060 |
| your_instance_name/rpll_inst/CLKOUTP.default_gen_clk |
120.000 |
0.072 |