#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: Desktop-2019KKU # Wed Sep 18 18:28:13 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\gw_uart_slave.v" (library work) @I:"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\gw_uart_slave.v":"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\uart_slave_defines.vh" (library work) @I::"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\uart_slave.v" (library work) Verilog syntax check successful! Selecting top level module gw_uart_slave @N:CG364 : uart_slave.v(49) | Synthesizing module uart_slave_rx in library work. Running optimization stage 1 on uart_slave_rx ....... @W:CL265 : uart_slave.v(159) | Removing unused bit 10 of shift_data_rx[10:0]. Either assign all bits or reduce the width of the signal. @N:CG364 : uart_slave.v(190) | Synthesizing module uart_slave_tx in library work. Running optimization stage 1 on uart_slave_tx ....... @N:CG364 : uart_slave.v(8) | Synthesizing module uart_slave in library work. Running optimization stage 1 on uart_slave ....... @N:CG364 : gw_uart_slave.v(3) | Synthesizing module gw_uart_slave in library work. Running optimization stage 1 on gw_uart_slave ....... Running optimization stage 2 on gw_uart_slave ....... Running optimization stage 2 on uart_slave ....... Running optimization stage 2 on uart_slave_tx ....... Running optimization stage 2 on uart_slave_rx ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\impl\synthesize\rev_1\synwork\layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 18:28:14 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 18:28:14 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 18:28:14 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 18:28:15 2019 ###########################################################] Premap Report # Wed Sep 18 18:28:15 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design @L: D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\impl\synthesize\rev_1\gw_uart_slave_scck.rpt Printing clock summary report in "D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\impl\synthesize\rev_1\gw_uart_slave_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design @W:FX474 : | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @W:BN680 : uart_slave.v(312) | Found conflicting initial value on the register bit_num[3:0]. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. @W:BN680 : uart_slave.v(293) | Found conflicting initial value on the register shift_data[10:0]. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. @W:BN132 : uart_slave.v(223) | Removing sequential instance u_uart_slave.u_uart_slave_tx.cnt_en_0 because it is equivalent to instance u_uart_slave.u_uart_slave_tx.busy_n_0. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------- 0 - gw_uart_slave|SCLK 229.3 MHz 4.362 inferred Autoconstr_clkgroup_0 99 ========================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------- gw_uart_slave|SCLK 99 SCLK(port) u_uart_slave.u_uart_slave_tx.shift_data[10].C - - ================================================================================================================================= @W:MT529 : uart_slave.v(100) | Found inferred clock gw_uart_slave|SCLK which controls 99 sequential elements including u_uart_slave.u_uart_slave_rx.div_cnt[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 99 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ======================================= Non-Gated/Non-Generated Clocks ======================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------- ClockId_0_0 SCLK Unconstrained_port 99 u_uart_slave.u_uart_slave_tx.bit_num[0] =============================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\impl\synthesize\rev_1\gw_uart_slave.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 192MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Sep 18 18:28:17 2019 ###########################################################] Map & Optimize Report # Wed Sep 18 18:28:17 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled @N:FX493 : | Applying initial value "000000000000000000000000" on instance u_uart_slave.u_uart_slave_rx.div_cnt[23:0]. @N:FX493 : | Applying initial value "0000" on instance u_uart_slave.u_uart_slave_rx.cnt_n[3:0]. @N:FX493 : | Applying initial value "0" on instance u_uart_slave.u_uart_slave_rx.cnt_en. @N:FX493 : | Applying initial value "0000000000" on instance u_uart_slave.u_uart_slave_rx.shift_data_rx[9:0]. @N:FX493 : | Applying initial value "0" on instance u_uart_slave.u_uart_slave_rx.shift_flag. @N:FX493 : | Applying initial value "0" on instance u_uart_slave.u_uart_slave_rx.div_end. @N:FX493 : | Applying initial value "00" on instance u_uart_slave.u_uart_slave_rx.rx_reg[1:0]. @N:FX493 : | Applying initial value "0000" on instance u_uart_slave.u_uart_slave_tx.bit_num[3:0]. @N:FX493 : | Applying initial value "000000000000000000000000" on instance u_uart_slave.u_uart_slave_tx.div_cnt[23:0]. @N:FX493 : | Applying initial value "1" on instance u_uart_slave.u_uart_slave_tx.tx_reg. @N:FX493 : | Applying initial value "0000" on instance u_uart_slave.u_uart_slave_tx.cnt_n[3:0]. @N:FX493 : | Applying initial value "0" on instance u_uart_slave.u_uart_slave_tx.busy_n. @N:FX493 : | Applying initial value "0" on instance u_uart_slave.u_uart_slave_tx.shift_flag. @N:FX493 : | Applying initial value "0" on instance u_uart_slave.u_uart_slave_tx.div_end. @N:FX493 : | Applying initial value "00000000000" on instance u_uart_slave.u_uart_slave_tx.shift_data[10:0]. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) @N:BN362 : uart_slave.v(293) | Removing sequential instance shift_data[10] (in view: work.uart_slave_tx(verilog)) because it does not drive other instances. Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 192MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -1.84ns 167 / 98 2 0h:00m:00s -1.84ns 166 / 98 3 0h:00m:00s -2.10ns 167 / 98 4 0h:00m:00s -2.10ns 167 / 98 5 0h:00m:00s -2.10ns 167 / 98 6 0h:00m:00s -2.10ns 167 / 98 @N:FX271 : uart_slave.v(312) | Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[0] (in view: work.gw_uart_slave(verilog)) with 8 loads 1 time to improve timing. @N:FX271 : uart_slave.v(312) | Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[2] (in view: work.gw_uart_slave(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : uart_slave.v(147) | Replicating instance u_uart_slave.u_uart_slave_rx.cnt_n[0] (in view: work.gw_uart_slave(verilog)) with 4 loads 1 time to improve timing. @N:FX271 : uart_slave.v(312) | Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[1] (in view: work.gw_uart_slave(verilog)) with 10 loads 1 time to improve timing. Timing driven replication report Added 4 Registers via timing driven replication Added 4 LUTs via timing driven replication 7 0h:00m:01s -1.69ns 172 / 102 8 0h:00m:01s -1.48ns 173 / 102 @N:FX271 : uart_slave.v(312) | Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[3] (in view: work.gw_uart_slave(verilog)) with 8 loads 1 time to improve timing. Timing driven replication report Added 1 Registers via timing driven replication Added 1 LUTs via timing driven replication 9 0h:00m:01s -1.84ns 172 / 103 10 0h:00m:01s -2.10ns 172 / 103 11 0h:00m:01s -2.10ns 172 / 103 12 0h:00m:01s -2.10ns 172 / 103 13 0h:00m:01s -2.10ns 172 / 103 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 121MB peak: 194MB) Writing Analyst data base D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\impl\synthesize\rev_1\synwork\gw_uart_slave_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 194MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 194MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 194MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 194MB) @W:MT420 : | Found inferred clock gw_uart_slave|SCLK with period 5.78ns. Please declare a user-defined clock on port SCLK. ##### START OF TIMING REPORT #####[ # Timing report written on Wed Sep 18 18:28:20 2019 # Top view: gw_uart_slave Requested Frequency: 173.1 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.019 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------- gw_uart_slave|SCLK 173.1 MHz 147.2 MHz 5.776 6.795 -1.019 inferred Autoconstr_clkgroup_0 System 100.0 MHz 185.9 MHz 10.000 5.378 4.622 system system_clkgroup ============================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------- System gw_uart_slave|SCLK | 5.776 4.622 | No paths - | No paths - | No paths - gw_uart_slave|SCLK gw_uart_slave|SCLK | 5.776 -1.019 | No paths - | No paths - | No paths - =============================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: gw_uart_slave|SCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- u_uart_slave.u_uart_slave_tx.shift_data[5] gw_uart_slave|SCLK DFFCE Q shift_data[5] 0.367 -1.019 u_uart_slave.u_uart_slave_tx.bit_num_fast[3] gw_uart_slave|SCLK DFFP Q bit_num_fast[3] 0.367 -0.952 u_uart_slave.u_uart_slave_rx.div_cnt[6] gw_uart_slave|SCLK DFFC Q div_cnt[6] 0.367 -0.762 u_uart_slave.u_uart_slave_tx.shift_data[8] gw_uart_slave|SCLK DFFCE Q shift_data[8] 0.367 -0.742 u_uart_slave.u_uart_slave_rx.cnt_n[2] gw_uart_slave|SCLK DFFC Q cnt_n[2] 0.367 -0.740 u_uart_slave.u_uart_slave_rx.div_cnt[2] gw_uart_slave|SCLK DFFC Q div_cnt[2] 0.367 -0.695 u_uart_slave.u_uart_slave_rx.div_cnt[4] gw_uart_slave|SCLK DFFC Q div_cnt[4] 0.367 -0.695 u_uart_slave.u_uart_slave_rx.cnt_n[1] gw_uart_slave|SCLK DFFC Q cnt_n[1] 0.367 -0.673 u_uart_slave.u_uart_slave_rx.div_cnt[1] gw_uart_slave|SCLK DFFC Q div_cnt[1] 0.367 -0.628 u_uart_slave.u_uart_slave_rx.div_cnt[0] gw_uart_slave|SCLK DFFC Q div_cnt[0] 0.367 -0.573 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ u_uart_slave.u_uart_slave_tx.tx_reg_0 gw_uart_slave|SCLK DFFPE D tx_reg_3 5.643 -1.019 u_uart_slave.u_uart_slave_rx.cnt_en_0 gw_uart_slave|SCLK DFFCE CE un1_cnt_en7_1_mb 5.643 -0.762 u_uart_slave.u_uart_slave_rx.cnt_n[1] gw_uart_slave|SCLK DFFC D cnt_n_3[1] 5.643 -0.740 u_uart_slave.u_uart_slave_rx.cnt_n[3] gw_uart_slave|SCLK DFFC D cnt_n_3[3] 5.643 -0.740 u_uart_slave.u_uart_slave_tx.div_cnt[23] gw_uart_slave|SCLK DFFC D div_cnt_3[23] 5.643 -0.573 u_uart_slave.u_uart_slave_rx.div_cnt[23] gw_uart_slave|SCLK DFFC D div_cnt_3[23] 5.643 -0.573 u_uart_slave.u_uart_slave_rx.cnt_en_0 gw_uart_slave|SCLK DFFCE D cnt_en7_i 5.643 -0.552 u_uart_slave.u_uart_slave_rx.div_end_0 gw_uart_slave|SCLK DFFC D div_end8 5.643 -0.552 u_uart_slave.u_uart_slave_tx.div_cnt[22] gw_uart_slave|SCLK DFFC D div_cnt_3[22] 5.643 -0.516 u_uart_slave.u_uart_slave_rx.div_cnt[22] gw_uart_slave|SCLK DFFC D div_cnt_3[22] 5.643 -0.516 ============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.776 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.643 - Propagation time: 6.662 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.019 Number of logic level(s): 4 Starting point: u_uart_slave.u_uart_slave_tx.shift_data[5] / Q Ending point: u_uart_slave.u_uart_slave_tx.tx_reg_0 / D The start point is clocked by gw_uart_slave|SCLK [rising] on pin CLK The end point is clocked by gw_uart_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- u_uart_slave.u_uart_slave_tx.shift_data[5] DFFCE Q Out 0.367 0.367 - shift_data[5] Net - - 1.021 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1_N_2L1_0 LUT3 I1 In - 1.388 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1_N_2L1_0 LUT3 F Out 1.099 2.487 - tx_reg_3_u_N_2L1_1_N_2L1_0 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1 LUT4 I3 In - 3.253 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1 LUT4 F Out 0.626 3.879 - tx_reg_3_u_N_2L1_1 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1 LUT4 I3 In - 4.644 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1 LUT4 F Out 0.626 5.270 - tx_reg_3_u_1 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u LUT4 I3 In - 6.036 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u LUT4 F Out 0.626 6.662 - tx_reg_3 Net - - 0.000 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_0 DFFPE D In - 6.662 - ======================================================================================================================= Total path delay (propagation time + setup) of 6.795 is 3.477(51.2%) logic and 3.318(48.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.776 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.643 - Propagation time: 6.595 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.952 Number of logic level(s): 4 Starting point: u_uart_slave.u_uart_slave_tx.bit_num_fast[3] / Q Ending point: u_uart_slave.u_uart_slave_tx.tx_reg_0 / D The start point is clocked by gw_uart_slave|SCLK [rising] on pin CLK The end point is clocked by gw_uart_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- u_uart_slave.u_uart_slave_tx.bit_num_fast[3] DFFP Q Out 0.367 0.367 - bit_num_fast[3] Net - - 1.021 - 2 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1_N_2L1_0 LUT3 I0 In - 1.388 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1_N_2L1_0 LUT3 F Out 1.032 2.420 - tx_reg_3_u_N_2L1_1_N_2L1_0 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1 LUT4 I3 In - 3.186 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1 LUT4 F Out 0.626 3.812 - tx_reg_3_u_N_2L1_1 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1 LUT4 I3 In - 4.577 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1 LUT4 F Out 0.626 5.203 - tx_reg_3_u_1 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u LUT4 I3 In - 5.969 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u LUT4 F Out 0.626 6.595 - tx_reg_3 Net - - 0.000 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_0 DFFPE D In - 6.595 - ======================================================================================================================= Total path delay (propagation time + setup) of 6.728 is 3.410(50.7%) logic and 3.318(49.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.776 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.643 - Propagation time: 6.405 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.762 Number of logic level(s): 3 Starting point: u_uart_slave.u_uart_slave_rx.div_cnt[6] / Q Ending point: u_uart_slave.u_uart_slave_rx.cnt_en_0 / CE The start point is clocked by gw_uart_slave|SCLK [rising] on pin CLK The end point is clocked by gw_uart_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- u_uart_slave.u_uart_slave_rx.div_cnt[6] DFFC Q Out 0.367 0.367 - div_cnt[6] Net - - 1.021 - 3 u_uart_slave.u_uart_slave_rx.div_end8_19_9 LUT4 I1 In - 1.388 - u_uart_slave.u_uart_slave_rx.div_end8_19_9 LUT4 F Out 1.099 2.487 - div_end8_19_9 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_rx.div_end8_19 LUT4 I1 In - 3.253 - u_uart_slave.u_uart_slave_rx.div_end8_19 LUT4 F Out 1.099 4.352 - div_end8_19 Net - - 1.021 - 3 u_uart_slave.u_uart_slave_rx.un1_cnt_en7_1_mb LUT4 I0 In - 5.373 - u_uart_slave.u_uart_slave_rx.un1_cnt_en7_1_mb LUT4 F Out 1.032 6.405 - un1_cnt_en7_1_mb Net - - 0.000 - 1 u_uart_slave.u_uart_slave_rx.cnt_en_0 DFFCE CE In - 6.405 - ============================================================================================================= Total path delay (propagation time + setup) of 6.538 is 3.730(57.1%) logic and 2.808(42.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.776 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.643 - Propagation time: 6.385 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.742 Number of logic level(s): 4 Starting point: u_uart_slave.u_uart_slave_tx.shift_data[8] / Q Ending point: u_uart_slave.u_uart_slave_tx.tx_reg_0 / D The start point is clocked by gw_uart_slave|SCLK [rising] on pin CLK The end point is clocked by gw_uart_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- u_uart_slave.u_uart_slave_tx.shift_data[8] DFFCE Q Out 0.367 0.367 - shift_data[8] Net - - 1.021 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1_N_2L1_0 LUT3 I2 In - 1.388 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1_N_2L1_0 LUT3 F Out 0.822 2.210 - tx_reg_3_u_N_2L1_1_N_2L1_0 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1 LUT4 I3 In - 2.976 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1_1 LUT4 F Out 0.626 3.602 - tx_reg_3_u_N_2L1_1 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1 LUT4 I3 In - 4.367 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u_N_2L1 LUT4 F Out 0.626 4.993 - tx_reg_3_u_1 Net - - 0.766 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_3_u LUT4 I3 In - 5.759 - u_uart_slave.u_uart_slave_tx.tx_reg_3_u LUT4 F Out 0.626 6.385 - tx_reg_3 Net - - 0.000 - 1 u_uart_slave.u_uart_slave_tx.tx_reg_0 DFFPE D In - 6.385 - ======================================================================================================================= Total path delay (propagation time + setup) of 6.518 is 3.200(49.1%) logic and 3.318(50.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.776 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.643 - Propagation time: 6.383 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.740 Number of logic level(s): 3 Starting point: u_uart_slave.u_uart_slave_rx.cnt_n[2] / Q Ending point: u_uart_slave.u_uart_slave_rx.cnt_n[1] / D The start point is clocked by gw_uart_slave|SCLK [rising] on pin CLK The end point is clocked by gw_uart_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- u_uart_slave.u_uart_slave_rx.cnt_n[2] DFFC Q Out 0.367 0.367 - cnt_n[2] Net - - 1.021 - 4 u_uart_slave.u_uart_slave_rx.un1_cnt_n_2 LUT4 I1 In - 1.388 - u_uart_slave.u_uart_slave_rx.un1_cnt_n_2 LUT4 F Out 1.099 2.487 - un1_cnt_n_2 Net - - 1.021 - 5 u_uart_slave.u_uart_slave_rx.cnt_n9 LUT3 I2 In - 3.508 - u_uart_slave.u_uart_slave_rx.cnt_n9 LUT3 F Out 0.822 4.330 - cnt_n9 Net - - 1.021 - 2 u_uart_slave.u_uart_slave_rx.cnt_n_3[1] LUT4 I0 In - 5.351 - u_uart_slave.u_uart_slave_rx.cnt_n_3[1] LUT4 F Out 1.032 6.383 - cnt_n_3[1] Net - - 0.000 - 1 u_uart_slave.u_uart_slave_rx.cnt_n[1] DFFC D In - 6.383 - ======================================================================================================= Total path delay (propagation time + setup) of 6.516 is 3.453(53.0%) logic and 3.063(47.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------- RSTN_c_i System INV O RSTN_c_i 0.000 4.622 ========================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ u_uart_slave.u_uart_slave_tx.bit_num[1] System DFFP PRESET RSTN_c_i 5.643 4.622 u_uart_slave.u_uart_slave_tx.bit_num[3] System DFFP PRESET RSTN_c_i 5.643 4.622 u_uart_slave.u_uart_slave_tx.bit_num_fast[1] System DFFP PRESET RSTN_c_i 5.643 4.622 u_uart_slave.u_uart_slave_tx.bit_num_fast[3] System DFFP PRESET RSTN_c_i 5.643 4.622 ================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.776 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.643 - Propagation time: 1.021 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 4.622 Number of logic level(s): 0 Starting point: RSTN_c_i / O Ending point: u_uart_slave.u_uart_slave_tx.bit_num[1] / PRESET The start point is clocked by System [rising] The end point is clocked by gw_uart_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- RSTN_c_i INV O Out 0.000 0.000 - RSTN_c_i Net - - 1.021 - 103 u_uart_slave.u_uart_slave_tx.bit_num[1] DFFP PRESET In - 1.021 - ======================================================================================================== Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 194MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 194MB) --------------------------------------- Resource Usage Report for gw_uart_slave Mapping to part: gw1n_4lqfp144-6 Cell usage: ALU 48 uses DFFC 68 uses DFFCE 29 uses DFFP 4 uses DFFPE 2 uses GSR 1 use INV 1 use MUX2_LUT5 1 use LUT2 8 uses LUT3 68 uses LUT4 47 uses I/O ports: 4 I/O primitives: 4 IBUF 3 uses OBUF 1 use I/O Register bits: 0 Register bits not including I/Os: 103 of 3456 (2%) Total load per clock: gw_uart_slave|SCLK: 103 @S |Mapping Summary: Total LUTs: 123 (2%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 41MB peak: 194MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Wed Sep 18 18:28:21 2019 ###########################################################]