@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: BN680 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":312:4:312:9|Found conflicting initial value on the register bit_num[3:0]. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. 
@W: BN680 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":293:4:293:9|Found conflicting initial value on the register shift_data[10:0]. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. 
@W: BN132 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":223:4:223:9|Removing sequential instance u_uart_slave.u_uart_slave_tx.cnt_en_0 because it is equivalent to instance u_uart_slave.u_uart_slave_tx.busy_n_0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT529 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":100:4:100:9|Found inferred clock gw_uart_slave|SCLK which controls 99 sequential elements including u_uart_slave.u_uart_slave_rx.div_cnt[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
