@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "000000000000000000000000" on instance u_uart_slave.u_uart_slave_rx.div_cnt[23:0].
@N: FX493 |Applying initial value "0000" on instance u_uart_slave.u_uart_slave_rx.cnt_n[3:0].
@N: FX493 |Applying initial value "0" on instance u_uart_slave.u_uart_slave_rx.cnt_en.
@N: FX493 |Applying initial value "0000000000" on instance u_uart_slave.u_uart_slave_rx.shift_data_rx[9:0].
@N: FX493 |Applying initial value "0" on instance u_uart_slave.u_uart_slave_rx.shift_flag.
@N: FX493 |Applying initial value "0" on instance u_uart_slave.u_uart_slave_rx.div_end.
@N: FX493 |Applying initial value "00" on instance u_uart_slave.u_uart_slave_rx.rx_reg[1:0].
@N: FX493 |Applying initial value "0000" on instance u_uart_slave.u_uart_slave_tx.bit_num[3:0].
@N: FX493 |Applying initial value "000000000000000000000000" on instance u_uart_slave.u_uart_slave_tx.div_cnt[23:0].
@N: FX493 |Applying initial value "1" on instance u_uart_slave.u_uart_slave_tx.tx_reg.
@N: FX493 |Applying initial value "0000" on instance u_uart_slave.u_uart_slave_tx.cnt_n[3:0].
@N: FX493 |Applying initial value "0" on instance u_uart_slave.u_uart_slave_tx.busy_n.
@N: FX493 |Applying initial value "0" on instance u_uart_slave.u_uart_slave_tx.shift_flag.
@N: FX493 |Applying initial value "0" on instance u_uart_slave.u_uart_slave_tx.div_end.
@N: FX493 |Applying initial value "00000000000" on instance u_uart_slave.u_uart_slave_tx.shift_data[10:0].
@N: BN362 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":293:4:293:9|Removing sequential instance shift_data[10] (in view: work.uart_slave_tx(verilog)) because it does not drive other instances.
@N: FX271 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":312:4:312:9|Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[0] (in view: work.gw_uart_slave(verilog)) with 8 loads 1 time to improve timing.
@N: FX271 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":312:4:312:9|Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[2] (in view: work.gw_uart_slave(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":147:4:147:9|Replicating instance u_uart_slave.u_uart_slave_rx.cnt_n[0] (in view: work.gw_uart_slave(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":312:4:312:9|Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[1] (in view: work.gw_uart_slave(verilog)) with 10 loads 1 time to improve timing.
@N: FX271 :"d:\ip release\uart_sram\gowin_uart_refdesign_for_release_190918\gowin_uart_slave_refdesign\project\gw_uart_slave\src\uart_slave.v":312:4:312:9|Replicating instance u_uart_slave.u_uart_slave_tx.bit_num[3] (in view: work.gw_uart_slave(verilog)) with 8 loads 1 time to improve timing.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
