@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\uart_slave.v":49:7:49:19|Synthesizing module uart_slave_rx in library work.
@N: CG364 :"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\uart_slave.v":190:7:190:19|Synthesizing module uart_slave_tx in library work.
@N: CG364 :"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\uart_slave.v":8:7:8:16|Synthesizing module uart_slave in library work.
@N: CG364 :"D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\gw_uart_slave.v":3:7:3:19|Synthesizing module gw_uart_slave in library work.
@N|Running in 64-bit mode

