#--  Synopsys, Inc.
#--  Version O-2018.09G-SP1-1-Beta1
#--  Project file D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\impl\synthesize\rev_1\run_options.txt
#--  Written on Wed Sep 18 18:28:13 2019


#project files
add_file -verilog "D:/IP release/uart_sram/Gowin_UART_RefDesign_For_Release_190918/Gowin_UART_Slave_RefDesign/project/gw_uart_slave/src/gw_uart_slave.v"
add_file -verilog "D:/IP release/uart_sram/Gowin_UART_RefDesign_For_Release_190918/Gowin_UART_Slave_RefDesign/project/gw_uart_slave/src/uart_slave.v"
add_file -verilog "D:/IP release/uart_sram/Gowin_UART_RefDesign_For_Release_190918/Gowin_UART_Slave_RefDesign/project/gw_uart_slave/src/uart_slave_defines.vh"



#implementation: "rev_1"
impl -add rev_1 -type fpga

#device options
set_option -technology GOWIN-GW1N
set_option -part GW1N_4
set_option -package LQFP144
set_option -speed_grade -6
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "gw_uart_slave"

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# GOWIN-GW1N
set_option -maxfan 10000
set_option -rw_check_on_ram 1
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -run_prop_extract 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/gw_uart_slave.vm"
impl -active "rev_1"
