Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\impl\synthesize\rev_1\gw_uart_slave.vm
Physical Constraints File	D:\IP release\uart_sram\Gowin_UART_RefDesign_For_Release_190918\Gowin_UART_Slave_RefDesign\project\gw_uart_slave\src\gw_uart_slave.cst
Timing Constraint File	---
GOWIN version	V1.9.1.01Beta
Part Number	GW1N-LV4LQ144C6/I5
Created Time	Wed Sep 18 18:28:24 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	238
Numbers of Endpoints Analyzed	238
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	107.837(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.727	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[3]/Q	u_uart_slave/u_uart_slave_tx/tx_reg_0/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.673
2	2.685	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[12]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.715
3	2.694	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[16]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.706
4	3.048	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[18]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.352
5	3.112	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[10]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.288
6	3.152	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[15]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.248
7	3.158	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[8]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.242
8	3.197	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.203
9	3.226	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[14]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.174
10	3.283	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[13]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.117
11	3.290	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.110
12	3.292	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[10]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.108
13	3.300	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[8]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.100
14	3.301	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[14]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.099
15	3.311	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[4]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.089
16	3.312	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.088
17	3.314	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.086
18	3.348	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[12]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.052
19	3.361	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[19]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.039
20	3.368	u_uart_slave/u_uart_slave_tx/div_cnt_Z[2]/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.032
21	3.369	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[17]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.031
22	3.371	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	6.029
23	3.404	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[5]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	5.996
24	3.416	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[9]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	5.984
25	3.467	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[22]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	5.933

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.568	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[5]/Q	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.568
2	0.568	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[4]/Q	u_uart_slave/u_uart_slave_rx/data_rx[2]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.568
3	0.571	u_uart_slave/u_uart_slave_rx/rx_reg_Z[0]/Q	u_uart_slave/u_uart_slave_rx/rx_reg_Z[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.571
4	0.708	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/Q	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.708
5	0.709	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]/Q	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
6	0.709	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]/Q	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
7	0.709	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]/Q	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
8	0.709	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/Q	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
9	0.709	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/Q	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
10	0.710	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]/Q	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.710
11	0.833	u_uart_slave/u_uart_slave_rx/data_rx[1]/Q	u_uart_slave/u_uart_slave_tx/shift_data_Z[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.833
12	0.833	u_uart_slave/u_uart_slave_rx/data_rx[5]/Q	u_uart_slave/u_uart_slave_tx/shift_data_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.833
13	0.870	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.885
14	0.870	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[7]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.885
15	0.870	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[8]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.885
16	0.870	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[9]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.885
17	0.893	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/Q	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.893
18	0.894	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]/Q	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.894
19	0.895	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/Q	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.895
20	0.904	u_uart_slave/u_uart_slave_rx/data_rx[4]/Q	u_uart_slave/u_uart_slave_tx/shift_data_Z[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.904
21	0.943	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/Q	u_uart_slave/u_uart_slave_rx/cnt_n_Z[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.943
22	0.943	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/Q	u_uart_slave/u_uart_slave_rx/cnt_n_Z[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.943
23	0.953	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/Q	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.953
24	0.967	u_uart_slave/u_uart_slave_tx/div_end_0/Q	u_uart_slave/u_uart_slave_tx/div_cnt_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.967
25	0.979	u_uart_slave/u_uart_slave_rx/cnt_en_0/Q	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.979

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]
2	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_rx/div_end_0
3	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]
4	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]
5	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]
6	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_tx/div_cnt_Z[16]
7	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_tx/div_end_0
8	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]
9	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_tx/shift_flag_0
10	2.329	3.579	1.250	Low Pulse Width	DEFAULT_CLK	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.727
Data Arrival Time	13.043
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[3]
To	u_uart_slave/u_uart_slave_tx/tx_reg_0
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R13C8[1][B]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[3]/CLK
4.828	0.458	tC2Q	RF	2	R13C8[1][B]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[3]/Q
5.805	0.977	tNET	FF	1	R11C6[1][B]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u_N_2L1_1_N_2L1_0_cZ/I0
6.904	1.099	tINS	FF	1	R11C6[1][B]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u_N_2L1_1_N_2L1_0_cZ/F
7.725	0.821	tNET	FF	1	R11C8[0][A]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u_N_2L1_1_cZ/I3
8.527	0.802	tINS	FR	1	R11C8[0][A]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u_N_2L1_1_cZ/F
8.946	0.419	tNET	RR	1	R11C9[1][A]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u_N_2L1/I3
9.572	0.626	tINS	RF	1	R11C9[1][A]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u_N_2L1/F
9.908	0.336	tNET	FF	1	R11C9[0][B]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u/I3
10.940	1.032	tINS	FF	1	R11C9[0][B]	u_uart_slave/u_uart_slave_tx/tx_reg_3_u/F
13.043	2.103	tNET	FF	1	IOT14[B]	u_uart_slave/u_uart_slave_tx/tx_reg_0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	IOT14[B]	u_uart_slave/u_uart_slave_tx/tx_reg_0/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/tx_reg_0
13.770	-0.400	tSu		1	IOT14[B]	u_uart_slave/u_uart_slave_tx/tx_reg_0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.559, 41.034%; route: 4.656, 53.681%; tC2Q: 0.458, 5.284%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path2

Path Summary:

Slack	2.685
Data Arrival Time	11.085
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[12]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.527	0.563	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/SUM
9.986	1.459	tNET	FF	1	R7C10[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[12]/I0
11.085	1.099	tINS	FF	1	R7C10[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[12]/F
11.085	0.000	tNET	FF	1	R7C10[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[12]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C10[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[12]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[12]
13.770	-0.400	tSu		1	R7C10[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[12]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.334, 49.651%; route: 2.923, 43.523%; tC2Q: 0.458, 6.826%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path3

Path Summary:

Slack	2.694
Data Arrival Time	11.075
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[16]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.192	0.057	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/COUT
8.192	0.000	tNET	FF	2	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/CIN
8.755	0.563	tINS	FF	1	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/SUM
10.043	1.289	tNET	FF	1	R8C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[16]/I0
11.075	1.032	tINS	FF	1	R8C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[16]/F
11.075	0.000	tNET	FF	1	R8C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[16]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R8C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[16]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[16]
13.770	-0.400	tSu		1	R8C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[16]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.495, 52.120%; route: 2.752, 41.045%; tC2Q: 0.458, 6.835%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path4

Path Summary:

Slack	3.048
Data Arrival Time	10.721
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[18]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.192	0.057	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/COUT
8.192	0.000	tNET	FF	2	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/CIN
8.249	0.057	tINS	FF	1	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/COUT
8.249	0.000	tNET	FF	2	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/CIN
8.306	0.057	tINS	FF	1	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/COUT
8.306	0.000	tNET	FF	2	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/CIN
8.869	0.563	tINS	FF	1	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/SUM
9.689	0.821	tNET	FF	1	R8C6[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[18]/I0
10.721	1.032	tINS	FF	1	R8C6[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[18]/F
10.721	0.000	tNET	FF	1	R8C6[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[18]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R8C6[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[18]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[18]
13.770	-0.400	tSu		1	R8C6[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[18]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.609, 56.821%; route: 2.284, 35.963%; tC2Q: 0.458, 7.216%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path5

Path Summary:

Slack	3.112
Data Arrival Time	10.658
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[10]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
8.413	0.563	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/SUM
10.032	1.620	tNET	FF	1	R7C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[10]/I0
10.658	0.626	tINS	FF	1	R7C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[10]/F
10.658	0.000	tNET	FF	1	R7C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[10]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[10]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[10]
13.770	-0.400	tSu		1	R7C8[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[10]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 2.747, 43.683%; route: 3.083, 49.028%; tC2Q: 0.458, 7.289%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path6

Path Summary:

Slack	3.152
Data Arrival Time	10.617
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[15]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.698	0.563	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/SUM
9.518	0.821	tNET	FF	1	R7C7[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[15]/I0
10.617	1.099	tINS	FF	1	R7C7[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[15]/F
10.617	0.000	tNET	FF	1	R7C7[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[15]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C7[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[15]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[15]
13.770	-0.400	tSu		1	R7C7[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[15]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.505, 56.102%; route: 2.284, 36.562%; tC2Q: 0.458, 7.336%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path7

Path Summary:

Slack	3.158
Data Arrival Time	10.611
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[8]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/CLK
4.828	0.458	tC2Q	RF	3	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q
6.455	1.626	tNET	FF	2	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/I0
7.500	1.045	tINS	FF	1	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/COUT
7.500	0.000	tNET	FF	2	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/CIN
7.557	0.057	tINS	FF	1	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/COUT
7.557	0.000	tNET	FF	2	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/CIN
7.614	0.057	tINS	FF	1	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/COUT
7.614	0.000	tNET	FF	2	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/CIN
7.671	0.057	tINS	FF	1	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/COUT
7.671	0.000	tNET	FF	2	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/CIN
7.728	0.057	tINS	FF	1	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/COUT
7.728	0.000	tNET	FF	2	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/CIN
8.291	0.563	tINS	FF	1	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/SUM
9.579	1.289	tNET	FF	1	R14C9[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[8]/I0
10.611	1.032	tINS	FF	1	R14C9[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[8]/F
10.611	0.000	tNET	FF	1	R14C9[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[8]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R14C9[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[8]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[8]
13.770	-0.400	tSu		1	R14C9[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[8]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 2.868, 45.949%; route: 2.915, 46.708%; tC2Q: 0.458, 7.343%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path8

Path Summary:

Slack	3.197
Data Arrival Time	10.572
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
8.185	0.563	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/SUM
9.473	1.289	tNET	FF	1	R7C9[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[6]/I0
10.572	1.099	tINS	FF	1	R7C9[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[6]/F
10.572	0.000	tNET	FF	1	R7C9[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C9[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]
13.770	-0.400	tSu		1	R7C9[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 2.992, 48.238%; route: 2.752, 44.373%; tC2Q: 0.458, 7.389%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path9

Path Summary:

Slack	3.226
Data Arrival Time	10.544
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[14]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.641	0.563	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/SUM
9.445	0.804	tNET	FF	1	R7C8[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[14]/I0
10.544	1.099	tINS	FF	1	R7C8[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[14]/F
10.544	0.000	tNET	FF	1	R7C8[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[14]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C8[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[14]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[14]
13.770	-0.400	tSu		1	R7C8[2][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[14]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.448, 55.846%; route: 2.268, 36.730%; tC2Q: 0.458, 7.424%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path10

Path Summary:

Slack	3.283
Data Arrival Time	10.487
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[13]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.584	0.563	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/SUM
9.388	0.804	tNET	FF	1	R7C8[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[13]/I0
10.487	1.099	tINS	FF	1	R7C8[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[13]/F
10.487	0.000	tNET	FF	1	R7C8[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[13]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C8[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[13]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[13]
13.770	-0.400	tSu		1	R7C8[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[13]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.391, 55.435%; route: 2.268, 37.072%; tC2Q: 0.458, 7.493%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path11

Path Summary:

Slack	3.290
Data Arrival Time	10.480
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
8.242	0.563	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/SUM
9.381	1.139	tNET	FF	1	R7C10[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[7]/I0
10.480	1.099	tINS	FF	1	R7C10[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[7]/F
10.480	0.000	tNET	FF	1	R7C10[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C10[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]
13.770	-0.400	tSu		1	R7C10[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.049, 49.903%; route: 2.603, 42.596%; tC2Q: 0.458, 7.502%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path12

Path Summary:

Slack	3.292
Data Arrival Time	10.478
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[10]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/CLK
4.828	0.458	tC2Q	RF	3	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q
6.455	1.626	tNET	FF	2	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/I0
7.500	1.045	tINS	FF	1	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/COUT
7.500	0.000	tNET	FF	2	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/CIN
7.557	0.057	tINS	FF	1	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/COUT
7.557	0.000	tNET	FF	2	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/CIN
7.614	0.057	tINS	FF	1	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/COUT
7.614	0.000	tNET	FF	2	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/CIN
7.671	0.057	tINS	FF	1	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/COUT
7.671	0.000	tNET	FF	2	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/CIN
7.728	0.057	tINS	FF	1	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/COUT
7.728	0.000	tNET	FF	2	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/CIN
7.785	0.057	tINS	FF	1	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/COUT
7.785	0.000	tNET	FF	2	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/CIN
7.842	0.057	tINS	FF	1	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/COUT
7.842	0.000	tNET	FF	2	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/CIN
8.405	0.563	tINS	FF	1	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/SUM
9.379	0.975	tNET	FF	1	R14C8[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[10]/I0
10.478	1.099	tINS	FF	1	R14C8[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[10]/F
10.478	0.000	tNET	FF	1	R14C8[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[10]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R14C8[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[10]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[10]
13.770	-0.400	tSu		1	R14C8[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[10]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.049, 49.915%; route: 2.601, 42.581%; tC2Q: 0.458, 7.503%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path13

Path Summary:

Slack	3.300
Data Arrival Time	10.470
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[8]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
8.299	0.563	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/SUM
9.438	1.139	tNET	FF	1	R7C10[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[8]/I0
10.470	1.032	tINS	FF	1	R7C10[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[8]/F
10.470	0.000	tNET	FF	1	R7C10[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[8]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C10[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[8]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[8]
13.770	-0.400	tSu		1	R7C10[1][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[8]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.039, 49.821%; route: 2.603, 42.665%; tC2Q: 0.458, 7.514%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path14

Path Summary:

Slack	3.301
Data Arrival Time	10.469
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[14]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/CLK
4.828	0.458	tC2Q	RF	3	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q
6.455	1.626	tNET	FF	2	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/I0
7.500	1.045	tINS	FF	1	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/COUT
7.500	0.000	tNET	FF	2	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/CIN
7.557	0.057	tINS	FF	1	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/COUT
7.557	0.000	tNET	FF	2	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/CIN
7.614	0.057	tINS	FF	1	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/COUT
7.614	0.000	tNET	FF	2	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/CIN
7.671	0.057	tINS	FF	1	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/COUT
7.671	0.000	tNET	FF	2	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/CIN
7.728	0.057	tINS	FF	1	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/COUT
7.728	0.000	tNET	FF	2	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/CIN
7.785	0.057	tINS	FF	1	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/COUT
7.785	0.000	tNET	FF	2	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/CIN
7.842	0.057	tINS	FF	1	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/COUT
7.842	0.000	tNET	FF	2	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/CIN
7.899	0.057	tINS	FF	1	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/COUT
7.899	0.000	tNET	FF	2	R14C5[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_11_0/CIN
7.956	0.057	tINS	FF	1	R14C5[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_11_0/COUT
7.956	0.000	tNET	FF	2	R14C5[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_12_0/CIN
8.013	0.057	tINS	FF	1	R14C5[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_12_0/COUT
8.013	0.000	tNET	FF	2	R14C5[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_13_0/CIN
8.070	0.057	tINS	FF	1	R14C5[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_13_0/COUT
8.070	0.000	tNET	FF	2	R14C5[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_14_0/CIN
8.633	0.563	tINS	FF	1	R14C5[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_14_0/SUM
9.437	0.804	tNET	FF	1	R14C8[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[14]/I0
10.469	1.032	tINS	FF	1	R14C8[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[14]/F
10.469	0.000	tNET	FF	1	R14C8[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[14]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R14C8[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[14]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[14]
13.770	-0.400	tSu		1	R14C8[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[14]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.210, 52.631%; route: 2.431, 39.855%; tC2Q: 0.458, 7.515%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path15

Path Summary:

Slack	3.311
Data Arrival Time	10.458
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[4]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
8.071	0.563	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/SUM
9.359	1.289	tNET	FF	1	R7C9[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[4]/I0
10.458	1.099	tINS	FF	1	R7C9[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[4]/F
10.458	0.000	tNET	FF	1	R7C9[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C9[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[4]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[4]
13.770	-0.400	tSu		1	R7C9[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[4]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 2.878, 47.268%; route: 2.752, 45.204%; tC2Q: 0.458, 7.528%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path16

Path Summary:

Slack	3.312
Data Arrival Time	10.457
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/CLK
4.828	0.458	tC2Q	RF	3	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q
6.455	1.626	tNET	FF	2	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/I0
7.500	1.045	tINS	FF	1	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/COUT
7.500	0.000	tNET	FF	2	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/CIN
7.557	0.057	tINS	FF	1	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/COUT
7.557	0.000	tNET	FF	2	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/CIN
7.614	0.057	tINS	FF	1	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/COUT
7.614	0.000	tNET	FF	2	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/CIN
7.671	0.057	tINS	FF	1	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/COUT
7.671	0.000	tNET	FF	2	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/CIN
7.728	0.057	tINS	FF	1	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/COUT
7.728	0.000	tNET	FF	2	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/CIN
7.785	0.057	tINS	FF	1	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/COUT
7.785	0.000	tNET	FF	2	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/CIN
7.842	0.057	tINS	FF	1	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/COUT
7.842	0.000	tNET	FF	2	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/CIN
7.899	0.057	tINS	FF	1	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/COUT
7.899	0.000	tNET	FF	2	R14C5[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_11_0/CIN
7.956	0.057	tINS	FF	1	R14C5[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_11_0/COUT
7.956	0.000	tNET	FF	2	R14C5[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_12_0/CIN
8.013	0.057	tINS	FF	1	R14C5[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_12_0/COUT
8.013	0.000	tNET	FF	2	R14C5[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_13_0/CIN
8.070	0.057	tINS	FF	1	R14C5[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_13_0/COUT
8.070	0.000	tNET	FF	2	R14C5[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_14_0/CIN
8.127	0.057	tINS	FF	1	R14C5[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_14_0/COUT
8.127	0.000	tNET	FF	2	R14C5[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_15_0/CIN
8.184	0.057	tINS	FF	1	R14C5[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_15_0/COUT
8.184	0.000	tNET	FF	2	R14C6[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_16_0/CIN
8.241	0.057	tINS	FF	1	R14C6[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_16_0/COUT
8.241	0.000	tNET	FF	2	R14C6[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_17_0/CIN
8.298	0.057	tINS	FF	1	R14C6[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_17_0/COUT
8.298	0.000	tNET	FF	2	R14C6[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_18_0/CIN
8.355	0.057	tINS	FF	1	R14C6[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_18_0/COUT
8.355	0.000	tNET	FF	2	R14C6[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_19_0/CIN
8.412	0.057	tINS	FF	1	R14C6[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_19_0/COUT
8.412	0.000	tNET	FF	2	R14C6[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_20_0/CIN
8.940	0.528	tINS	FR	1	R14C6[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_20_0/SUM
9.358	0.419	tNET	RR	1	R14C7[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[20]/I0
10.457	1.099	tINS	RF	1	R14C7[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[20]/F
10.457	0.000	tNET	FF	1	R14C7[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R14C7[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[20]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[20]
13.770	-0.400	tSu		1	R14C7[2][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.584, 58.873%; route: 2.045, 33.598%; tC2Q: 0.458, 7.529%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path17

Path Summary:

Slack	3.314
Data Arrival Time	10.455
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.192	0.057	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/COUT
8.192	0.000	tNET	FF	2	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/CIN
8.249	0.057	tINS	FF	1	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/COUT
8.249	0.000	tNET	FF	2	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/CIN
8.306	0.057	tINS	FF	1	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/COUT
8.306	0.000	tNET	FF	2	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/CIN
8.363	0.057	tINS	FF	1	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/COUT
8.363	0.000	tNET	FF	2	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/CIN
8.420	0.057	tINS	FF	1	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/COUT
8.420	0.000	tNET	FF	2	R7C6[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_20_0/CIN
8.477	0.057	tINS	FF	1	R7C6[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_20_0/COUT
8.477	0.000	tNET	FF	2	R7C6[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_21_0/CIN
9.005	0.528	tINS	FR	1	R7C6[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_21_0/SUM
9.423	0.419	tNET	RR	1	R8C6[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[21]/I0
10.455	1.032	tINS	RF	1	R8C6[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[21]/F
10.455	0.000	tNET	FF	1	R8C6[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R8C6[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]
13.770	-0.400	tSu		1	R8C6[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.745, 61.539%; route: 1.882, 30.930%; tC2Q: 0.458, 7.531%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path18

Path Summary:

Slack	3.348
Data Arrival Time	10.422
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[12]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/CLK
4.828	0.458	tC2Q	RF	3	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q
6.455	1.626	tNET	FF	2	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/I0
7.500	1.045	tINS	FF	1	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/COUT
7.500	0.000	tNET	FF	2	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/CIN
7.557	0.057	tINS	FF	1	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/COUT
7.557	0.000	tNET	FF	2	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/CIN
7.614	0.057	tINS	FF	1	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/COUT
7.614	0.000	tNET	FF	2	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/CIN
7.671	0.057	tINS	FF	1	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/COUT
7.671	0.000	tNET	FF	2	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/CIN
7.728	0.057	tINS	FF	1	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/COUT
7.728	0.000	tNET	FF	2	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/CIN
7.785	0.057	tINS	FF	1	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/COUT
7.785	0.000	tNET	FF	2	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/CIN
7.842	0.057	tINS	FF	1	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/COUT
7.842	0.000	tNET	FF	2	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/CIN
7.899	0.057	tINS	FF	1	R14C5[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_10_0/COUT
7.899	0.000	tNET	FF	2	R14C5[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_11_0/CIN
7.956	0.057	tINS	FF	1	R14C5[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_11_0/COUT
7.956	0.000	tNET	FF	2	R14C5[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_12_0/CIN
8.519	0.563	tINS	FF	1	R14C5[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_12_0/SUM
9.323	0.804	tNET	FF	1	R14C8[0][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[12]/I0
10.422	1.099	tINS	FF	1	R14C8[0][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[12]/F
10.422	0.000	tNET	FF	1	R14C8[0][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[12]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R14C8[0][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[12]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[12]
13.770	-0.400	tSu		1	R14C8[0][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[12]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.163, 52.263%; route: 2.431, 40.164%; tC2Q: 0.458, 7.573%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path19

Path Summary:

Slack	3.361
Data Arrival Time	10.408
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[19]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.192	0.057	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/COUT
8.192	0.000	tNET	FF	2	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/CIN
8.249	0.057	tINS	FF	1	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/COUT
8.249	0.000	tNET	FF	2	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/CIN
8.306	0.057	tINS	FF	1	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/COUT
8.306	0.000	tNET	FF	2	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/CIN
8.363	0.057	tINS	FF	1	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/COUT
8.363	0.000	tNET	FF	2	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/CIN
8.891	0.528	tINS	FR	1	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/SUM
9.309	0.419	tNET	RR	1	R8C6[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[19]/I0
10.408	1.099	tINS	RF	1	R8C6[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[19]/F
10.408	0.000	tNET	FF	1	R8C6[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[19]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R8C6[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[19]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[19]
13.770	-0.400	tSu		1	R8C6[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[19]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.698, 61.239%; route: 1.882, 31.171%; tC2Q: 0.458, 7.590%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path20

Path Summary:

Slack	3.368
Data Arrival Time	10.402
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/div_cnt_Z[2]
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R12C6[0][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[2]/CLK
4.828	0.458	tC2Q	RF	3	R12C6[0][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[2]/Q
6.138	1.310	tNET	FF	2	R14C3[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_2_0/I0
7.183	1.045	tINS	FF	1	R14C3[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_2_0/COUT
7.183	0.000	tNET	FF	2	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/CIN
7.746	0.563	tINS	FF	1	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/SUM
9.370	1.624	tNET	FF	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[3]/I0
10.402	1.032	tINS	FF	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[3]/F
10.402	0.000	tNET	FF	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
13.770	-0.400	tSu		1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 2.640, 43.765%; route: 2.934, 48.637%; tC2Q: 0.458, 7.598%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path21

Path Summary:

Slack	3.369
Data Arrival Time	10.401
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[17]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.192	0.057	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/COUT
8.192	0.000	tNET	FF	2	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/CIN
8.249	0.057	tINS	FF	1	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/COUT
8.249	0.000	tNET	FF	2	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/CIN
8.812	0.563	tINS	FF	1	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/SUM
9.302	0.490	tNET	FF	1	R8C6[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[17]/I0
10.401	1.099	tINS	FF	1	R8C6[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[17]/F
10.401	0.000	tNET	FF	1	R8C6[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[17]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R8C6[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[17]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[17]
13.770	-0.400	tSu		1	R8C6[0][B]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[17]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.619, 60.009%; route: 1.953, 32.391%; tC2Q: 0.458, 7.600%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path22

Path Summary:

Slack	3.371
Data Arrival Time	10.398
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.192	0.057	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/COUT
8.192	0.000	tNET	FF	2	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/CIN
8.249	0.057	tINS	FF	1	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/COUT
8.249	0.000	tNET	FF	2	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/CIN
8.306	0.057	tINS	FF	1	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/COUT
8.306	0.000	tNET	FF	2	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/CIN
8.363	0.057	tINS	FF	1	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/COUT
8.363	0.000	tNET	FF	2	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/CIN
8.420	0.057	tINS	FF	1	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/COUT
8.420	0.000	tNET	FF	2	R7C6[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_20_0/CIN
8.948	0.528	tINS	FR	1	R7C6[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_20_0/SUM
9.366	0.419	tNET	RR	1	R8C6[2][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[20]/I0
10.398	1.032	tINS	RF	1	R8C6[2][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[20]/F
10.398	0.000	tNET	FF	1	R8C6[2][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R8C6[2][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[20]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[20]
13.770	-0.400	tSu		1	R8C6[2][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.688, 61.175%; route: 1.882, 31.222%; tC2Q: 0.458, 7.603%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path23

Path Summary:

Slack	3.404
Data Arrival Time	10.366
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[5]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
8.128	0.563	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/SUM
9.267	1.139	tNET	FF	1	R7C10[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[5]/I0
10.366	1.099	tINS	FF	1	R7C10[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[5]/F
10.366	0.000	tNET	FF	1	R7C10[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[5]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R7C10[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[5]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[5]
13.770	-0.400	tSu		1	R7C10[1][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[5]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 2.935, 48.950%; route: 2.603, 43.405%; tC2Q: 0.458, 7.644%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path24

Path Summary:

Slack	3.416
Data Arrival Time	10.354
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[9]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/CLK
4.828	0.458	tC2Q	RF	3	R12C9[1][B]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[3]/Q
6.455	1.626	tNET	FF	2	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/I0
7.500	1.045	tINS	FF	1	R14C3[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_3_0/COUT
7.500	0.000	tNET	FF	2	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/CIN
7.557	0.057	tINS	FF	1	R14C4[0][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_4_0/COUT
7.557	0.000	tNET	FF	2	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/CIN
7.614	0.057	tINS	FF	1	R14C4[0][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_5_0/COUT
7.614	0.000	tNET	FF	2	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/CIN
7.671	0.057	tINS	FF	1	R14C4[1][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_6_0/COUT
7.671	0.000	tNET	FF	2	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/CIN
7.728	0.057	tINS	FF	1	R14C4[1][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_7_0/COUT
7.728	0.000	tNET	FF	2	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/CIN
7.785	0.057	tINS	FF	1	R14C4[2][A]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_8_0/COUT
7.785	0.000	tNET	FF	2	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/CIN
8.348	0.563	tINS	FF	1	R14C4[2][B]	u_uart_slave/u_uart_slave_tx/un6_div_cnt_cry_9_0/SUM
9.322	0.975	tNET	FF	1	R14C8[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[9]/I0
10.354	1.032	tINS	FF	1	R14C8[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[9]/F
10.354	0.000	tNET	FF	1	R14C8[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[9]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R14C8[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[9]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[9]
13.770	-0.400	tSu		1	R14C8[0][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[9]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 2.925, 48.877%; route: 2.601, 43.464%; tC2Q: 0.458, 7.659%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Path25

Path Summary:

Slack	3.467
Data Arrival Time	10.302
Data Required Time	13.770
From	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[22]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
4.370	3.388	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
4.828	0.458	tC2Q	RF	3	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/Q
6.292	1.463	tNET	FF	2	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/I0
7.337	1.045	tINS	FF	1	R7C3[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_0_0/COUT
7.337	0.000	tNET	FF	2	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/CIN
7.394	0.057	tINS	FF	1	R7C3[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_1_0/COUT
7.394	0.000	tNET	FF	2	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/CIN
7.451	0.057	tINS	FF	1	R7C3[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_2_0/COUT
7.451	0.000	tNET	FF	2	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/CIN
7.508	0.057	tINS	FF	1	R7C3[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_3_0/COUT
7.508	0.000	tNET	FF	2	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/CIN
7.565	0.057	tINS	FF	1	R7C4[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_4_0/COUT
7.565	0.000	tNET	FF	2	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/CIN
7.622	0.057	tINS	FF	1	R7C4[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_5_0/COUT
7.622	0.000	tNET	FF	2	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/CIN
7.679	0.057	tINS	FF	1	R7C4[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_6_0/COUT
7.679	0.000	tNET	FF	2	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/CIN
7.736	0.057	tINS	FF	1	R7C4[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_7_0/COUT
7.736	0.000	tNET	FF	2	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/CIN
7.793	0.057	tINS	FF	1	R7C4[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_8_0/COUT
7.793	0.000	tNET	FF	2	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/CIN
7.850	0.057	tINS	FF	1	R7C4[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_9_0/COUT
7.850	0.000	tNET	FF	2	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/CIN
7.907	0.057	tINS	FF	1	R7C5[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_10_0/COUT
7.907	0.000	tNET	FF	2	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/CIN
7.964	0.057	tINS	FF	1	R7C5[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_11_0/COUT
7.964	0.000	tNET	FF	2	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/CIN
8.021	0.057	tINS	FF	1	R7C5[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_12_0/COUT
8.021	0.000	tNET	FF	2	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/CIN
8.078	0.057	tINS	FF	1	R7C5[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_13_0/COUT
8.078	0.000	tNET	FF	2	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/CIN
8.135	0.057	tINS	FF	1	R7C5[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_14_0/COUT
8.135	0.000	tNET	FF	2	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/CIN
8.192	0.057	tINS	FF	1	R7C5[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_15_0/COUT
8.192	0.000	tNET	FF	2	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/CIN
8.249	0.057	tINS	FF	1	R7C6[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_16_0/COUT
8.249	0.000	tNET	FF	2	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/CIN
8.306	0.057	tINS	FF	1	R7C6[0][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_17_0/COUT
8.306	0.000	tNET	FF	2	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/CIN
8.363	0.057	tINS	FF	1	R7C6[1][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_18_0/COUT
8.363	0.000	tNET	FF	2	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/CIN
8.420	0.057	tINS	FF	1	R7C6[1][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_19_0/COUT
8.420	0.000	tNET	FF	2	R7C6[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_20_0/CIN
8.477	0.057	tINS	FF	1	R7C6[2][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_20_0/COUT
8.477	0.000	tNET	FF	2	R7C6[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_21_0/CIN
8.534	0.057	tINS	FF	1	R7C6[2][B]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_21_0/COUT
8.534	0.000	tNET	FF	2	R7C7[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_22_0/CIN
9.062	0.528	tINS	FR	1	R7C7[0][A]	u_uart_slave/u_uart_slave_rx/un6_div_cnt_cry_22_0/SUM
9.480	0.419	tNET	RR	1	R8C7[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[22]/I0
10.302	0.822	tINS	RF	1	R8C7[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[22]/F
10.302	0.000	tNET	FF	1	R8C7[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[22]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
14.370	3.388	tNET	RR	1	R8C7[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[22]/CLK
14.170	-0.200	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[22]
13.770	-0.400	tSu		1	R8C7[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[22]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%
Arrival Data Path Delay	cell: 3.592, 60.547%; route: 1.882, 31.728%; tC2Q: 0.458, 7.726%
Required Clock Path Delay	cell: 0.982, 22.470%; route: 3.388, 77.530%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.568
Data Arrival Time	3.927
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[5]
To	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C8[1][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[5]/CLK
3.693	0.333	tC2Q	RF	2	R9C8[1][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[5]/Q
3.927	0.234	tNET	FF	1	R9C7[0][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C7[0][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]
3.359	0.000	tHld		1	R9C7[0][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 41.295%; tC2Q: 0.333, 58.705%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path2

Path Summary:

Slack	0.568
Data Arrival Time	3.927
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[4]
To	u_uart_slave/u_uart_slave_rx/data_rx[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C8[1][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[4]/CLK
3.693	0.333	tC2Q	RF	2	R9C8[1][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[4]/Q
3.927	0.234	tNET	FF	1	R9C9[0][A]	u_uart_slave/u_uart_slave_rx/data_rx[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C9[0][A]	u_uart_slave/u_uart_slave_rx/data_rx[2]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/data_rx[2]
3.359	0.000	tHld		1	R9C9[0][A]	u_uart_slave/u_uart_slave_rx/data_rx[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 41.295%; tC2Q: 0.333, 58.705%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path3

Path Summary:

Slack	0.571
Data Arrival Time	3.930
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/rx_reg_Z[0]
To	u_uart_slave/u_uart_slave_rx/rx_reg_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R6C6[1][B]	u_uart_slave/u_uart_slave_rx/rx_reg_Z[0]/CLK
3.693	0.333	tC2Q	RR	2	R6C6[1][B]	u_uart_slave/u_uart_slave_rx/rx_reg_Z[0]/Q
3.930	0.238	tNET	RR	1	R6C6[1][A]	u_uart_slave/u_uart_slave_rx/rx_reg_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R6C6[1][A]	u_uart_slave/u_uart_slave_rx/rx_reg_Z[1]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/rx_reg_Z[1]
3.359	0.000	tHld		1	R6C6[1][A]	u_uart_slave/u_uart_slave_rx/rx_reg_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	4.067
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]
To	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R12C8[0][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/CLK
3.693	0.333	tC2Q	RR	2	R12C8[0][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/Q
3.695	0.002	tNET	RR	1	R12C8[0][A]	u_uart_slave/u_uart_slave_tx/cnt_n_3_cZ[3]/I2
4.067	0.372	tINS	RF	1	R12C8[0][A]	u_uart_slave/u_uart_slave_tx/cnt_n_3_cZ[3]/F
4.067	0.000	tNET	FF	1	R12C8[0][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R12C8[0][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]
3.359	0.000	tHld		1	R12C8[0][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path5

Path Summary:

Slack	0.709
Data Arrival Time	4.068
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]
To	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C9[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]/CLK
3.693	0.333	tC2Q	RR	3	R13C9[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]/Q
3.696	0.004	tNET	RR	1	R13C9[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_4_fast_cZ[1]/I1
4.068	0.372	tINS	RF	1	R13C9[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_4_fast_cZ[1]/F
4.068	0.000	tNET	FF	1	R13C9[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C9[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]
3.359	0.000	tHld		1	R13C9[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path6

Path Summary:

Slack	0.709
Data Arrival Time	4.068
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]
To	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]/CLK
3.693	0.333	tC2Q	RR	4	R13C8[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]/Q
3.696	0.004	tNET	RR	1	R13C8[0][A]	u_uart_slave/u_uart_slave_tx/un1_bit_num_axbxc2_1_cZ/I0
4.068	0.372	tINS	RF	1	R13C8[0][A]	u_uart_slave/u_uart_slave_tx/un1_bit_num_axbxc2_1_cZ/F
4.068	0.000	tNET	FF	1	R13C8[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/bit_num_Z[2]
3.359	0.000	tHld		1	R13C8[0][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path7

Path Summary:

Slack	0.709
Data Arrival Time	4.068
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]
To	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R12C8[1][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]/CLK
3.693	0.333	tC2Q	RR	3	R12C8[1][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]/Q
3.696	0.004	tNET	RR	1	R12C8[1][A]	u_uart_slave/u_uart_slave_tx/cnt_n_3_cZ[1]/I2
4.068	0.372	tINS	RF	1	R12C8[1][A]	u_uart_slave/u_uart_slave_tx/cnt_n_3_cZ[1]/F
4.068	0.000	tNET	FF	1	R12C8[1][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R12C8[1][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]
3.359	0.000	tHld		1	R12C8[1][A]	u_uart_slave/u_uart_slave_tx/cnt_n_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path8

Path Summary:

Slack	0.709
Data Arrival Time	4.068
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]
To	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/CLK
3.693	0.333	tC2Q	RR	4	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/Q
3.696	0.004	tNET	RR	1	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[2]/I1
4.068	0.372	tINS	RF	1	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[2]/F
4.068	0.000	tNET	FF	1	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]
3.359	0.000	tHld		1	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path9

Path Summary:

Slack	0.709
Data Arrival Time	4.068
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]
To	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/CLK
3.693	0.333	tC2Q	RR	3	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/Q
3.696	0.004	tNET	RR	1	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[0]/I1
4.068	0.372	tINS	RF	1	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[0]/F
4.068	0.000	tNET	FF	1	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]
3.359	0.000	tHld		1	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path10

Path Summary:

Slack	0.710
Data Arrival Time	4.069
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]
To	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[1][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]/CLK
3.693	0.333	tC2Q	RR	7	R13C8[1][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]/Q
3.697	0.005	tNET	RR	1	R13C8[1][A]	u_uart_slave/u_uart_slave_tx/un1_bit_num_axb0_cZ/I0
4.069	0.372	tINS	RF	1	R13C8[1][A]	u_uart_slave/u_uart_slave_tx/un1_bit_num_axb0_cZ/F
4.069	0.000	tNET	FF	1	R13C8[1][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[1][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/bit_num_Z[0]
3.359	0.000	tHld		1	R13C8[1][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path11

Path Summary:

Slack	0.833
Data Arrival Time	4.193
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/data_rx[1]
To	u_uart_slave/u_uart_slave_tx/shift_data_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C6[2][B]	u_uart_slave/u_uart_slave_rx/data_rx[1]/CLK
3.693	0.333	tC2Q	RR	1	R9C6[2][B]	u_uart_slave/u_uart_slave_rx/data_rx[1]/Q
4.193	0.500	tNET	RR	1	R11C6[0][A]	u_uart_slave/u_uart_slave_tx/shift_data_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R11C6[0][A]	u_uart_slave/u_uart_slave_tx/shift_data_Z[3]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/shift_data_Z[3]
3.359	0.000	tHld		1	R11C6[0][A]	u_uart_slave/u_uart_slave_tx/shift_data_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path12

Path Summary:

Slack	0.833
Data Arrival Time	4.193
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/data_rx[5]
To	u_uart_slave/u_uart_slave_tx/shift_data_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C6[1][B]	u_uart_slave/u_uart_slave_rx/data_rx[5]/CLK
3.693	0.333	tC2Q	RR	1	R9C6[1][B]	u_uart_slave/u_uart_slave_rx/data_rx[5]/Q
4.193	0.500	tNET	RR	1	R11C6[0][B]	u_uart_slave/u_uart_slave_tx/shift_data_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R11C6[0][B]	u_uart_slave/u_uart_slave_tx/shift_data_Z[7]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/shift_data_Z[7]
3.359	0.000	tHld		1	R11C6[0][B]	u_uart_slave/u_uart_slave_tx/shift_data_Z[7]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.500, 60.007%; tC2Q: 0.333, 39.993%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path13

Path Summary:

Slack	0.870
Data Arrival Time	4.245
Data Required Time	3.374
From	u_uart_slave/u_uart_slave_rx/shift_flag_0
To	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/CLK
3.693	0.333	tC2Q	RR	10	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q
4.245	0.552	tNET	RR	1	R9C7[0][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C7[0][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]
3.374	0.015	tHld		1	R9C7[0][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[6]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.552, 62.351%; tC2Q: 0.333, 37.649%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path14

Path Summary:

Slack	0.870
Data Arrival Time	4.245
Data Required Time	3.374
From	u_uart_slave/u_uart_slave_rx/shift_flag_0
To	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/CLK
3.693	0.333	tC2Q	RR	10	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q
4.245	0.552	tNET	RR	1	R9C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[7]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[7]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[7]
3.374	0.015	tHld		1	R9C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[7]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.552, 62.351%; tC2Q: 0.333, 37.649%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path15

Path Summary:

Slack	0.870
Data Arrival Time	4.245
Data Required Time	3.374
From	u_uart_slave/u_uart_slave_rx/shift_flag_0
To	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[8]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/CLK
3.693	0.333	tC2Q	RR	10	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q
4.245	0.552	tNET	RR	1	R9C7[1][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[8]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C7[1][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[8]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[8]
3.374	0.015	tHld		1	R9C7[1][A]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[8]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.552, 62.351%; tC2Q: 0.333, 37.649%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path16

Path Summary:

Slack	0.870
Data Arrival Time	4.245
Data Required Time	3.374
From	u_uart_slave/u_uart_slave_rx/shift_flag_0
To	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[9]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/CLK
3.693	0.333	tC2Q	RR	10	R8C7[0][B]	u_uart_slave/u_uart_slave_rx/shift_flag_0/Q
4.245	0.552	tNET	RR	1	R9C7[1][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[9]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C7[1][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[9]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[9]
3.374	0.015	tHld		1	R9C7[1][B]	u_uart_slave/u_uart_slave_rx/shift_data_rx_Z[9]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.552, 62.351%; tC2Q: 0.333, 37.649%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path17

Path Summary:

Slack	0.893
Data Arrival Time	4.252
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]
To	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R7C9[2][A]	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/CLK
3.693	0.333	tC2Q	RR	3	R7C9[2][A]	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/Q
3.696	0.004	tNET	RR	1	R7C9[2][A]	u_uart_slave/u_uart_slave_rx/cnt_n_3_fast_cZ[0]/I1
4.252	0.556	tINS	RR	1	R7C9[2][A]	u_uart_slave/u_uart_slave_rx/cnt_n_3_fast_cZ[0]/F
4.252	0.000	tNET	RR	1	R7C9[2][A]	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R7C9[2][A]	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]
3.359	0.000	tHld		1	R7C9[2][A]	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path18

Path Summary:

Slack	0.894
Data Arrival Time	4.253
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]
To	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R12C9[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]/CLK
3.693	0.333	tC2Q	RR	7	R12C9[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]/Q
3.697	0.005	tNET	RR	1	R12C9[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_0[3]/I0
4.253	0.556	tINS	RR	1	R12C9[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_0[3]/F
4.253	0.000	tNET	RR	1	R12C9[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R12C9[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/bit_num_Z[3]
3.359	0.000	tHld		1	R12C9[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path19

Path Summary:

Slack	0.895
Data Arrival Time	4.255
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]
To	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/CLK
3.693	0.333	tC2Q	RR	7	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/Q
3.699	0.006	tNET	RR	1	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_4_cZ[1]/I1
4.255	0.556	tINS	RR	1	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_4_cZ[1]/F
4.255	0.000	tNET	RR	1	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/bit_num_Z[1]
3.359	0.000	tHld		1	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path20

Path Summary:

Slack	0.904
Data Arrival Time	4.263
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/data_rx[4]
To	u_uart_slave/u_uart_slave_tx/shift_data_Z[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R9C9[0][B]	u_uart_slave/u_uart_slave_rx/data_rx[4]/CLK
3.693	0.333	tC2Q	RR	1	R9C9[0][B]	u_uart_slave/u_uart_slave_rx/data_rx[4]/Q
4.263	0.570	tNET	RR	1	R11C10[0][A]	u_uart_slave/u_uart_slave_tx/shift_data_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R11C10[0][A]	u_uart_slave/u_uart_slave_tx/shift_data_Z[6]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/shift_data_Z[6]
3.359	0.000	tHld		1	R11C10[0][A]	u_uart_slave/u_uart_slave_tx/shift_data_Z[6]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.570, 63.116%; tC2Q: 0.333, 36.884%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path21

Path Summary:

Slack	0.943
Data Arrival Time	4.302
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]
To	u_uart_slave/u_uart_slave_rx/cnt_n_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/CLK
3.693	0.333	tC2Q	RF	4	R8C7[1][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[2]/Q
3.930	0.238	tNET	FF	1	R8C8[0][B]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[3]/I1
4.302	0.372	tINS	FF	1	R8C8[0][B]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[3]/F
4.302	0.000	tNET	FF	1	R8C8[0][B]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C8[0][B]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[3]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/cnt_n_Z[3]
3.359	0.000	tHld		1	R8C8[0][B]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path22

Path Summary:

Slack	0.943
Data Arrival Time	4.302
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]
To	u_uart_slave/u_uart_slave_rx/cnt_n_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/CLK
3.693	0.333	tC2Q	RF	3	R8C9[0][A]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/Q
3.930	0.238	tNET	FF	1	R8C8[1][B]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[1]/I1
4.302	0.372	tINS	FF	1	R8C8[1][B]	u_uart_slave/u_uart_slave_rx/cnt_n_3_cZ[1]/F
4.302	0.000	tNET	FF	1	R8C8[1][B]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R8C8[1][B]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[1]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/cnt_n_Z[1]
3.359	0.000	tHld		1	R8C8[1][B]	u_uart_slave/u_uart_slave_rx/cnt_n_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path23

Path Summary:

Slack	0.953
Data Arrival Time	4.312
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]
To	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/CLK
3.693	0.333	tC2Q	RR	7	R13C8[2][A]	u_uart_slave/u_uart_slave_tx/bit_num_Z[1]/Q
3.940	0.247	tNET	RR	1	R13C8[0][B]	u_uart_slave/u_uart_slave_tx/un1_bit_num_axb0_fast_cZ/I0
4.312	0.372	tINS	RF	1	R13C8[0][B]	u_uart_slave/u_uart_slave_tx/un1_bit_num_axb0_fast_cZ/F
4.312	0.000	tNET	FF	1	R13C8[0][B]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C8[0][B]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[0]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[0]
3.359	0.000	tHld		1	R13C8[0][B]	u_uart_slave/u_uart_slave_tx/bit_num_fast_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 39.049%; route: 0.247, 25.962%; tC2Q: 0.333, 34.990%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path24

Path Summary:

Slack	0.967
Data Arrival Time	4.326
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_tx/div_end_0
To	u_uart_slave/u_uart_slave_tx/div_cnt_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R12C6[1][A]	u_uart_slave/u_uart_slave_tx/div_end_0/CLK
3.693	0.333	tC2Q	RF	28	R12C6[1][A]	u_uart_slave/u_uart_slave_tx/div_end_0/Q
3.954	0.261	tNET	FF	1	R13C6[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[7]/I2
4.326	0.372	tINS	FF	1	R13C6[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_3_cZ[7]/F
4.326	0.000	tNET	FF	1	R13C6[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R13C6[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[7]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_tx/div_cnt_Z[7]
3.359	0.000	tHld		1	R13C6[1][A]	u_uart_slave/u_uart_slave_tx/div_cnt_Z[7]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 38.478%; route: 0.261, 27.043%; tC2Q: 0.333, 34.479%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Path25

Path Summary:

Slack	0.979
Data Arrival Time	4.338
Data Required Time	3.359
From	u_uart_slave/u_uart_slave_rx/cnt_en_0
To	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R6C6[0][A]	u_uart_slave/u_uart_slave_rx/cnt_en_0/CLK
3.693	0.333	tC2Q	RR	29	R6C6[0][A]	u_uart_slave/u_uart_slave_rx/cnt_en_0/Q
3.966	0.273	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[0]/I1
4.338	0.372	tINS	RF	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_3_cZ[0]/F
4.338	0.000	tNET	FF	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOL3[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	103	IOL3[B]	SCLK_ibuf/O
3.359	2.515	tNET	RR	1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]/CLK
3.359	0.000	tUnc				u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]
3.359	0.000	tHld		1	R6C8[0][A]	u_uart_slave/u_uart_slave_rx/div_cnt_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%
Arrival Data Path Delay	cell: 0.372, 38.008%; route: 0.273, 27.934%; tC2Q: 0.333, 34.058%
Required Clock Path Delay	cell: 0.844, 25.135%; route: 2.515, 74.865%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_rx/cnt_n_fast_Z[0]/CLK

MPW2

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_rx/div_end_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_rx/div_end_0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_rx/div_end_0/CLK

MPW3

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_rx/cnt_n_Z[0]/CLK

MPW4

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_rx/div_cnt_Z[21]/CLK

MPW5

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_rx/div_cnt_Z[7]/CLK

MPW6

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_tx/div_cnt_Z[16]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_tx/div_cnt_Z[16]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_tx/div_cnt_Z[16]/CLK

MPW7

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_tx/div_end_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_tx/div_end_0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_tx/div_end_0/CLK

MPW8

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_rx/div_cnt_Z[6]/CLK

MPW9

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_tx/shift_flag_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_tx/shift_flag_0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_tx/shift_flag_0/CLK

MPW10

MPW Summary:

Slack:	2.329
Actual Width:	3.579
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.780	3.796	tNET	FF	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.359	2.515	tNET	RR	u_uart_slave/u_uart_slave_tx/cnt_n_Z[3]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
103	SCLK_c	0.727	3.796
30	div_end	4.941	1.362
29	cnt_en	5.138	1.345
28	div_end	5.598	1.369
27	busy_n	4.705	1.315
13	fram_end	5.486	1.789
10	shift_flag	7.382	2.494
9	rx_fram_end8	4.927	1.859
8	shift_flag	6.053	2.812
7	bit_num[1]	3.124	0.990

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R13C6	0.361
R7C6	0.347
R7C7	0.347
R14C6	0.347
R12C8	0.306
R7C8	0.306
R13C8	0.278
R13C7	0.278
R8C6	0.278
R14C7	0.278

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command