#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: Desktop-2019KKU # Tue Sep 17 16:42:51 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\src\gw_spi_slave.v" (library work) @I::"D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\src\spi_slave.v" (library work) Verilog syntax check successful! Selecting top level module gw_spi_slave @N:CG364 : spi_slave.v(8) | Synthesizing module spi_slave in library work. @W:CG1340 : spi_slave.v(106) | Index into variable miso_shift_reg could be out of range ; a simulation mismatch is possible. Running optimization stage 1 on spi_slave ....... @N:CG364 : gw_spi_slave.v(3) | Synthesizing module gw_spi_slave in library work. Running optimization stage 1 on gw_spi_slave ....... Running optimization stage 2 on gw_spi_slave ....... Running optimization stage 2 on spi_slave ....... @N:CL189 : spi_slave.v(94) | Register bit genblk2.tx_cnt[3] is always 0. @N:CL189 : spi_slave.v(94) | Register bit genblk2.tx_cnt[4] is always 0. @N:CL189 : spi_slave.v(94) | Register bit genblk2.tx_cnt[5] is always 0. @W:CL279 : spi_slave.v(94) | Pruning register bits 5 to 3 of genblk2.tx_cnt[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\impl\synthesize\rev_1\synwork\layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 16:42:51 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 16:42:51 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 16:42:51 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 16:42:53 2019 ###########################################################] Premap Report # Tue Sep 17 16:42:53 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design @L: D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\impl\synthesize\rev_1\gw_spi_slave_scck.rpt Printing clock summary report in "D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\impl\synthesize\rev_1\gw_spi_slave_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design @W:FX474 : | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------------- 0 - gw_spi_slave|SCLK 303.9 MHz 3.290 inferred Autoconstr_clkgroup_0 25 ======================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------------------------------------------ gw_spi_slave|SCLK 25 SCLK(port) u_spi_slave.genblk1\.rx_cnt[0].C - u_spi_slave.un1_SCLK.I[0](inv) ==================================================================================================================================== @W:MT529 : spi_slave.v(94) | Found inferred clock gw_spi_slave|SCLK which controls 25 sequential elements including u_spi_slave.genblk2\.miso_shift_reg[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 25 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ======================================= Non-Gated/Non-Generated Clocks ======================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------------------- ClockId_0_0 SCLK Unconstrained_port 25 u_spi_slave.genblk1\.mosi_shift_reg[7] ============================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\impl\synthesize\rev_1\gw_spi_slave.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 192MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 192MB) None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 192MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 192MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Sep 17 16:42:55 2019 ###########################################################] Map & Optimize Report # Tue Sep 17 16:42:55 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled @N:FX493 : | Applying initial value "00000000" on instance u_spi_slave.genblk2\.miso_shift_reg[7:0]. @N:FX493 : | Applying initial value "000" on instance u_spi_slave.genblk2\.tx_cnt[2:0]. @N:FX493 : | Applying initial value "00000000" on instance u_spi_slave.genblk1\.mosi_shift_reg[7:0]. @N:FX493 : | Applying initial value "000000" on instance u_spi_slave.genblk1\.rx_cnt[5:0]. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -1.43ns 29 / 25 2 0h:00m:00s -1.43ns 29 / 25 3 0h:00m:00s -1.43ns 29 / 25 4 0h:00m:00s -1.43ns 29 / 25 5 0h:00m:00s -1.43ns 29 / 25 6 0h:00m:00s -1.43ns 29 / 25 @N:FX271 : spi_slave.v(45) | Replicating instance u_spi_slave.genblk1\.rx_cnt[0] (in view: work.gw_spi_slave(verilog)) with 5 loads 1 time to improve timing. @N:FX271 : spi_slave.v(45) | Replicating instance u_spi_slave.genblk1\.rx_cnt[1] (in view: work.gw_spi_slave(verilog)) with 4 loads 1 time to improve timing. Timing driven replication report Added 2 Registers via timing driven replication Added 2 LUTs via timing driven replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 191MB) Writing Analyst data base D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\impl\synthesize\rev_1\synwork\gw_spi_slave_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 191MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 191MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 189MB peak: 191MB) @W:MT420 : | Found inferred clock gw_spi_slave|SCLK with period 3.81ns. Please declare a user-defined clock on port SCLK. ##### START OF TIMING REPORT #####[ # Timing report written on Tue Sep 17 16:42:58 2019 # Top view: gw_spi_slave Requested Frequency: 262.3 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.673 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------- gw_spi_slave|SCLK 262.3 MHz 223.0 MHz 3.812 4.485 -0.673 inferred Autoconstr_clkgroup_0 System 100.0 MHz 136.2 MHz 10.000 7.342 2.658 system system_clkgroup =========================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------- System gw_spi_slave|SCLK | 3.812 2.658 | No paths - | 3.812 2.658 | No paths - gw_spi_slave|SCLK System | 3.812 2.424 | No paths - | No paths - | 3.812 2.424 gw_spi_slave|SCLK gw_spi_slave|SCLK | 3.812 -0.673 | 3.812 0.171 | 1.906 0.385 | No paths - ============================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: gw_spi_slave|SCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt[5] gw_spi_slave|SCLK DFFRE Q un4_rx_cnt_axb5 0.367 -0.673 u_spi_slave.genblk1\.rx_cnt[4] gw_spi_slave|SCLK DFFRE Q un4_rx_cnt_axb4 0.367 -0.667 u_spi_slave.genblk1\.rx_cnt[1] gw_spi_slave|SCLK DFFRE Q un4_rx_cnt_axb1 0.367 -0.606 u_spi_slave.genblk1\.rx_cnt_fast[0] gw_spi_slave|SCLK DFFR Q rx_cnt_fast[0] 0.367 -0.538 u_spi_slave.genblk1\.rx_cnt[2] gw_spi_slave|SCLK DFFRE Q un4_rx_cnt_axb2 0.367 -0.329 u_spi_slave.genblk2\.tx_cnt[0] gw_spi_slave|SCLK DFFNR Q CO0 0.367 0.171 u_spi_slave.genblk1\.mosi_shift_reg[0] gw_spi_slave|SCLK DFFR Q mosi_shift_reg[0] 0.367 0.385 u_spi_slave.genblk1\.mosi_shift_reg[1] gw_spi_slave|SCLK DFFR Q mosi_shift_reg[1] 0.367 0.385 u_spi_slave.genblk1\.mosi_shift_reg[2] gw_spi_slave|SCLK DFFR Q mosi_shift_reg[2] 0.367 0.385 u_spi_slave.genblk1\.mosi_shift_reg[3] gw_spi_slave|SCLK DFFR Q mosi_shift_reg[3] 0.367 0.385 =========================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt[3] gw_spi_slave|SCLK DFFR D N_27_0 3.679 -0.673 u_spi_slave.genblk2\.miso_shift_reg[0] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.miso_shift_reg[1] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.miso_shift_reg[2] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.miso_shift_reg[3] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.miso_shift_reg[4] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.miso_shift_reg[5] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.miso_shift_reg[6] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.miso_shift_reg[7] gw_spi_slave|SCLK DFFNE CE tx_cnt11 3.679 0.171 u_spi_slave.genblk2\.tx_cnt[0] gw_spi_slave|SCLK DFFNR RESET un1_SS 3.679 0.171 ===================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3.812 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.679 - Propagation time: 4.352 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.673 Number of logic level(s): 2 Starting point: u_spi_slave.genblk1\.rx_cnt[5] / Q Ending point: u_spi_slave.genblk1\.rx_cnt[3] / D The start point is clocked by gw_spi_slave|SCLK [rising] on pin CLK The end point is clocked by gw_spi_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt[5] DFFRE Q Out 0.367 0.367 - un4_rx_cnt_axb5 Net - - 1.021 - 10 u_spi_slave.g0_i_a4_0 LUT2 I1 In - 1.388 - u_spi_slave.g0_i_a4_0 LUT2 F Out 1.099 2.487 - g0_i_a4_0 Net - - 0.766 - 1 u_spi_slave.g0_3_0 LUT3 I1 In - 3.253 - u_spi_slave.g0_3_0 LUT3 F Out 1.099 4.352 - N_27_0 Net - - 0.000 - 1 u_spi_slave.genblk1\.rx_cnt[3] DFFR D In - 4.352 - ============================================================================================== Total path delay (propagation time + setup) of 4.485 is 2.698(60.2%) logic and 1.787(39.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 3.812 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.679 - Propagation time: 4.346 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.667 Number of logic level(s): 2 Starting point: u_spi_slave.genblk1\.rx_cnt[4] / Q Ending point: u_spi_slave.genblk1\.rx_cnt[3] / D The start point is clocked by gw_spi_slave|SCLK [rising] on pin CLK The end point is clocked by gw_spi_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt[4] DFFRE Q Out 0.367 0.367 - un4_rx_cnt_axb4 Net - - 1.082 - 11 u_spi_slave.g0_i_a4_0 LUT2 I0 In - 1.449 - u_spi_slave.g0_i_a4_0 LUT2 F Out 1.032 2.481 - g0_i_a4_0 Net - - 0.766 - 1 u_spi_slave.g0_3_0 LUT3 I1 In - 3.247 - u_spi_slave.g0_3_0 LUT3 F Out 1.099 4.346 - N_27_0 Net - - 0.000 - 1 u_spi_slave.genblk1\.rx_cnt[3] DFFR D In - 4.346 - ============================================================================================== Total path delay (propagation time + setup) of 4.479 is 2.631(58.7%) logic and 1.848(41.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 3.812 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.679 - Propagation time: 4.285 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.606 Number of logic level(s): 2 Starting point: u_spi_slave.genblk1\.rx_cnt[1] / Q Ending point: u_spi_slave.genblk1\.rx_cnt[3] / D The start point is clocked by gw_spi_slave|SCLK [rising] on pin CLK The end point is clocked by gw_spi_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt[1] DFFRE Q Out 0.367 0.367 - un4_rx_cnt_axb1 Net - - 1.021 - 3 u_spi_slave.g0_i_o2 LUT3 I1 In - 1.388 - u_spi_slave.g0_i_o2 LUT3 F Out 1.099 2.487 - N_6_0 Net - - 0.766 - 1 u_spi_slave.g0_3_0 LUT3 I0 In - 3.253 - u_spi_slave.g0_3_0 LUT3 F Out 1.032 4.285 - N_27_0 Net - - 0.000 - 1 u_spi_slave.genblk1\.rx_cnt[3] DFFR D In - 4.285 - ============================================================================================== Total path delay (propagation time + setup) of 4.418 is 2.631(59.6%) logic and 1.787(40.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 3.812 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.679 - Propagation time: 4.218 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.539 Number of logic level(s): 2 Starting point: u_spi_slave.genblk1\.rx_cnt_fast[0] / Q Ending point: u_spi_slave.genblk1\.rx_cnt[3] / D The start point is clocked by gw_spi_slave|SCLK [rising] on pin CLK The end point is clocked by gw_spi_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt_fast[0] DFFR Q Out 0.367 0.367 - rx_cnt_fast[0] Net - - 1.021 - 4 u_spi_slave.g0_i_o2 LUT3 I0 In - 1.388 - u_spi_slave.g0_i_o2 LUT3 F Out 1.032 2.420 - N_6_0 Net - - 0.766 - 1 u_spi_slave.g0_3_0 LUT3 I0 In - 3.186 - u_spi_slave.g0_3_0 LUT3 F Out 1.032 4.218 - N_27_0 Net - - 0.000 - 1 u_spi_slave.genblk1\.rx_cnt[3] DFFR D In - 4.218 - ================================================================================================== Total path delay (propagation time + setup) of 4.351 is 2.564(58.9%) logic and 1.787(41.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 3.812 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.679 - Propagation time: 4.008 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.329 Number of logic level(s): 2 Starting point: u_spi_slave.genblk1\.rx_cnt[2] / Q Ending point: u_spi_slave.genblk1\.rx_cnt[3] / D The start point is clocked by gw_spi_slave|SCLK [rising] on pin CLK The end point is clocked by gw_spi_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt[2] DFFRE Q Out 0.367 0.367 - un4_rx_cnt_axb2 Net - - 1.021 - 4 u_spi_slave.g0_i_o2 LUT3 I2 In - 1.388 - u_spi_slave.g0_i_o2 LUT3 F Out 0.822 2.210 - N_6_0 Net - - 0.766 - 1 u_spi_slave.g0_3_0 LUT3 I0 In - 2.976 - u_spi_slave.g0_3_0 LUT3 F Out 1.032 4.008 - N_27_0 Net - - 0.000 - 1 u_spi_slave.genblk1\.rx_cnt[3] DFFR D In - 4.008 - ============================================================================================== Total path delay (propagation time + setup) of 4.141 is 2.354(56.8%) logic and 1.787(43.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------ u_spi_slave.genblk1\.rx_cnt_0_0[0] System INV O N_33_0 0.000 2.658 u_spi_slave.genblk1\.rx_cnt_0_0[1] System INV O N_31_0 0.000 2.658 u_spi_slave.genblk1\.rx_cnt_0_fast_0[0] System INV O N_33_fast_0 0.000 2.658 u_spi_slave.genblk1\.rx_cnt_0_fast_0[1] System INV O N_31_fast_0 0.000 2.658 u_spi_slave.genblk2\.tx_cnt_0_0[0] System INV O N_5_0 0.000 2.658 u_spi_slave.genblk2\.tx_cnt_0_0[1] System INV O N_3_0 0.000 2.658 ============================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt[0] System DFFR D N_33_0 3.679 2.658 u_spi_slave.genblk1\.rx_cnt[1] System DFFRE D N_31_0 3.679 2.658 u_spi_slave.genblk1\.rx_cnt_fast[0] System DFFR D N_33_fast_0 3.679 2.658 u_spi_slave.genblk1\.rx_cnt_fast[1] System DFFRE D N_31_fast_0 3.679 2.658 u_spi_slave.genblk2\.tx_cnt[0] System DFFNR D N_5_0 3.679 2.658 u_spi_slave.genblk2\.tx_cnt[1] System DFFNRE D N_3_0 3.679 2.658 =========================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3.812 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.679 - Propagation time: 1.021 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.658 Number of logic level(s): 0 Starting point: u_spi_slave.genblk1\.rx_cnt_0_0[0] / O Ending point: u_spi_slave.genblk1\.rx_cnt[0] / D The start point is clocked by System [rising] The end point is clocked by gw_spi_slave|SCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------- u_spi_slave.genblk1\.rx_cnt_0_0[0] INV O Out 0.000 0.000 - N_33_0 Net - - 1.021 - 1 u_spi_slave.genblk1\.rx_cnt[0] DFFR D In - 1.021 - ================================================================================================= Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 191MB) --------------------------------------- Resource Usage Report for gw_spi_slave Mapping to part: gw1n_4lqfp144-6 Cell usage: DFFNE 8 uses DFFNR 1 use DFFNRE 2 uses DFFR 11 uses DFFRE 5 uses GSR 1 use INV 6 uses MUX2_LUT5 2 uses MUX2_LUT6 1 use LUT2 4 uses LUT3 6 uses LUT4 12 uses I/O ports: 4 I/O primitives: 4 IBUF 3 uses TBUF 1 use I/O Register bits: 0 Register bits not including I/Os: 27 of 3456 (0%) Total load per clock: gw_spi_slave|SCLK: 27 @S |Mapping Summary: Total LUTs: 22 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 191MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Sep 17 16:42:58 2019 ###########################################################]