@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\src\spi_slave.v":8:7:8:15|Synthesizing module spi_slave in library work.
@N: CG364 :"D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\src\gw_spi_slave.v":3:7:3:18|Synthesizing module gw_spi_slave in library work.
@N: CL189 :"D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\src\spi_slave.v":94:4:94:9|Register bit genblk2.tx_cnt[3] is always 0.
@N: CL189 :"D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\src\spi_slave.v":94:4:94:9|Register bit genblk2.tx_cnt[4] is always 0.
@N: CL189 :"D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\gw_spi_slave\src\spi_slave.v":94:4:94:9|Register bit genblk2.tx_cnt[5] is always 0.
@N|Running in 64-bit mode

