Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\impl\synthesize\rev_1\gw_spi_slave.vm
Physical Constraints File	D:\IP release\spi_sram\Gowin_SPI_RefDesign_For_Release_190917\Gowin_SPI_Slave_RefDesign\project\src\gw_spi_slave.cst
Timing Constraint File	---
GOWIN version	V1.9.1.01Beta
Part Number	GW1N-LV4LQ144C6/I5
Created Time	Tue Sep 17 18:56:42 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	83
Numbers of Endpoints Analyzed	62
Numbers of Falling Endpoints	24
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	184.976(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.297	u_spi_slave/genblk1.mosi_shift_reg[1]/Q	u_spi_slave/genblk2.miso_shift_reg[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	2.297
2	2.297	u_spi_slave/genblk1.mosi_shift_reg[3]/Q	u_spi_slave/genblk2.miso_shift_reg[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	2.297
3	2.301	u_spi_slave/genblk1.mosi_shift_reg[7]/Q	u_spi_slave/genblk2.miso_shift_reg[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	2.293
4	2.690	u_spi_slave/genblk1.mosi_shift_reg[0]/Q	u_spi_slave/genblk2.miso_shift_reg[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	1.904
5	2.690	u_spi_slave/genblk1.mosi_shift_reg[2]/Q	u_spi_slave/genblk2.miso_shift_reg[2]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	1.904
6	2.759	u_spi_slave/genblk1.mosi_shift_reg[5]/Q	u_spi_slave/genblk2.miso_shift_reg[5]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	1.835
7	3.312	u_spi_slave/genblk1.mosi_shift_reg[6]/Q	u_spi_slave/genblk2.miso_shift_reg[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	1.282
8	3.714	u_spi_slave/genblk1.mosi_shift_reg[4]/Q	u_spi_slave/genblk2.miso_shift_reg[4]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[F]	5.000	-0.194	0.881
9	5.707	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[2]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	4.050
10	5.707	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[3]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	4.050
11	5.707	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[4]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	4.050
12	5.707	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[5]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	4.050
13	6.067	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[6]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	3.690
14	6.067	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[7]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	3.690
15	6.067	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[0]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	3.690
16	6.067	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.miso_shift_reg[1]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	10.000	0.000	3.690
17	6.191	u_spi_slave/genblk1.rx_cnt[3]/Q	u_spi_slave/genblk1.mosi_shift_reg[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	3.209
18	6.191	u_spi_slave/genblk1.rx_cnt[3]/Q	u_spi_slave/genblk1.mosi_shift_reg[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	3.209
19	6.259	u_spi_slave/genblk1.rx_cnt_fast[0]/Q	u_spi_slave/genblk1.rx_cnt[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	3.141
20	6.433	u_spi_slave/genblk1.rx_cnt[3]/Q	u_spi_slave/genblk1.mosi_shift_reg[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.967
21	6.515	u_spi_slave/genblk1.rx_cnt[4]/Q	u_spi_slave/genblk1.mosi_shift_reg[5]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.885
22	6.536	u_spi_slave/genblk1.rx_cnt[3]/Q	u_spi_slave/genblk1.mosi_shift_reg[4]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.864
23	6.607	u_spi_slave/genblk1.rx_cnt[4]/Q	u_spi_slave/genblk1.mosi_shift_reg[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.793
24	6.607	u_spi_slave/genblk1.rx_cnt[4]/Q	u_spi_slave/genblk1.mosi_shift_reg[2]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.793
25	6.834	u_spi_slave/genblk1.rx_cnt[3]/Q	u_spi_slave/genblk1.mosi_shift_reg[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.566

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.708	u_spi_slave/genblk1.rx_cnt[0]/Q	u_spi_slave/genblk1.rx_cnt[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.708
2	0.709	u_spi_slave/genblk1.rx_cnt_fast[1]/Q	u_spi_slave/genblk1.rx_cnt_fast[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
3	0.709	u_spi_slave/genblk1.rx_cnt[5]/Q	u_spi_slave/genblk1.rx_cnt[5]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
4	0.709	u_spi_slave/genblk1.rx_cnt_fast[0]/Q	u_spi_slave/genblk1.rx_cnt_fast[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.709
5	0.710	u_spi_slave/genblk1.rx_cnt[4]/Q	u_spi_slave/genblk1.rx_cnt[4]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.710
6	0.710	u_spi_slave/genblk2.tx_cnt[2]/Q	u_spi_slave/genblk2.tx_cnt[2]/D	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	0.000	0.000	0.710
7	0.839	u_spi_slave/genblk2.tx_cnt[0]/Q	u_spi_slave/genblk2.tx_cnt[1]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	0.000	0.000	0.854
8	0.839	u_spi_slave/genblk2.tx_cnt[0]/Q	u_spi_slave/genblk2.tx_cnt[2]/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	0.000	0.000	0.854
9	0.843	u_spi_slave/genblk1.rx_cnt[3]/Q	u_spi_slave/genblk1.rx_cnt[4]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.858
10	0.893	u_spi_slave/genblk1.rx_cnt[1]/Q	u_spi_slave/genblk1.rx_cnt[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.893
11	0.894	u_spi_slave/genblk2.tx_cnt[0]/Q	u_spi_slave/genblk2.tx_cnt[0]/D	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	0.000	0.000	0.894
12	0.943	u_spi_slave/genblk1.mosi_shift_reg[6]/Q	u_spi_slave/genblk1.mosi_shift_reg[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.943
13	0.943	u_spi_slave/genblk1.rx_cnt[1]/Q	u_spi_slave/genblk1.rx_cnt[2]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.943
14	1.061	u_spi_slave/genblk2.tx_cnt[1]/Q	u_spi_slave/genblk2.tx_cnt[1]/D	DEFAULT_CLK:[F]	DEFAULT_CLK:[F]	0.000	0.000	1.061
15	1.066	u_spi_slave/genblk1.rx_cnt[3]/Q	u_spi_slave/genblk1.rx_cnt[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.066
16	1.101	u_spi_slave/genblk1.rx_cnt[0]/Q	u_spi_slave/genblk1.rx_cnt_fast[1]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.116
17	1.101	u_spi_slave/genblk1.rx_cnt[0]/Q	u_spi_slave/genblk1.rx_cnt[1]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.116
18	1.101	u_spi_slave/genblk1.rx_cnt[0]/Q	u_spi_slave/genblk1.rx_cnt[2]/CE	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.116
19	1.277	u_spi_slave/genblk1.mosi_shift_reg[3]/Q	u_spi_slave/genblk1.mosi_shift_reg[4]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.277
20	1.292	u_spi_slave/genblk1.mosi_shift_reg[2]/Q	u_spi_slave/genblk1.mosi_shift_reg[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.292
21	1.294	u_spi_slave/genblk1.mosi_shift_reg[0]/Q	u_spi_slave/genblk1.mosi_shift_reg[1]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.294
22	1.300	u_spi_slave/genblk1.mosi_shift_reg[5]/Q	u_spi_slave/genblk1.mosi_shift_reg[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.300
23	1.391	u_spi_slave/genblk1.rx_cnt[5]/Q	u_spi_slave/genblk1.mosi_shift_reg[3]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.406
24	1.391	u_spi_slave/genblk1.rx_cnt[5]/Q	u_spi_slave/genblk1.mosi_shift_reg[2]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.406
25	1.391	u_spi_slave/genblk1.rx_cnt[5]/Q	u_spi_slave/genblk1.mosi_shift_reg[7]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.406

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk2.miso_shift_reg[7]
2	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk2.miso_shift_reg[5]
3	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk2.miso_shift_reg[1]
4	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk1.mosi_shift_reg[2]
5	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk1.mosi_shift_reg[1]
6	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk2.miso_shift_reg[2]
7	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk1.mosi_shift_reg[0]
8	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk1.rx_cnt_fast[1]
9	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk2.tx_cnt[1]
10	2.562	3.812	1.250	Low Pulse Width	DEFAULT_CLK	u_spi_slave/genblk1.mosi_shift_reg[7]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.297
Data Arrival Time	6.702
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[1]
To	u_spi_slave/genblk2.miso_shift_reg[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]/CLK
4.863	0.458	tC2Q	RF	2	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]/Q
6.702	1.839	tNET	FF	1	R11C13[2][B]	u_spi_slave/genblk2.miso_shift_reg[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C13[2][B]	u_spi_slave/genblk2.miso_shift_reg[1]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[1]
8.999	-0.400	tSu		1	R11C13[2][B]	u_spi_slave/genblk2.miso_shift_reg[1]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.839, 80.050%; tC2Q: 0.458, 19.950%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path2

Path Summary:

Slack	2.297
Data Arrival Time	6.702
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[3]
To	u_spi_slave/genblk2.miso_shift_reg[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/CLK
4.863	0.458	tC2Q	RF	2	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/Q
6.702	1.839	tNET	FF	1	R11C15[2][B]	u_spi_slave/genblk2.miso_shift_reg[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C15[2][B]	u_spi_slave/genblk2.miso_shift_reg[3]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[3]
8.999	-0.400	tSu		1	R11C15[2][B]	u_spi_slave/genblk2.miso_shift_reg[3]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.839, 80.050%; tC2Q: 0.458, 19.950%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path3

Path Summary:

Slack	2.301
Data Arrival Time	6.698
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[7]
To	u_spi_slave/genblk2.miso_shift_reg[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/CLK
4.863	0.458	tC2Q	RF	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/Q
6.698	1.835	tNET	FF	1	R11C13[0][B]	u_spi_slave/genblk2.miso_shift_reg[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C13[0][B]	u_spi_slave/genblk2.miso_shift_reg[7]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[7]
8.999	-0.400	tSu		1	R11C13[0][B]	u_spi_slave/genblk2.miso_shift_reg[7]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.835, 80.014%; tC2Q: 0.458, 19.986%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path4

Path Summary:

Slack	2.690
Data Arrival Time	6.309
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[0]
To	u_spi_slave/genblk2.miso_shift_reg[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg[0]/CLK
4.863	0.458	tC2Q	RR	2	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg[0]/Q
6.309	1.446	tNET	RR	1	R11C13[2][A]	u_spi_slave/genblk2.miso_shift_reg[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C13[2][A]	u_spi_slave/genblk2.miso_shift_reg[0]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[0]
8.999	-0.400	tSu		1	R11C13[2][A]	u_spi_slave/genblk2.miso_shift_reg[0]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.446, 75.933%; tC2Q: 0.458, 24.067%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path5

Path Summary:

Slack	2.690
Data Arrival Time	6.309
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[2]
To	u_spi_slave/genblk2.miso_shift_reg[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/CLK
4.863	0.458	tC2Q	RR	2	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/Q
6.309	1.446	tNET	RR	1	R11C15[2][A]	u_spi_slave/genblk2.miso_shift_reg[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C15[2][A]	u_spi_slave/genblk2.miso_shift_reg[2]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[2]
8.999	-0.400	tSu		1	R11C15[2][A]	u_spi_slave/genblk2.miso_shift_reg[2]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.446, 75.933%; tC2Q: 0.458, 24.067%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path6

Path Summary:

Slack	2.759
Data Arrival Time	6.240
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[5]
To	u_spi_slave/genblk2.miso_shift_reg[5]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg[5]/CLK
4.863	0.458	tC2Q	RF	2	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg[5]/Q
6.240	1.377	tNET	FF	1	R11C14[0][B]	u_spi_slave/genblk2.miso_shift_reg[5]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C14[0][B]	u_spi_slave/genblk2.miso_shift_reg[5]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[5]
8.999	-0.400	tSu		1	R11C14[0][B]	u_spi_slave/genblk2.miso_shift_reg[5]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.377, 75.023%; tC2Q: 0.458, 24.977%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path7

Path Summary:

Slack	3.312
Data Arrival Time	5.686
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[6]
To	u_spi_slave/genblk2.miso_shift_reg[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/CLK
4.863	0.458	tC2Q	RF	2	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/Q
5.686	0.824	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.miso_shift_reg[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.miso_shift_reg[6]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[6]
8.999	-0.400	tSu		1	R11C13[0][A]	u_spi_slave/genblk2.miso_shift_reg[6]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.824, 64.246%; tC2Q: 0.458, 35.754%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path8

Path Summary:

Slack	3.714
Data Arrival Time	5.285
Data Required Time	8.999
From	u_spi_slave/genblk1.mosi_shift_reg[4]
To	u_spi_slave/genblk2.miso_shift_reg[4]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]/CLK
4.863	0.458	tC2Q	RR	2	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]/Q
5.285	0.422	tNET	RR	1	R11C14[0][A]	u_spi_slave/genblk2.miso_shift_reg[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C14[0][A]	u_spi_slave/genblk2.miso_shift_reg[4]/CLK
9.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[4]
8.999	-0.400	tSu		1	R11C14[0][A]	u_spi_slave/genblk2.miso_shift_reg[4]

Path Statistics:

Clock Skew	0.194
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 47.965%; tC2Q: 0.458, 52.035%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path9

Path Summary:

Slack	5.707
Data Arrival Time	13.649
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.649	1.085	tNET	RR	1	R11C15[2][A]	u_spi_slave/genblk2.miso_shift_reg[2]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C15[2][A]	u_spi_slave/genblk2.miso_shift_reg[2]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[2]
19.356	-0.043	tSu		1	R11C15[2][A]	u_spi_slave/genblk2.miso_shift_reg[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 25.333%; route: 2.566, 63.350%; tC2Q: 0.458, 11.317%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path10

Path Summary:

Slack	5.707
Data Arrival Time	13.649
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.649	1.085	tNET	RR	1	R11C15[2][B]	u_spi_slave/genblk2.miso_shift_reg[3]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C15[2][B]	u_spi_slave/genblk2.miso_shift_reg[3]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[3]
19.356	-0.043	tSu		1	R11C15[2][B]	u_spi_slave/genblk2.miso_shift_reg[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 25.333%; route: 2.566, 63.350%; tC2Q: 0.458, 11.317%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path11

Path Summary:

Slack	5.707
Data Arrival Time	13.649
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.649	1.085	tNET	RR	1	R11C14[0][A]	u_spi_slave/genblk2.miso_shift_reg[4]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C14[0][A]	u_spi_slave/genblk2.miso_shift_reg[4]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[4]
19.356	-0.043	tSu		1	R11C14[0][A]	u_spi_slave/genblk2.miso_shift_reg[4]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 25.333%; route: 2.566, 63.350%; tC2Q: 0.458, 11.317%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path12

Path Summary:

Slack	5.707
Data Arrival Time	13.649
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.649	1.085	tNET	RR	1	R11C14[0][B]	u_spi_slave/genblk2.miso_shift_reg[5]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C14[0][B]	u_spi_slave/genblk2.miso_shift_reg[5]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[5]
19.356	-0.043	tSu		1	R11C14[0][B]	u_spi_slave/genblk2.miso_shift_reg[5]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 25.333%; route: 2.566, 63.350%; tC2Q: 0.458, 11.317%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path13

Path Summary:

Slack	6.067
Data Arrival Time	13.289
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.289	0.725	tNET	RR	1	R11C13[0][A]	u_spi_slave/genblk2.miso_shift_reg[6]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.miso_shift_reg[6]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[6]
19.356	-0.043	tSu		1	R11C13[0][A]	u_spi_slave/genblk2.miso_shift_reg[6]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 27.807%; route: 2.205, 59.772%; tC2Q: 0.458, 12.422%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path14

Path Summary:

Slack	6.067
Data Arrival Time	13.289
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.289	0.725	tNET	RR	1	R11C13[0][B]	u_spi_slave/genblk2.miso_shift_reg[7]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C13[0][B]	u_spi_slave/genblk2.miso_shift_reg[7]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[7]
19.356	-0.043	tSu		1	R11C13[0][B]	u_spi_slave/genblk2.miso_shift_reg[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 27.807%; route: 2.205, 59.772%; tC2Q: 0.458, 12.422%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path15

Path Summary:

Slack	6.067
Data Arrival Time	13.289
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.289	0.725	tNET	RR	1	R11C13[2][A]	u_spi_slave/genblk2.miso_shift_reg[0]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C13[2][A]	u_spi_slave/genblk2.miso_shift_reg[0]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[0]
19.356	-0.043	tSu		1	R11C13[2][A]	u_spi_slave/genblk2.miso_shift_reg[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 27.807%; route: 2.205, 59.772%; tC2Q: 0.458, 12.422%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path16

Path Summary:

Slack	6.067
Data Arrival Time	13.289
Data Required Time	19.356
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.miso_shift_reg[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
9.599	3.615	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
10.057	0.458	tC2Q	FF	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
11.538	1.481	tNET	FF	1	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/I3
12.564	1.026	tINS	FR	8	R11C13[0][A]	u_spi_slave/genblk2.tx_cnt11/F
13.289	0.725	tNET	RR	1	R11C13[2][B]	u_spi_slave/genblk2.miso_shift_reg[1]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					DEFAULT_CLK(clock)
15.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
15.984	0.984	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
19.599	3.615	tNET	FF	1	R11C13[2][B]	u_spi_slave/genblk2.miso_shift_reg[1]/CLK
19.399	-0.200	tUnc				u_spi_slave/genblk2.miso_shift_reg[1]
19.356	-0.043	tSu		1	R11C13[2][B]	u_spi_slave/genblk2.miso_shift_reg[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%
Arrival Data Path Delay	cell: 1.026, 27.807%; route: 2.205, 59.772%; tC2Q: 0.458, 12.422%
Required Clock Path Delay	cell: 0.984, 21.405%; route: 3.615, 78.595%

Path17

Path Summary:

Slack	6.191
Data Arrival Time	7.613
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[3]
To	u_spi_slave/genblk1.mosi_shift_reg[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/Q
6.514	1.651	tNET	FF	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[1]/I2
7.613	1.099	tINS	FF	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[1]/F
7.613	0.000	tNET	FF	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[1]
13.805	-0.400	tSu		1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 1.099, 34.250%; route: 1.651, 51.467%; tC2Q: 0.458, 14.284%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path18

Path Summary:

Slack	6.191
Data Arrival Time	7.613
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[3]
To	u_spi_slave/genblk1.mosi_shift_reg[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/Q
6.514	1.651	tNET	FF	1	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[0]/I2
7.613	1.099	tINS	FF	1	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[0]/F
7.613	0.000	tNET	FF	1	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg[0]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[0]
13.805	-0.400	tSu		1	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 1.099, 34.250%; route: 1.651, 51.467%; tC2Q: 0.458, 14.284%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path19

Path Summary:

Slack	6.259
Data Arrival Time	7.546
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt_fast[0]
To	u_spi_slave/genblk1.rx_cnt[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_fast[0]/CLK
4.863	0.458	tC2Q	RR	4	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_fast[0]/Q
5.289	0.426	tNET	RR	1	R11C22[1][B]	u_spi_slave/g0_i_o2/I0
6.388	1.099	tINS	RF	1	R11C22[1][B]	u_spi_slave/g0_i_o2/F
6.724	0.336	tNET	FF	1	R11C22[0][B]	u_spi_slave/g0_3_0/I0
7.546	0.822	tINS	FF	1	R11C22[0][B]	u_spi_slave/g0_3_0/F
7.546	0.000	tNET	FF	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.rx_cnt[3]
13.805	-0.400	tSu		1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 1.921, 61.154%; route: 0.762, 24.255%; tC2Q: 0.458, 14.591%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path20

Path Summary:

Slack	6.433
Data Arrival Time	7.372
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[3]
To	u_spi_slave/genblk1.mosi_shift_reg[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/Q
6.340	1.477	tNET	FF	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[7]/I2
7.372	1.032	tINS	FF	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[7]/F
7.372	0.000	tNET	FF	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[7]
13.805	-0.400	tSu		1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 1.032, 34.783%; route: 1.477, 49.770%; tC2Q: 0.458, 15.448%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path21

Path Summary:

Slack	6.515
Data Arrival Time	7.290
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[4]
To	u_spi_slave/genblk1.mosi_shift_reg[5]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/Q
6.191	1.328	tNET	FF	1	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[5]/I3
7.290	1.099	tINS	FF	1	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[5]/F
7.290	0.000	tNET	FF	1	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg[5]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg[5]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[5]
13.805	-0.400	tSu		1	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg[5]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 1.099, 38.089%; route: 1.328, 46.027%; tC2Q: 0.458, 15.885%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path22

Path Summary:

Slack	6.536
Data Arrival Time	7.268
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[3]
To	u_spi_slave/genblk1.mosi_shift_reg[4]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/Q
6.169	1.306	tNET	FF	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[4]/I2
7.268	1.099	tINS	FF	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[4]/F
7.268	0.000	tNET	FF	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[4]
13.805	-0.400	tSu		1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 1.099, 38.376%; route: 1.306, 45.619%; tC2Q: 0.458, 16.005%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path23

Path Summary:

Slack	6.607
Data Arrival Time	7.198
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[4]
To	u_spi_slave/genblk1.mosi_shift_reg[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/Q
6.376	1.513	tNET	FF	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[3]/I3
7.198	0.822	tINS	FF	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[3]/F
7.198	0.000	tNET	FF	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[3]
13.805	-0.400	tSu		1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.822, 29.430%; route: 1.513, 54.160%; tC2Q: 0.458, 16.410%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path24

Path Summary:

Slack	6.607
Data Arrival Time	7.198
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[4]
To	u_spi_slave/genblk1.mosi_shift_reg[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/Q
6.376	1.513	tNET	FF	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[2]/I3
7.198	0.822	tINS	FF	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[2]/F
7.198	0.000	tNET	FF	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[2]
13.805	-0.400	tSu		1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.822, 29.430%; route: 1.513, 54.160%; tC2Q: 0.458, 16.410%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Path25

Path Summary:

Slack	6.834
Data Arrival Time	6.970
Data Required Time	13.805
From	u_spi_slave/genblk1.rx_cnt[3]
To	u_spi_slave/genblk1.mosi_shift_reg[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
4.405	3.423	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
4.863	0.458	tC2Q	RF	11	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/Q
6.344	1.481	tNET	FF	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[6]/I2
6.970	0.626	tINS	FF	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[6]/F
6.970	0.000	tNET	FF	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
10.982	0.982	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
14.405	3.423	tNET	RR	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/CLK
14.205	-0.200	tUnc				u_spi_slave/genblk1.mosi_shift_reg[6]
13.805	-0.400	tSu		1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%
Arrival Data Path Delay	cell: 0.626, 24.400%; route: 1.481, 57.735%; tC2Q: 0.458, 17.865%
Required Clock Path Delay	cell: 0.982, 22.292%; route: 3.423, 77.708%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.708
Data Arrival Time	4.118
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt[0]
To	u_spi_slave/genblk1.rx_cnt[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/CLK
3.744	0.333	tC2Q	RR	4	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/Q
3.746	0.002	tNET	RR	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt_0_0[0]/I0
4.118	0.372	tINS	RF	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt_0_0[0]/F
4.118	0.000	tNET	FF	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[0]
3.411	0.000	tHld		1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path2

Path Summary:

Slack	0.709
Data Arrival Time	4.119
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt_fast[1]
To	u_spi_slave/genblk1.rx_cnt_fast[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]/CLK
3.744	0.333	tC2Q	RR	3	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]/Q
3.747	0.004	tNET	RR	1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_0_fast_0[1]/I0
4.119	0.372	tINS	RF	1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_0_fast_0[1]/F
4.119	0.000	tNET	FF	1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt_fast[1]
3.411	0.000	tHld		1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path3

Path Summary:

Slack	0.709
Data Arrival Time	4.119
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt[5]
To	u_spi_slave/genblk1.rx_cnt[5]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/CLK
3.744	0.333	tC2Q	RR	10	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/Q
3.747	0.004	tNET	RR	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt_0_0[5]/I3
4.119	0.372	tINS	RF	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt_0_0[5]/F
4.119	0.000	tNET	FF	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[5]
3.411	0.000	tHld		1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path4

Path Summary:

Slack	0.709
Data Arrival Time	4.119
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt_fast[0]
To	u_spi_slave/genblk1.rx_cnt_fast[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_fast[0]/CLK
3.744	0.333	tC2Q	RR	4	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_fast[0]/Q
3.747	0.004	tNET	RR	1	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_0_fast_0[0]/I0
4.119	0.372	tINS	RF	1	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_0_fast_0[0]/F
4.119	0.000	tNET	FF	1	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_fast[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_fast[0]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt_fast[0]
3.411	0.000	tHld		1	R11C22[0][A]	u_spi_slave/genblk1.rx_cnt_fast[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path5

Path Summary:

Slack	0.710
Data Arrival Time	4.121
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt[4]
To	u_spi_slave/genblk1.rx_cnt[4]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/CLK
3.744	0.333	tC2Q	RR	11	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/Q
3.749	0.005	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt_0_0[4]/I3
4.121	0.372	tINS	RF	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt_0_0[4]/F
4.121	0.000	tNET	FF	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[4]
3.411	0.000	tHld		1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path6

Path Summary:

Slack	0.710
Data Arrival Time	9.239
Data Required Time	8.529
From	u_spi_slave/genblk2.tx_cnt[2]
To	u_spi_slave/genblk2.tx_cnt[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
8.862	0.333	tC2Q	FR	7	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/Q
8.867	0.005	tNET	RR	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt_0_0[2]/I1
9.239	0.372	tINS	RF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt_0_0[2]/F
9.239	0.000	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
8.529	0.000	tUnc				u_spi_slave/genblk2.tx_cnt[2]
8.529	0.000	tHld		1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%

Path7

Path Summary:

Slack	0.839
Data Arrival Time	9.383
Data Required Time	8.544
From	u_spi_slave/genblk2.tx_cnt[0]
To	u_spi_slave/genblk2.tx_cnt[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/CLK
8.862	0.333	tC2Q	FR	6	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/Q
9.383	0.521	tNET	RR	1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]/CLK
8.529	0.000	tUnc				u_spi_slave/genblk2.tx_cnt[1]
8.544	0.015	tHld		1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 60.980%; tC2Q: 0.333, 39.020%
Required Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%

Path8

Path Summary:

Slack	0.839
Data Arrival Time	9.383
Data Required Time	8.544
From	u_spi_slave/genblk2.tx_cnt[0]
To	u_spi_slave/genblk2.tx_cnt[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/CLK
8.862	0.333	tC2Q	FR	6	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/Q
9.383	0.521	tNET	RR	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]/CLK
8.529	0.000	tUnc				u_spi_slave/genblk2.tx_cnt[2]
8.544	0.015	tHld		1	R11C23[1][A]	u_spi_slave/genblk2.tx_cnt[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 60.980%; tC2Q: 0.333, 39.020%
Required Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%

Path9

Path Summary:

Slack	0.843
Data Arrival Time	4.268
Data Required Time	3.426
From	u_spi_slave/genblk1.rx_cnt[3]
To	u_spi_slave/genblk1.rx_cnt[4]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
3.744	0.333	tC2Q	RR	11	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/Q
4.268	0.524	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[4]
3.426	0.015	tHld		1	R11C22[1][A]	u_spi_slave/genblk1.rx_cnt[4]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.524, 61.141%; tC2Q: 0.333, 38.859%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path10

Path Summary:

Slack	0.893
Data Arrival Time	4.303
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt[1]
To	u_spi_slave/genblk1.rx_cnt[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/CLK
3.744	0.333	tC2Q	RR	3	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/Q
3.747	0.004	tNET	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt_0_0[1]/I0
4.303	0.556	tINS	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt_0_0[1]/F
4.303	0.000	tNET	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[1]
3.411	0.000	tHld		1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path11

Path Summary:

Slack	0.894
Data Arrival Time	9.423
Data Required Time	8.529
From	u_spi_slave/genblk2.tx_cnt[0]
To	u_spi_slave/genblk2.tx_cnt[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/CLK
8.862	0.333	tC2Q	FR	6	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/Q
8.867	0.005	tNET	RR	1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt_0_0[0]/I0
9.423	0.556	tINS	RR	1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt_0_0[0]/F
9.423	0.000	tNET	RR	1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]/CLK
8.529	0.000	tUnc				u_spi_slave/genblk2.tx_cnt[0]
8.529	0.000	tHld		1	R11C23[2][A]	u_spi_slave/genblk2.tx_cnt[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%
Arrival Data Path Delay	cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%

Path12

Path Summary:

Slack	0.943
Data Arrival Time	4.353
Data Required Time	3.411
From	u_spi_slave/genblk1.mosi_shift_reg[6]
To	u_spi_slave/genblk1.mosi_shift_reg[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/CLK
3.744	0.333	tC2Q	RR	2	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/Q
3.981	0.238	tNET	RR	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[7]/I1
4.353	0.372	tINS	RF	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[7]/F
4.353	0.000	tNET	FF	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[7]
3.411	0.000	tHld		1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 39.452%; route: 0.238, 25.196%; tC2Q: 0.333, 35.352%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path13

Path Summary:

Slack	0.943
Data Arrival Time	4.354
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt[1]
To	u_spi_slave/genblk1.rx_cnt[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/CLK
3.744	0.333	tC2Q	RF	3	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/Q
3.982	0.238	tNET	FF	1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt_0_0[2]/I0
4.354	0.372	tINS	FF	1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt_0_0[2]/F
4.354	0.000	tNET	FF	1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt[2]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[2]
3.411	0.000	tHld		1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path14

Path Summary:

Slack	1.061
Data Arrival Time	9.589
Data Required Time	8.529
From	u_spi_slave/genblk2.tx_cnt[1]
To	u_spi_slave/genblk2.tx_cnt[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]/CLK
8.862	0.333	tC2Q	FR	6	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]/Q
8.865	0.004	tNET	RR	1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt_0_0[1]/I0
9.589	0.724	tINS	RR	1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt_0_0[1]/F
9.589	0.000	tNET	RR	1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT14[B]	SCLK_ibuf/I
5.847	0.847	tINS	FF	27	IOT14[B]	SCLK_ibuf/O
8.529	2.682	tNET	FF	1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]/CLK
8.529	0.000	tUnc				u_spi_slave/genblk2.tx_cnt[1]
8.529	0.000	tHld		1	R11C23[1][B]	u_spi_slave/genblk2.tx_cnt[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 0.847, 24.001%; route: 2.682, 75.999%

Path15

Path Summary:

Slack	1.066
Data Arrival Time	4.476
Data Required Time	3.411
From	u_spi_slave/genblk1.rx_cnt[3]
To	u_spi_slave/genblk1.rx_cnt[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
3.744	0.333	tC2Q	RR	11	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/Q
3.752	0.008	tNET	RR	1	R11C22[0][B]	u_spi_slave/g0_3_0/I2
4.476	0.724	tINS	RR	1	R11C22[0][B]	u_spi_slave/g0_3_0/F
4.476	0.000	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[3]
3.411	0.000	tHld		1	R11C22[0][B]	u_spi_slave/genblk1.rx_cnt[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.724, 67.943%; route: 0.008, 0.776%; tC2Q: 0.333, 31.281%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path16

Path Summary:

Slack	1.101
Data Arrival Time	4.526
Data Required Time	3.426
From	u_spi_slave/genblk1.rx_cnt[0]
To	u_spi_slave/genblk1.rx_cnt_fast[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/CLK
3.744	0.333	tC2Q	RR	4	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/Q
4.526	0.782	tNET	RR	1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt_fast[1]
3.426	0.015	tHld		1	R11C23[0][A]	u_spi_slave/genblk1.rx_cnt_fast[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.782, 70.122%; tC2Q: 0.333, 29.878%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path17

Path Summary:

Slack	1.101
Data Arrival Time	4.526
Data Required Time	3.426
From	u_spi_slave/genblk1.rx_cnt[0]
To	u_spi_slave/genblk1.rx_cnt[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/CLK
3.744	0.333	tC2Q	RR	4	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/Q
4.526	0.782	tNET	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[1]
3.426	0.015	tHld		1	R11C22[2][A]	u_spi_slave/genblk1.rx_cnt[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.782, 70.122%; tC2Q: 0.333, 29.878%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path18

Path Summary:

Slack	1.101
Data Arrival Time	4.526
Data Required Time	3.426
From	u_spi_slave/genblk1.rx_cnt[0]
To	u_spi_slave/genblk1.rx_cnt[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/CLK
3.744	0.333	tC2Q	RR	4	R11C24[0][A]	u_spi_slave/genblk1.rx_cnt[0]/Q
4.526	0.782	tNET	RR	1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt[2]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt[2]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.rx_cnt[2]
3.426	0.015	tHld		1	R11C23[0][B]	u_spi_slave/genblk1.rx_cnt[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.782, 70.122%; tC2Q: 0.333, 29.878%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path19

Path Summary:

Slack	1.277
Data Arrival Time	4.687
Data Required Time	3.411
From	u_spi_slave/genblk1.mosi_shift_reg[3]
To	u_spi_slave/genblk1.mosi_shift_reg[4]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/CLK
3.744	0.333	tC2Q	RR	2	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/Q
4.315	0.572	tNET	RR	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[4]/I1
4.687	0.372	tINS	RF	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg_0_0[4]/F
4.687	0.000	tNET	FF	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[4]
3.411	0.000	tHld		1	R11C15[1][A]	u_spi_slave/genblk1.mosi_shift_reg[4]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.372, 29.133%; route: 0.572, 44.762%; tC2Q: 0.333, 26.105%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path20

Path Summary:

Slack	1.292
Data Arrival Time	4.702
Data Required Time	3.411
From	u_spi_slave/genblk1.mosi_shift_reg[2]
To	u_spi_slave/genblk1.mosi_shift_reg[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/CLK
3.744	0.333	tC2Q	RF	2	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/Q
3.978	0.234	tNET	FF	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[3]/I1
4.702	0.724	tINS	FR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[3]/F
4.702	0.000	tNET	RR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[3]
3.411	0.000	tHld		1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.724, 56.045%; route: 0.234, 18.151%; tC2Q: 0.333, 25.803%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path21

Path Summary:

Slack	1.294
Data Arrival Time	4.704
Data Required Time	3.411
From	u_spi_slave/genblk1.mosi_shift_reg[0]
To	u_spi_slave/genblk1.mosi_shift_reg[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg[0]/CLK
3.744	0.333	tC2Q	RF	2	R11C13[1][A]	u_spi_slave/genblk1.mosi_shift_reg[0]/Q
3.978	0.234	tNET	FF	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[1]/I1
4.704	0.726	tINS	FR	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[1]/F
4.704	0.000	tNET	RR	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[1]
3.411	0.000	tHld		1	R11C13[1][B]	u_spi_slave/genblk1.mosi_shift_reg[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.726, 56.113%; route: 0.234, 18.123%; tC2Q: 0.333, 25.764%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path22

Path Summary:

Slack	1.300
Data Arrival Time	4.710
Data Required Time	3.411
From	u_spi_slave/genblk1.mosi_shift_reg[5]
To	u_spi_slave/genblk1.mosi_shift_reg[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg[5]/CLK
3.744	0.333	tC2Q	RR	2	R11C14[1][A]	u_spi_slave/genblk1.mosi_shift_reg[5]/Q
3.986	0.243	tNET	RR	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[6]/I1
4.710	0.724	tINS	RR	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg_0_0[6]/F
4.710	0.000	tNET	RR	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[6]
3.411	0.000	tHld		1	R11C14[1][B]	u_spi_slave/genblk1.mosi_shift_reg[6]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.724, 55.695%; route: 0.243, 18.663%; tC2Q: 0.333, 25.642%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path23

Path Summary:

Slack	1.391
Data Arrival Time	4.816
Data Required Time	3.426
From	u_spi_slave/genblk1.rx_cnt[5]
To	u_spi_slave/genblk1.mosi_shift_reg[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/CLK
3.744	0.333	tC2Q	RR	10	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/Q
4.816	1.073	tNET	RR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[3]
3.426	0.015	tHld		1	R11C15[0][B]	u_spi_slave/genblk1.mosi_shift_reg[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.073, 76.290%; tC2Q: 0.333, 23.710%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path24

Path Summary:

Slack	1.391
Data Arrival Time	4.816
Data Required Time	3.426
From	u_spi_slave/genblk1.rx_cnt[5]
To	u_spi_slave/genblk1.mosi_shift_reg[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/CLK
3.744	0.333	tC2Q	RR	10	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/Q
4.816	1.073	tNET	RR	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[2]
3.426	0.015	tHld		1	R11C15[0][A]	u_spi_slave/genblk1.mosi_shift_reg[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.073, 76.290%; tC2Q: 0.333, 23.710%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Path25

Path Summary:

Slack	1.391
Data Arrival Time	4.816
Data Required Time	3.426
From	u_spi_slave/genblk1.rx_cnt[5]
To	u_spi_slave/genblk1.mosi_shift_reg[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/CLK
3.744	0.333	tC2Q	RR	10	R11C21[0][A]	u_spi_slave/genblk1.rx_cnt[5]/Q
4.816	1.073	tNET	RR	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT14[B]	SCLK_ibuf/I
0.844	0.844	tINS	RR	27	IOT14[B]	SCLK_ibuf/O
3.411	2.566	tNET	RR	1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]/CLK
3.411	0.000	tUnc				u_spi_slave/genblk1.mosi_shift_reg[7]
3.426	0.015	tHld		1	R11C14[2][A]	u_spi_slave/genblk1.mosi_shift_reg[7]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.073, 76.290%; tC2Q: 0.333, 23.710%
Required Clock Path Delay	cell: 0.844, 24.758%; route: 2.566, 75.242%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk2.miso_shift_reg[7]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk2.miso_shift_reg[7]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk2.miso_shift_reg[7]/CLK

MPW2

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk2.miso_shift_reg[5]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk2.miso_shift_reg[5]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk2.miso_shift_reg[5]/CLK

MPW3

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk2.miso_shift_reg[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk2.miso_shift_reg[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk2.miso_shift_reg[1]/CLK

MPW4

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk1.mosi_shift_reg[2]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk1.mosi_shift_reg[2]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk1.mosi_shift_reg[2]/CLK

MPW5

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk1.mosi_shift_reg[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk1.mosi_shift_reg[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk1.mosi_shift_reg[1]/CLK

MPW6

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk2.miso_shift_reg[2]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk2.miso_shift_reg[2]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk2.miso_shift_reg[2]/CLK

MPW7

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk1.mosi_shift_reg[0]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk1.mosi_shift_reg[0]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk1.mosi_shift_reg[0]/CLK

MPW8

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk1.rx_cnt_fast[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk1.rx_cnt_fast[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk1.rx_cnt_fast[1]/CLK

MPW9

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk2.tx_cnt[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk2.tx_cnt[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk2.tx_cnt[1]/CLK

MPW10

MPW Summary:

Slack:	2.562
Actual Width:	3.812
Required Width:	1.250
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_spi_slave/genblk1.mosi_shift_reg[7]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	SCLK_ibuf/I
5.984	0.984	tINS	FF	SCLK_ibuf/O
9.599	3.615	tNET	FF	u_spi_slave/genblk1.mosi_shift_reg[7]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	SCLK_ibuf/I
10.844	0.844	tINS	RR	SCLK_ibuf/O
13.411	2.566	tNET	RR	u_spi_slave/genblk1.mosi_shift_reg[7]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
27	SCLK_c	2.297	3.615
11	un4_rx_cnt_axb3	6.191	1.651
11	un4_rx_cnt_axb4	6.458	1.513
10	un4_rx_cnt_axb5	6.661	1.855
8	tx_cnt11	5.707	1.194
7	un3_MISO_i[2]	5.707	1.498
6	un3_MISO_i[1]	6.002	1.640
6	CO0	6.255	1.972
4	rx_cnt[0]	8.214	1.192
4	un4_rx_cnt_axb2	6.734	0.832

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C13	0.278
R11C22	0.250
R11C14	0.222
R11C15	0.222
R11C23	0.208
R11C21	0.111
R1C14	0.083
R11C12	0.083
R11C24	0.042
R1C13	0.042

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command