#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019 #install: D:\Gowin\sdio_sweg\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-050 # Mon Nov 11 16:08:01 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\Gowin\sdio_sweg\IDE\ipcore\SDIOSlaveController\data\sdio_slave_controller_top.v" (library work) @I:"D:\Gowin\sdio_sweg\IDE\ipcore\SDIOSlaveController\data\sdio_slave_controller_top.v":"C:\Users\guitong\Desktop\sdio_reference_design\sdio_test\src\sdio_slave_controller\temp\sdioslave\define.vh" (library work) @I:"D:\Gowin\sdio_sweg\IDE\ipcore\SDIOSlaveController\data\sdio_slave_controller_top.v":"D:\Gowin\sdio_sweg\IDE\ipcore\SDIOSlaveController\data\static_macro_define.vh" (library work) @I::"D:\Gowin\sdio_sweg\IDE\ipcore\SDIOSlaveController\data\sdio_slave_controller.v" (library work) @I:"D:\Gowin\sdio_sweg\IDE\ipcore\SDIOSlaveController\data\sdio_slave_controller.v":"C:\Users\guitong\Desktop\sdio_reference_design\sdio_test\src\sdio_slave_controller\temp\sdioslave\sdio_param.vh" (library work) Verilog syntax check successful! Selecting top level module SDIO_Slave_Controller_Top Running optimization stage 1 on \~sdio_if.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~cmd_dec.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~sdio_biu.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~card_fixed_regs.SDIO_Slave_Controller_Top _16744448_0_1_2_3_4_5 ....... Running optimization stage 1 on \~crc7_chk.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~resp_gen.SDIO_Slave_Controller_Top _Z1 ....... Running optimization stage 1 on \~resp_conv.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~fn0_reg.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~slv_cpu_if.SDIO_Slave_Controller_Top _3_5_4 ....... Running optimization stage 1 on \~cmd53_ctrl.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~cmd53_tx_rx.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~cis_fnx_if.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~irq_gen.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~cmd19_tx.SDIO_Slave_Controller_Top ....... Running optimization stage 1 on \~sdio_slave_ctrl.SDIO_Slave_Controller_Top ....... @N:CG364 : sdio_slave_controller_top.v(5) | Synthesizing module SDIO_Slave_Controller_Top in library work. Running optimization stage 1 on SDIO_Slave_Controller_Top ....... Running optimization stage 2 on SDIO_Slave_Controller_Top ....... Running optimization stage 2 on \~sdio_slave_ctrl.SDIO_Slave_Controller_Top ....... Running optimization stage 2 on \~cmd19_tx.SDIO_Slave_Controller_Top ....... Extracted state machine for register c_state State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on \~irq_gen.SDIO_Slave_Controller_Top ....... Running optimization stage 2 on \~cis_fnx_if.SDIO_Slave_Controller_Top ....... Running optimization stage 2 on \~cmd53_tx_rx.SDIO_Slave_Controller_Top ....... Extracted state machine for register c_state State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top ....... Running optimization stage 2 on \~cmd53_ctrl.SDIO_Slave_Controller_Top ....... Extracted state machine for register c_state State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 Running optimization stage 2 on \~slv_cpu_if.SDIO_Slave_Controller_Top _3_5_4 ....... Running optimization stage 2 on \~fn0_reg.SDIO_Slave_Controller_Top ....... Extracted state machine for register reg102_d1 State machine has 17 reachable states with original encodings of: 00000 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Extracted state machine for register reg100_d1 State machine has 3 reachable states with original encodings of: 00 10 11 Extracted state machine for register reg7_d1 State machine has 3 reachable states with original encodings of: 00 10 11 Extracted state machine for register c_state State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on \~resp_conv.SDIO_Slave_Controller_Top ....... Extracted state machine for register c_state State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on \~resp_gen.SDIO_Slave_Controller_Top _Z1 ....... Extracted state machine for register c_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on \~crc7_chk.SDIO_Slave_Controller_Top ....... Running optimization stage 2 on \~card_fixed_regs.SDIO_Slave_Controller_Top _16744448_0_1_2_3_4_5 ....... Running optimization stage 2 on \~sdio_biu.SDIO_Slave_Controller_Top ....... Extracted state machine for register io_current_state State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 Running optimization stage 2 on \~cmd_dec.SDIO_Slave_Controller_Top ....... Extracted state machine for register c_state State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 Running optimization stage 2 on \~sdio_if.SDIO_Slave_Controller_Top ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 120MB peak: 124MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime Process completed successfully. # Mon Nov 11 16:08:08 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode @N:NF107 : sdio_slave_controller_top.v(5) | Selected library: work cell: SDIO_Slave_Controller_Top view verilog as top level @N:NF107 : sdio_slave_controller_top.v(5) | Selected library: work cell: SDIO_Slave_Controller_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Nov 11 16:08:09 2019 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: sdio_slave_controller_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 19MB peak: 19MB) Process took 0h:00m:06s realtime, 0h:00m:05s cputime Process completed successfully. # Mon Nov 11 16:08:09 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode @N:NF107 : sdio_slave_controller_top.v(5) | Selected library: work cell: SDIO_Slave_Controller_Top view verilog as top level @N:NF107 : sdio_slave_controller_top.v(5) | Selected library: work cell: SDIO_Slave_Controller_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 96MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Nov 11 16:08:11 2019 ###########################################################] Premap Report # Mon Nov 11 16:08:12 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @A:MF827 : | No constraint file specified. Linked File: sdio_slave_controller_scck.rpt Printing clock summary report in "C:\Users\guitong\Desktop\sdio_reference_design\sdio_test\src\sdio_slave_controller\temp\sdioslave\rev_1\sdio_slave_controller_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 136MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 149MB) Encoding state machine c_state[5:0] (in view: work.\\\~cmd_dec\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 Encoding state machine io_current_state_1[5:0] (in view: work.\\\~sdio_biu\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 Encoding state machine c_state[3:0] (in view: work.\\\~resp_gen\.SDIO_Slave_Controller_Top\ _Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine c_state[2:0] (in view: work.\\\~resp_conv\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine reg102_d1_1[16:0] (in view: work.\\\~fn0_reg\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 00000 -> 00000000000000001 10000 -> 00000000000000010 10001 -> 00000000000000100 10010 -> 00000000000001000 10011 -> 00000000000010000 10100 -> 00000000000100000 10101 -> 00000000001000000 10110 -> 00000000010000000 10111 -> 00000000100000000 11000 -> 00000001000000000 11001 -> 00000010000000000 11010 -> 00000100000000000 11011 -> 00001000000000000 11100 -> 00010000000000000 11101 -> 00100000000000000 11110 -> 01000000000000000 11111 -> 10000000000000000 Encoding state machine reg100_d1[2:0] (in view: work.\\\~fn0_reg\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 00 -> 00 10 -> 10 11 -> 11 Encoding state machine reg7_d1_1[2:0] (in view: work.\\\~fn0_reg\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 00 -> 00 10 -> 10 11 -> 11 Encoding state machine c_state[2:0] (in view: work.\\\~fn0_reg\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine c_state[5:0] (in view: work.\\\~cmd53_ctrl\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 Encoding state machine c_state[9:0] (in view: work.\\\~cmd53_tx_rx\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 0000 -> 0000000001 0001 -> 0000000010 0010 -> 0000000100 0011 -> 0000001000 0100 -> 0000010000 0101 -> 0000100000 0110 -> 0001000000 0111 -> 0010000000 1000 -> 0100000000 1001 -> 1000000000 Encoding state machine c_state[2:0] (in view: work.\\\~cmd19_tx\.SDIO_Slave_Controller_Top\ (verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB) Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------- 0 - SDIO_Slave_Controller_Top|sdio_clk 168.2 MHz 5.946 inferred Autoconstr_clkgroup_0 1382 0 - SDIO_Slave_Controller_Top|cpu_clk 544.5 MHz 1.837 inferred Autoconstr_clkgroup_1 189 0 - SDIO_Slave_Controller_Top|clk_2mhz 317.9 MHz 3.145 inferred Autoconstr_clkgroup_2 19 ========================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SDIO_Slave_Controller_Top|sdio_clk 1382 sdio_clk(port) u_sdio_slave_ctrl.u_cmd19_tx.sdio_tuning_start.C u_sdio_slave_ctrl.u_cmd_dec.genblk1.sd_clk_d1.D[0] u_sdio_slave_ctrl.u_irq_gen.un1_clk.I[0](inv) SDIO_Slave_Controller_Top|cpu_clk 189 cpu_clk(port) u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_cs_d1.C - - SDIO_Slave_Controller_Top|clk_2mhz 19 clk_2mhz(port) u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_d4.C - - ============================================================================================================================================================================================================================= ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 3 non-gated/non-generated clock tree(s) driving 1589 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 sdio_clk port 1381 ENCRYPTED ClockId_0_1 cpu_clk port 189 ENCRYPTED ClockId_0_2 clk_2mhz port 19 ENCRYPTED ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\guitong\Desktop\sdio_reference_design\sdio_test\src\sdio_slave_controller\temp\sdioslave\rev_1\sdio_slave_controller.sap. Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 237MB peak: 239MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 238MB peak: 239MB) Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 240MB peak: 240MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 158MB peak: 240MB) Process took 0h:00m:04s realtime, 0h:00m:03s cputime # Mon Nov 11 16:08:17 2019 ###########################################################] Map & Optimize Report # Mon Nov 11 16:08:17 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB) Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 245MB peak: 245MB) Finished factoring (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:06s; Memory used current: 269MB peak: 269MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:08s; Memory used current: 262MB peak: 287MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:09s; Memory used current: 263MB peak: 287MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:15s; Memory used current: 274MB peak: 287MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 274MB peak: 287MB) Finished preparing to map (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:17s; Memory used current: 274MB peak: 287MB) Finished technology mapping (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:19s; Memory used current: 299MB peak: 334MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:19s -2.80ns 3451 / 1567 2 0h:00m:19s -2.79ns 3465 / 1567 3 0h:00m:20s -2.67ns 3459 / 1567 4 0h:00m:20s -2.79ns 3461 / 1567 5 0h:00m:20s -2.66ns 3461 / 1567 6 0h:00m:21s -2.79ns 3461 / 1567 7 0h:00m:21s -2.79ns 3461 / 1567 8 0h:00m:21s -2.79ns 3461 / 1567 9 0h:00m:21s -2.79ns 3461 / 1567 Timing driven replication report Added 13 Registers via timing driven replication Added 13 LUTs via timing driven replication 10 0h:00m:24s -2.11ns 3496 / 1580 11 0h:00m:24s -1.40ns 3498 / 1580 12 0h:00m:25s -1.40ns 3502 / 1580 13 0h:00m:25s -1.40ns 3503 / 1580 14 0h:00m:25s -1.40ns 3508 / 1580 15 0h:00m:25s -1.40ns 3513 / 1580 Timing driven replication report Added 11 Registers via timing driven replication Added 11 LUTs via timing driven replication 16 0h:00m:25s -1.40ns 3522 / 1591 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:26s; Memory used current: 302MB peak: 334MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port @W: : | Converting bidirection inout port to output port. Because it's a pure output port @W: : | Converting bidirection inout port to inpure port. Because it's a pure input port Finished restoring hierarchy (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:27s; Memory used current: 303MB peak: 334MB) Start Writing Netlists (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:27s; Memory used current: 224MB peak: 334MB) Writing Analyst data base C:\Users\guitong\Desktop\sdio_reference_design\sdio_test\src\sdio_slave_controller\temp\sdioslave\rev_1\synwork\sdio_slave_controller_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 298MB peak: 334MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:31s; Memory used current: 298MB peak: 334MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:31s; Memory used current: 299MB peak: 334MB) Start final timing analysis (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 290MB peak: 334MB) @W:MT420 : | Found inferred clock SDIO_Slave_Controller_Top|sdio_clk with period 5.67ns. Please declare a user-defined clock on port sdio_clk. @W:MT420 : | Found inferred clock SDIO_Slave_Controller_Top|cpu_clk with period 2.85ns. Please declare a user-defined clock on port cpu_clk. @W:MT420 : | Found inferred clock SDIO_Slave_Controller_Top|clk_2mhz with period 2.71ns. Please declare a user-defined clock on port clk_2mhz. ##### START OF TIMING REPORT #####[ # Timing report written on Mon Nov 11 16:08:51 2019 # Top view: SDIO_Slave_Controller_Top Requested Frequency: 176.4 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.001 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------- SDIO_Slave_Controller_Top|clk_2mhz 369.5 MHz 314.1 MHz 2.706 3.184 -0.478 inferred Autoconstr_clkgroup_2 SDIO_Slave_Controller_Top|cpu_clk 351.0 MHz 298.4 MHz 2.849 3.351 -0.503 inferred Autoconstr_clkgroup_1 SDIO_Slave_Controller_Top|sdio_clk 176.4 MHz 149.9 MHz 5.670 6.671 -1.001 inferred Autoconstr_clkgroup_0 System 150.0 MHz 220.5 MHz 6.667 4.536 2.131 system system_clkgroup ============================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------- System SDIO_Slave_Controller_Top|sdio_clk | 5.671 3.545 | No paths - | No paths - | No paths - System SDIO_Slave_Controller_Top|cpu_clk | 2.849 2.131 | No paths - | No paths - | No paths - SDIO_Slave_Controller_Top|sdio_clk System | 5.671 3.443 | No paths - | No paths - | No paths - SDIO_Slave_Controller_Top|sdio_clk SDIO_Slave_Controller_Top|sdio_clk | 5.671 -1.001 | 5.671 2.556 | 2.835 -0.097 | No paths - SDIO_Slave_Controller_Top|sdio_clk SDIO_Slave_Controller_Top|cpu_clk | Diff grp - | No paths - | No paths - | No paths - SDIO_Slave_Controller_Top|sdio_clk SDIO_Slave_Controller_Top|clk_2mhz | Diff grp - | No paths - | No paths - | No paths - SDIO_Slave_Controller_Top|cpu_clk SDIO_Slave_Controller_Top|sdio_clk | Diff grp - | No paths - | Diff grp - | No paths - SDIO_Slave_Controller_Top|cpu_clk SDIO_Slave_Controller_Top|cpu_clk | 2.849 -0.503 | No paths - | No paths - | No paths - SDIO_Slave_Controller_Top|clk_2mhz SDIO_Slave_Controller_Top|sdio_clk | Diff grp - | No paths - | Diff grp - | No paths - SDIO_Slave_Controller_Top|clk_2mhz SDIO_Slave_Controller_Top|clk_2mhz | 2.706 -0.478 | No paths - | No paths - | No paths - ================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SDIO_Slave_Controller_Top|clk_2mhz ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[0] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[0] 0.243 -0.478 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[1] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[1] 0.243 -0.443 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[4] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[4] 0.243 -0.429 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[3] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[3] 0.243 -0.408 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[2] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[2] 0.243 -0.408 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[5] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[5] 0.243 -0.321 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[6] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[6] 0.243 -0.268 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[7] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[7] 0.243 -0.233 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[13] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[13] 0.243 -0.230 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[8] SDIO_Slave_Controller_Top|clk_2mhz DFFC Q sd_clk_stop_cnt[8] 0.243 -0.198 =============================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[13] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[13] 2.645 -0.478 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[12] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[12] 2.645 -0.443 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en SDIO_Slave_Controller_Top|clk_2mhz DFFCE D uhs_i_en_ldmx 2.645 -0.429 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[11] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[11] 2.645 -0.408 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[10] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[10] 2.645 -0.373 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[9] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[9] 2.645 -0.338 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[8] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[8] 2.645 -0.303 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[7] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[7] 2.645 -0.268 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[6] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[6] 2.645 -0.233 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[5] SDIO_Slave_Controller_Top|clk_2mhz DFFC D sd_clk_stop_cnt_lm[5] 2.645 -0.198 ==================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.706 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.645 - Propagation time: 3.123 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.478 Number of logic level(s): 15 Starting point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[0] / Q Ending point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[13] / D The start point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[0] DFFC Q Out 0.243 0.243 - sd_clk_stop_cnt[0] Net - - 0.535 - 2 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[0] ALU I0 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[0] ALU COUT Out 0.549 1.327 - sd_clk_stop_cnt_cry[0] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[1] ALU CIN In - 1.327 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[1] ALU COUT Out 0.035 1.362 - sd_clk_stop_cnt_cry[1] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[2] ALU CIN In - 1.362 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[2] ALU COUT Out 0.035 1.397 - sd_clk_stop_cnt_cry[2] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[3] ALU CIN In - 1.397 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[3] ALU COUT Out 0.035 1.432 - sd_clk_stop_cnt_cry[3] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[4] ALU CIN In - 1.432 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[4] ALU COUT Out 0.035 1.467 - sd_clk_stop_cnt_cry[4] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[5] ALU CIN In - 1.467 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[5] ALU COUT Out 0.035 1.502 - sd_clk_stop_cnt_cry[5] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[6] ALU CIN In - 1.502 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[6] ALU COUT Out 0.035 1.537 - sd_clk_stop_cnt_cry[6] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[7] ALU CIN In - 1.537 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[7] ALU COUT Out 0.035 1.572 - sd_clk_stop_cnt_cry[7] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[8] ALU CIN In - 1.572 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[8] ALU COUT Out 0.035 1.607 - sd_clk_stop_cnt_cry[8] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[9] ALU CIN In - 1.607 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[9] ALU COUT Out 0.035 1.642 - sd_clk_stop_cnt_cry[9] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[10] ALU CIN In - 1.642 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[10] ALU COUT Out 0.035 1.677 - sd_clk_stop_cnt_cry[10] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[11] ALU CIN In - 1.677 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[11] ALU COUT Out 0.035 1.712 - sd_clk_stop_cnt_cry[11] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[12] ALU CIN In - 1.712 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[12] ALU COUT Out 0.035 1.747 - sd_clk_stop_cnt_cry[12] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_s_0[13] ALU CIN In - 1.747 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_s_0[13] ALU SUM Out 0.470 2.217 - sd_clk_stop_cnt_s[13] Net - - 0.535 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_lm_0[13] LUT4 I3 In - 2.752 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_lm_0[13] LUT4 F Out 0.371 3.123 - sd_clk_stop_cnt_lm[13] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[13] DFFC D In - 3.123 - ============================================================================================================================= Total path delay (propagation time + setup) of 3.184 is 2.114(66.4%) logic and 1.070(33.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 2.706 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.645 - Propagation time: 3.088 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.443 Number of logic level(s): 14 Starting point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[1] / Q Ending point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[13] / D The start point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[1] DFFC Q Out 0.243 0.243 - sd_clk_stop_cnt[1] Net - - 0.535 - 2 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[1] ALU I0 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[1] ALU COUT Out 0.549 1.327 - sd_clk_stop_cnt_cry[1] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[2] ALU CIN In - 1.327 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[2] ALU COUT Out 0.035 1.362 - sd_clk_stop_cnt_cry[2] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[3] ALU CIN In - 1.362 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[3] ALU COUT Out 0.035 1.397 - sd_clk_stop_cnt_cry[3] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[4] ALU CIN In - 1.397 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[4] ALU COUT Out 0.035 1.432 - sd_clk_stop_cnt_cry[4] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[5] ALU CIN In - 1.432 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[5] ALU COUT Out 0.035 1.467 - sd_clk_stop_cnt_cry[5] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[6] ALU CIN In - 1.467 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[6] ALU COUT Out 0.035 1.502 - sd_clk_stop_cnt_cry[6] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[7] ALU CIN In - 1.502 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[7] ALU COUT Out 0.035 1.537 - sd_clk_stop_cnt_cry[7] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[8] ALU CIN In - 1.537 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[8] ALU COUT Out 0.035 1.572 - sd_clk_stop_cnt_cry[8] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[9] ALU CIN In - 1.572 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[9] ALU COUT Out 0.035 1.607 - sd_clk_stop_cnt_cry[9] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[10] ALU CIN In - 1.607 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[10] ALU COUT Out 0.035 1.642 - sd_clk_stop_cnt_cry[10] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[11] ALU CIN In - 1.642 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[11] ALU COUT Out 0.035 1.677 - sd_clk_stop_cnt_cry[11] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[12] ALU CIN In - 1.677 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[12] ALU COUT Out 0.035 1.712 - sd_clk_stop_cnt_cry[12] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_s_0[13] ALU CIN In - 1.712 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_s_0[13] ALU SUM Out 0.470 2.182 - sd_clk_stop_cnt_s[13] Net - - 0.535 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_lm_0[13] LUT4 I3 In - 2.717 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_lm_0[13] LUT4 F Out 0.371 3.088 - sd_clk_stop_cnt_lm[13] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[13] DFFC D In - 3.088 - ============================================================================================================================= Total path delay (propagation time + setup) of 3.149 is 2.079(66.0%) logic and 1.070(34.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 2.706 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.645 - Propagation time: 3.088 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.443 Number of logic level(s): 14 Starting point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[0] / Q Ending point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[12] / D The start point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[0] DFFC Q Out 0.243 0.243 - sd_clk_stop_cnt[0] Net - - 0.535 - 2 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[0] ALU I0 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[0] ALU COUT Out 0.549 1.327 - sd_clk_stop_cnt_cry[0] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[1] ALU CIN In - 1.327 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[1] ALU COUT Out 0.035 1.362 - sd_clk_stop_cnt_cry[1] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[2] ALU CIN In - 1.362 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[2] ALU COUT Out 0.035 1.397 - sd_clk_stop_cnt_cry[2] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[3] ALU CIN In - 1.397 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[3] ALU COUT Out 0.035 1.432 - sd_clk_stop_cnt_cry[3] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[4] ALU CIN In - 1.432 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[4] ALU COUT Out 0.035 1.467 - sd_clk_stop_cnt_cry[4] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[5] ALU CIN In - 1.467 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[5] ALU COUT Out 0.035 1.502 - sd_clk_stop_cnt_cry[5] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[6] ALU CIN In - 1.502 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[6] ALU COUT Out 0.035 1.537 - sd_clk_stop_cnt_cry[6] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[7] ALU CIN In - 1.537 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[7] ALU COUT Out 0.035 1.572 - sd_clk_stop_cnt_cry[7] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[8] ALU CIN In - 1.572 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[8] ALU COUT Out 0.035 1.607 - sd_clk_stop_cnt_cry[8] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[9] ALU CIN In - 1.607 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[9] ALU COUT Out 0.035 1.642 - sd_clk_stop_cnt_cry[9] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[10] ALU CIN In - 1.642 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[10] ALU COUT Out 0.035 1.677 - sd_clk_stop_cnt_cry[10] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[11] ALU CIN In - 1.677 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[11] ALU COUT Out 0.035 1.712 - sd_clk_stop_cnt_cry[11] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[12] ALU CIN In - 1.712 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_cry_0[12] ALU SUM Out 0.470 2.182 - sd_clk_stop_cnt_s[12] Net - - 0.535 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_lm_0[12] LUT4 I3 In - 2.717 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt_lm_0[12] LUT4 F Out 0.371 3.088 - sd_clk_stop_cnt_lm[12] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[12] DFFC D In - 3.088 - ============================================================================================================================= Total path delay (propagation time + setup) of 3.149 is 2.079(66.0%) logic and 1.070(34.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 2.706 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.645 - Propagation time: 3.074 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.429 Number of logic level(s): 3 Starting point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[4] / Q Ending point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en / D The start point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[4] DFFC Q Out 0.243 0.243 - sd_clk_stop_cnt[4] Net - - 0.535 - 2 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_7 LUT4 I1 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_7 LUT4 F Out 0.570 1.348 - uhs_i_en_en_7 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_10 LUT3 I2 In - 1.749 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_10 LUT3 F Out 0.462 2.211 - uhs_i_en_en_10 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_ldmx LUT4 I2 In - 2.612 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_ldmx LUT4 F Out 0.462 3.074 - uhs_i_en_ldmx Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en DFFCE D In - 3.074 - ======================================================================================================================= Total path delay (propagation time + setup) of 3.135 is 1.798(57.3%) logic and 1.337(42.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 2.706 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.645 - Propagation time: 3.053 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.408 Number of logic level(s): 3 Starting point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[3] / Q Ending point: u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en / D The start point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|clk_2mhz [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.genblk1\.sd_clk_stop_cnt[3] DFFC Q Out 0.243 0.243 - sd_clk_stop_cnt[3] Net - - 0.535 - 2 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_7 LUT4 I0 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_7 LUT4 F Out 0.549 1.327 - uhs_i_en_en_7 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_10 LUT3 I2 In - 1.728 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_en_10 LUT3 F Out 0.462 2.190 - uhs_i_en_en_10 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_ldmx LUT4 I2 In - 2.591 - u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en_ldmx LUT4 F Out 0.462 3.053 - uhs_i_en_ldmx Net - - 0.000 - 1 u_sdio_slave_ctrl.u_cmd_dec.genblk1\.uhs_i_en DFFCE D In - 3.053 - ======================================================================================================================= Total path delay (propagation time + setup) of 3.114 is 1.777(57.1%) logic and 1.337(42.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SDIO_Slave_Controller_Top|cpu_clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_ext_fn_if_code[0] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q fbr1_ext_fn_if_code[0] 0.243 -0.503 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_sda_mid_manf_code[3] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q fbr1_sda_mid_manf_code[3] 0.243 -0.503 u_sdio_slave_ctrl.u_slv_cpu_if.cccr_cis_pointer[19] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q cccr_cis_pointer[19] 0.243 -0.482 u_sdio_slave_ctrl.u_slv_cpu_if.cccr_max_blk_size[8] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q cccr_max_blk_size[8] 0.243 -0.482 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_sda_mid_manf_code[9] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q fbr1_sda_mid_manf_code[9] 0.243 -0.482 u_sdio_slave_ctrl.u_slv_cpu_if.cccr_sdtc SDIO_Slave_Controller_Top|cpu_clk DFFCE Q cccr_sdtc 0.243 -0.461 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_cis_ptr[19] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q fbr1_cis_ptr[19] 0.243 -0.461 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_max_blk_size[0] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q fbr1_max_blk_size[0] 0.243 -0.395 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_mid_card_info[2] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q fbr1_mid_card_info[2] 0.243 -0.395 u_sdio_slave_ctrl.u_slv_cpu_if.cccr_cis_pointer[2] SDIO_Slave_Controller_Top|cpu_clk DFFCE Q cccr_cis_pointer[2] 0.243 -0.374 ===================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[8] SDIO_Slave_Controller_Top|cpu_clk DFFCE D slv_cpu_rd_data_35[8] 2.788 -0.503 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[19] SDIO_Slave_Controller_Top|cpu_clk DFFCE D N_917_i 2.788 -0.503 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[25] SDIO_Slave_Controller_Top|cpu_clk DFFCE D N_23_0_i 2.788 -0.482 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[2] SDIO_Slave_Controller_Top|cpu_clk DFFCE D slv_cpu_rd_data_35[2] 2.788 -0.395 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[16] SDIO_Slave_Controller_Top|cpu_clk DFFCE D slv_cpu_rd_data_35[16] 2.788 -0.395 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[18] SDIO_Slave_Controller_Top|cpu_clk DFFCE D slv_cpu_rd_data_35[18] 2.788 -0.374 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[22] SDIO_Slave_Controller_Top|cpu_clk DFFCE D N_42_0_i 2.788 -0.374 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[23] SDIO_Slave_Controller_Top|cpu_clk DFFCE D N_33_0_i 2.788 -0.374 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[20] SDIO_Slave_Controller_Top|cpu_clk DFFCE D slv_cpu_rd_data_35[20] 2.788 -0.287 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[14] SDIO_Slave_Controller_Top|cpu_clk DFFCE D slv_cpu_rd_data_35[14] 2.788 -0.283 ============================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.849 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.788 - Propagation time: 3.290 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.503 Number of logic level(s): 3 Starting point: u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_ext_fn_if_code[0] / Q Ending point: u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[8] / D The start point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_ext_fn_if_code[0] DFFCE Q Out 0.243 0.243 - fbr1_ext_fn_if_code[0] Net - - 0.535 - 3 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_a2_1[8] LUT4 I1 In - 0.778 - u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_a2_1[8] LUT4 F Out 0.570 1.348 - N_378 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_1[8] LUT4 I1 In - 1.749 - u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_1[8] LUT4 F Out 0.570 2.319 - slv_cpu_rd_data_35_0_1[8] Net - - 0.401 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0[8] LUT4 I1 In - 2.720 - u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0[8] LUT4 F Out 0.570 3.290 - slv_cpu_rd_data_35[8] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[8] DFFCE D In - 3.290 - =========================================================================================================================== Total path delay (propagation time + setup) of 3.351 is 2.014(60.1%) logic and 1.337(39.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 2.849 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.788 - Propagation time: 3.290 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.503 Number of logic level(s): 3 Starting point: u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_sda_mid_manf_code[3] / Q Ending point: u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[19] / D The start point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_sda_mid_manf_code[3] DFFCE Q Out 0.243 0.243 - fbr1_sda_mid_manf_code[3] Net - - 0.535 - 4 u_sdio_slave_ctrl.u_cmd_dec.m107 LUT3 I1 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.m107 LUT3 F Out 0.570 1.348 - i54_mux Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb_1 LUT4 I1 In - 1.749 - u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb_1 LUT4 F Out 0.570 2.319 - N_917_i_mb_1 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb LUT4 I1 In - 2.720 - u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb LUT4 F Out 0.570 3.290 - N_917_i Net - - 0.000 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[19] DFFCE D In - 3.290 - ======================================================================================================================== Total path delay (propagation time + setup) of 3.351 is 2.014(60.1%) logic and 1.337(39.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 2.849 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.788 - Propagation time: 3.269 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.482 Number of logic level(s): 3 Starting point: u_sdio_slave_ctrl.u_slv_cpu_if.cccr_cis_pointer[19] / Q Ending point: u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[19] / D The start point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_slv_cpu_if.cccr_cis_pointer[19] DFFCE Q Out 0.243 0.243 - cccr_cis_pointer[19] Net - - 0.535 - 4 u_sdio_slave_ctrl.u_cmd_dec.m107 LUT3 I0 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.m107 LUT3 F Out 0.549 1.327 - i54_mux Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb_1 LUT4 I1 In - 1.728 - u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb_1 LUT4 F Out 0.570 2.298 - N_917_i_mb_1 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb LUT4 I1 In - 2.699 - u_sdio_slave_ctrl.u_cmd_dec.N_917_i_mb LUT4 F Out 0.570 3.269 - N_917_i Net - - 0.000 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[19] DFFCE D In - 3.269 - =================================================================================================================== Total path delay (propagation time + setup) of 3.330 is 1.993(59.8%) logic and 1.337(40.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 2.849 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.788 - Propagation time: 3.269 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.482 Number of logic level(s): 3 Starting point: u_sdio_slave_ctrl.u_slv_cpu_if.cccr_max_blk_size[8] / Q Ending point: u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[8] / D The start point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_slv_cpu_if.cccr_max_blk_size[8] DFFCE Q Out 0.243 0.243 - cccr_max_blk_size[8] Net - - 0.535 - 3 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_a2_1[8] LUT4 I0 In - 0.778 - u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_a2_1[8] LUT4 F Out 0.549 1.327 - N_378 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_1[8] LUT4 I1 In - 1.728 - u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0_1[8] LUT4 F Out 0.570 2.298 - slv_cpu_rd_data_35_0_1[8] Net - - 0.401 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0[8] LUT4 I1 In - 2.699 - u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data_35_0[8] LUT4 F Out 0.570 3.269 - slv_cpu_rd_data_35[8] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[8] DFFCE D In - 3.269 - =========================================================================================================================== Total path delay (propagation time + setup) of 3.330 is 1.993(59.8%) logic and 1.337(40.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 2.849 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.788 - Propagation time: 3.269 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.482 Number of logic level(s): 3 Starting point: u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_sda_mid_manf_code[9] / Q Ending point: u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[25] / D The start point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_sda_mid_manf_code[9] DFFCE Q Out 0.243 0.243 - fbr1_sda_mid_manf_code[9] Net - - 0.535 - 4 u_sdio_slave_ctrl.u_cmd_dec.m98 LUT3 I1 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.m98 LUT3 F Out 0.570 1.348 - i60_mux Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.N_23_0_i_1 LUT4 I0 In - 1.749 - u_sdio_slave_ctrl.u_cmd_dec.N_23_0_i_1 LUT4 F Out 0.549 2.298 - N_23_0_i_1 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_cmd_dec.N_23_0_i LUT3 I1 In - 2.699 - u_sdio_slave_ctrl.u_cmd_dec.N_23_0_i LUT3 F Out 0.570 3.269 - N_23_0_i Net - - 0.000 - 1 u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_rd_data[25] DFFCE D In - 3.269 - ======================================================================================================================== Total path delay (propagation time + setup) of 3.330 is 1.993(59.8%) logic and 1.337(40.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SDIO_Slave_Controller_Top|sdio_clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_latch SDIO_Slave_Controller_Top|sdio_clk DFFC Q fn0_abort_latch 0.243 -1.001 u_sdio_slave_ctrl.u_cmd_dec.cmd_crc_ok_fast SDIO_Slave_Controller_Top|sdio_clk DFFC Q cmd_crc_ok_fast 0.243 -0.980 u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_latch SDIO_Slave_Controller_Top|sdio_clk DFFC Q fn1_abort_latch 0.243 -0.980 u_sdio_slave_ctrl.u_fn0_reg.cmd53_ctrl_fn0_addr_d1[0] SDIO_Slave_Controller_Top|sdio_clk DFFCE Q cmd53_ctrl_fn0_addr_d1[0] 0.243 -0.963 u_sdio_slave_ctrl.u_cmd_dec.cmd_crc_ok_rep1 SDIO_Slave_Controller_Top|sdio_clk DFFC Q cmd_crc_ok_rep1 0.243 -0.959 u_sdio_slave_ctrl.u_fn0_reg.cmd53_ctrl_fn0_addr_d1[2] SDIO_Slave_Controller_Top|sdio_clk DFFCE Q cmd53_ctrl_fn0_addr_d1[2] 0.243 -0.914 u_sdio_slave_ctrl.u_fn0_reg.cmd53_ctrl_fn0_addr_d1[1] SDIO_Slave_Controller_Top|sdio_clk DFFCE Q cmd53_ctrl_fn0_addr_d1[1] 0.243 -0.893 u_sdio_slave_ctrl.u_cmd53_ctrl.io53_fn0_reg_rd_d1_fast SDIO_Slave_Controller_Top|sdio_clk DFFCE Q io53_fn0_reg_rd_d1_fast 0.243 -0.802 u_sdio_slave_ctrl.u_cmd53_ctrl.io53_cis_rd_d1_fast SDIO_Slave_Controller_Top|sdio_clk DFFCE Q io53_cis_rd_d1_fast 0.243 -0.781 u_sdio_slave_ctrl.u_fn0_reg.cmd53_ctrl_fn0_addr_d1[3] SDIO_Slave_Controller_Top|sdio_clk DFFCE Q cmd53_ctrl_fn0_addr_d1[3] 0.243 -0.731 ==================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] SDIO_Slave_Controller_Top|sdio_clk DFFC D N_81_i 5.609 -1.001 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata[0] SDIO_Slave_Controller_Top|sdio_clk DFFCE D cmd53_fn0_reg_rddata_52[0] 5.609 -0.963 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[4] SDIO_Slave_Controller_Top|sdio_clk DFFC D N_83_i 5.609 -0.785 u_sdio_slave_ctrl.u_cmd53_ctrl.cmd53_ctrl_fn0_reg_rd_en SDIO_Slave_Controller_Top|sdio_clk DFFC D cmd53_ctrl_fn0_reg_rd_en_3 5.609 -0.738 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata[5] SDIO_Slave_Controller_Top|sdio_clk DFFCE D cmd53_fn0_reg_rddata_52[5] 5.609 -0.731 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata[6] SDIO_Slave_Controller_Top|sdio_clk DFFCE D cmd53_fn0_reg_rddata_52[6] 5.609 -0.731 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata[7] SDIO_Slave_Controller_Top|sdio_clk DFFCE D cmd53_fn0_reg_rddata_52[7] 5.609 -0.710 u_sdio_slave_ctrl.u_cmd53_ctrl.cmd53_ctrl_cis_fnx_rd_en SDIO_Slave_Controller_Top|sdio_clk DFFC D cmd53_ctrl_cis_fnx_rd_en_3 5.609 -0.668 u_sdio_slave_ctrl.u_fn0_reg.cmd52_fn0_reg_rd_data[5] SDIO_Slave_Controller_Top|sdio_clk DFFC D cmd52_fn0_reg_rd_data_52[5] 5.609 -0.595 u_sdio_slave_ctrl.u_fn0_reg.cmd52_fn0_reg_rd_data[6] SDIO_Slave_Controller_Top|sdio_clk DFFC D cmd52_fn0_reg_rd_data_52[6] 5.609 -0.595 ======================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.670 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.609 - Propagation time: 6.610 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.001 Number of logic level(s): 6 Starting point: u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_latch / Q Ending point: u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] / D The start point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_latch DFFC Q Out 0.243 0.243 - fn0_abort_latch Net - - 0.535 - 6 u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_0_i LUT2 I1 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_0_i LUT2 F Out 0.570 1.348 - N_386 Net - - 0.535 - 3 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 I1 In - 1.883 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 F Out 0.570 2.453 - n_state43_0 Net - - 0.535 - 8 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 I0 In - 2.988 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 F Out 0.549 3.537 - n_state43 Net - - 0.535 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 I2 In - 4.072 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 F Out 0.462 4.534 - io_current_state35_3_0 Net - - 0.535 - 2 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 I1 In - 5.069 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 F Out 0.570 5.639 - N_110 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 I1 In - 6.040 - u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 F Out 0.570 6.610 - N_81_i Net - - 0.000 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] DFFC D In - 6.610 - =========================================================================================================================== Total path delay (propagation time + setup) of 6.671 is 3.595(53.9%) logic and 3.076(46.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.670 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.609 - Propagation time: 6.589 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.980 Number of logic level(s): 6 Starting point: u_sdio_slave_ctrl.u_cmd_dec.cmd_crc_ok_fast / Q Ending point: u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] / D The start point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.cmd_crc_ok_fast DFFC Q Out 0.243 0.243 - cmd_crc_ok_fast Net - - 0.535 - 4 u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_0_i LUT2 I0 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_0_i LUT2 F Out 0.549 1.327 - N_386 Net - - 0.535 - 3 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 I1 In - 1.862 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 F Out 0.570 2.432 - n_state43_0 Net - - 0.535 - 8 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 I0 In - 2.967 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 F Out 0.549 3.516 - n_state43 Net - - 0.535 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 I2 In - 4.051 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 F Out 0.462 4.513 - io_current_state35_3_0 Net - - 0.535 - 2 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 I1 In - 5.048 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 F Out 0.570 5.618 - N_110 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 I1 In - 6.019 - u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 F Out 0.570 6.589 - N_81_i Net - - 0.000 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] DFFC D In - 6.589 - =========================================================================================================================== Total path delay (propagation time + setup) of 6.650 is 3.574(53.7%) logic and 3.076(46.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.670 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.609 - Propagation time: 6.589 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.980 Number of logic level(s): 6 Starting point: u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_latch / Q Ending point: u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] / D The start point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_latch DFFC Q Out 0.243 0.243 - fn1_abort_latch Net - - 0.535 - 6 u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_0_i LUT2 I1 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_0_i LUT2 F Out 0.570 1.348 - N_11 Net - - 0.535 - 2 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 I0 In - 1.883 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 F Out 0.549 2.432 - n_state43_0 Net - - 0.535 - 8 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 I0 In - 2.967 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 F Out 0.549 3.516 - n_state43 Net - - 0.535 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 I2 In - 4.051 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 F Out 0.462 4.513 - io_current_state35_3_0 Net - - 0.535 - 2 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 I1 In - 5.048 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 F Out 0.570 5.618 - N_110 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 I1 In - 6.019 - u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 F Out 0.570 6.589 - N_81_i Net - - 0.000 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] DFFC D In - 6.589 - =========================================================================================================================== Total path delay (propagation time + setup) of 6.650 is 3.574(53.7%) logic and 3.076(46.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.670 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.609 - Propagation time: 6.572 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.963 Number of logic level(s): 6 Starting point: u_sdio_slave_ctrl.u_fn0_reg.cmd53_ctrl_fn0_addr_d1[0] / Q Ending point: u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata[0] / D The start point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_fn0_reg.cmd53_ctrl_fn0_addr_d1[0] DFFCE Q Out 0.243 0.243 - cmd53_ctrl_fn0_addr_d1[0] Net - - 1.074 - 118 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_3[0] LUT3 I2 In - 1.317 - u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_3[0] LUT3 F Out 0.462 1.779 - N_1906 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_34[0] LUT4 I0 In - 2.180 - u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_34[0] LUT4 F Out 0.549 2.729 - N_2144 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_41[0] LUT4 I0 In - 3.130 - u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_41[0] LUT4 F Out 0.549 3.679 - N_2203 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_45[0] LUT3 I0 In - 4.081 - u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_45[0] LUT3 F Out 0.549 4.630 - N_2236 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_rn[0] LUT3 I1 In - 5.031 - u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_rn[0] LUT3 F Out 0.570 5.601 - cmd53_fn0_reg_rddata_52_rn_1[0] Net - - 0.401 - 1 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_mb[0] LUT3 I1 In - 6.002 - u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata_52_mb[0] LUT3 F Out 0.570 6.572 - cmd53_fn0_reg_rddata_52[0] Net - - 0.000 - 1 u_sdio_slave_ctrl.u_fn0_reg.cmd53_fn0_reg_rddata[0] DFFCE D In - 6.572 - ========================================================================================================================= Total path delay (propagation time + setup) of 6.633 is 3.553(53.6%) logic and 3.080(46.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.670 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.609 - Propagation time: 6.568 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.959 Number of logic level(s): 6 Starting point: u_sdio_slave_ctrl.u_cmd_dec.cmd_crc_ok_rep1 / Q Ending point: u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] / D The start point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK The end point is clocked by SDIO_Slave_Controller_Top|sdio_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_cmd_dec.cmd_crc_ok_rep1 DFFC Q Out 0.243 0.243 - cmd_crc_ok_rep1 Net - - 0.535 - 5 u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_0_i LUT2 I0 In - 0.778 - u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_0_i LUT2 F Out 0.549 1.327 - N_11 Net - - 0.535 - 2 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 I0 In - 1.862 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43_0 LUT4 F Out 0.549 2.411 - n_state43_0 Net - - 0.535 - 8 u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 I0 In - 2.946 - u_sdio_slave_ctrl.u_cmd53_ctrl.n_state43 LUT2 F Out 0.549 3.495 - n_state43 Net - - 0.535 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 I2 In - 4.030 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state35_3_0 LUT4 F Out 0.462 4.492 - io_current_state35_3_0 Net - - 0.535 - 2 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 I1 In - 5.027 - u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1_ns_i_a3_1[3] LUT3 F Out 0.570 5.597 - N_110 Net - - 0.401 - 1 u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 I1 In - 5.998 - u_sdio_slave_ctrl.u_sdio_biu.N_81_i LUT4 F Out 0.570 6.568 - N_81_i Net - - 0.000 - 1 u_sdio_slave_ctrl.u_sdio_biu.io_current_state_1[3] DFFC D In - 6.568 - =========================================================================================================================== Total path delay (propagation time + setup) of 6.629 is 3.553(53.6%) logic and 3.076(46.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_card_fixed_regs.rstn_i System INV O rstn_i 0.000 2.131 u_sdio_slave_ctrl.u_fn0_reg.cmd52_rst_gen_fast_fast_RNI9R86 System INV O cmd52_rst_i 0.000 3.545 u_sdio_slave_ctrl.u_cmd_dec.any_cmd_RNO System INV O N_1220_i 0.000 5.074 u_sdio_slave_ctrl.u_cmd53_tx_rx.o_dat1_9_m1_xx_RNIEER4 System INV O N_1175_i 0.000 5.074 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_std_fn_if_code[0] System DFFP PRESET rstn_i 2.788 2.131 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_std_fn_if_code[1] System DFFP PRESET rstn_i 2.788 2.131 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_std_fn_if_code[2] System DFFP PRESET rstn_i 2.788 2.131 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_std_fn_if_code[3] System DFFP PRESET rstn_i 2.788 2.131 u_sdio_slave_ctrl.u_card_fixed_regs.rca[15] System DFFCE D rca_s[15] 5.609 3.545 u_sdio_slave_ctrl.u_card_fixed_regs.rca[14] System DFFCE D rca_s[14] 5.609 3.579 u_sdio_slave_ctrl.u_card_fixed_regs.rca[13] System DFFCE D rca_s[13] 5.609 3.615 u_sdio_slave_ctrl.u_card_fixed_regs.rca[12] System DFFCE D rca_s[12] 5.609 3.650 u_sdio_slave_ctrl.u_card_fixed_regs.rca[11] System DFFCE D rca_s[11] 5.609 3.684 u_sdio_slave_ctrl.u_card_fixed_regs.rca[10] System DFFCE D rca_s[10] 5.609 3.720 ============================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.849 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.788 - Propagation time: 0.657 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.131 Number of logic level(s): 0 Starting point: u_sdio_slave_ctrl.u_card_fixed_regs.rstn_i / O Ending point: u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_std_fn_if_code[0] / PRESET The start point is clocked by System [rising] The end point is clocked by SDIO_Slave_Controller_Top|cpu_clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- u_sdio_slave_ctrl.u_card_fixed_regs.rstn_i INV O Out 0.000 0.000 - rstn_i Net - - 0.657 - 1572 u_sdio_slave_ctrl.u_slv_cpu_if.fbr1_std_fn_if_code[0] DFFP PRESET In - 0.657 - ====================================================================================================================== Total path delay (propagation time + setup) of 0.718 is 0.061(8.5%) logic and 0.657(91.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 292MB peak: 334MB) Finished timing report (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 292MB peak: 334MB) --------------------------------------- Resource Usage Report for SDIO_Slave_Controller_Top Mapping to part: gw2a_18pbga256-8 Cell usage: ALU 275 uses DFFC 345 uses DFFCE 1153 uses DFFNC 15 uses DFFNCE 1 use DFFNP 7 uses DFFP 25 uses DFFPE 45 uses GSR 1 use INV 4 uses MUX2_LUT5 203 uses MUX2_LUT6 58 uses MUX2_LUT7 16 uses LUT2 571 uses LUT3 1079 uses LUT4 1655 uses I/O Register bits: 0 Register bits not including I/Os: 1591 of 15552 (10%) Total load per clock: SDIO_Slave_Controller_Top|sdio_clk: 1384 SDIO_Slave_Controller_Top|cpu_clk: 189 SDIO_Slave_Controller_Top|clk_2mhz: 19 @S |Mapping Summary: Total LUTs: 3305 (15%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 95MB peak: 334MB) Process took 0h:00m:34s realtime, 0h:00m:32s cputime # Mon Nov 11 16:08:52 2019 ###########################################################]