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	  Example SDIO Slave Controller Design Read Me
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Object device:GW2A-18PG256
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File List:
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.
|-- docs
|   `-- Readme.txt                      	-->  Read Me file (this file)
|-- tb 
|   `-- cmd_model.v                                    -->  File of sending commands
|   `-- tb.v                                    -->  TestBench for Example SDIO Slave Controller design
|   `-- test_cmd19_tuning.v                                    -->  File of testing cmd19
|   `-- test_cmd52_wr_rd_cis_fnx_task.v                                    -->  File of testing cmd52
|   `-- test_cmd53_blk_rd_cis_fnx_task.v                                    -->  File of testing reading blocks using cmd53
|   `-- test_cmd53_blk_wr_cis_fnx_task.v                                    -->  File of testing writing blocks using cmd53
|   `-- test_cmd53_byte_rd_cis_fnx_task.v                                    -->  File of testing reading bytes using cmd53
|   `-- test_cmd53_byte_wr_cis_fnx_task.v                                    -->  File of testing writing bytes using cmd53
|   `-- test_sd1bit_irq_task.v                                    -->  File of testing interrupt of 1 bit
|   `-- test_sd4bit_irq_task.v                                    -->  File of testing interrupt of 4 bit
|   `-- user_sdio_cmd52_if.v                                    -->  File of testing user's interface of cmd52
|   `-- user_sdio_cmd53_if.v                                    -->  File of testing user's interface of cmd53
|   `-- user_tuning_pattern.v                                    -->  File of testing user's interface of sending tuning pattern
|-- project
|   `-- sdio_test.gprj          		-->  GowinYunYuan Project File for Example Design
|   `-- sdio_test.gprj.user           	-->  GowinYunYuan Project File for Example Design
|   |-- impl
|   |-- src                          -->  File for GowinYunYuan Project in it
|   `-- temp
|-- simulation
|   `-- Modelsim
|   |   |-- cmd.do					-->  Command script
|   `-- VCS_SIM
|   |   |-- Makefile					-->  Command script
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HOW TO OPEN A PROJECT IN GowinYunYuan:
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1. Unzip the respective design files.
2. Launch GowinYunYuan and select "File -> Open -> Project"
3. In the Open Project dialog, enter the Project location -- "project",select the project"sdio_test.gprj".
4. Click Finish. Now the project is successfully loaded. 

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HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATION, AND TIMING ANALYSIS IN GowinYunYuan:
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1. Click the Process tab in the process panel of the GowinYunYuan dashboard. 
   Double click on Synthsize(Synplify Pro). This will bring the design through synthesis.
2. Click the Process tab in the process panel of the GowinYunYuan dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.
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HOW TO RUN SIMULATION
1. User can run functional simulation by software VCS or modelsim. 
2. User can check waveform by software Verdi.
3. During the simulation, the user needs to add prim_sim.v in the "Gowin Yunyuan" to the directory of "tb".
   File path:installation path\IDE\simlib\gw1n\prim_sim.v;or installation path\IDE\simlib\gw2a\prim_sim.v.
4. Script usage description：
         Makefile script of VCS:Makefile script should be ran under the directory of "VCS_SIM"
			(1)make vcs:simulation
			(2)make vd:view waveform
			(3)make clean:clear the files generated by the simulation
         cmd.do script of modelsim:cmd.do script should be ran under the directory of "Modelsim"
			do cmd.do:simulation and view waveform
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HOW TO  GENERATE IP CORE
1. Click the IP Core Generator tab in the Window panel of the GowinYunYuan dashboard.
   Double click on "SDIO Slave Controller". This will generate the IP Core for the design.
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