tbFile:=		../../tb/tb.v
cmdFile:=       ../../tb/cmd_model.v
user52ifFile:=  ../../tb/user_sdio_cmd52_if.v
user53ifFile:=  ../../tb/user_sdio_cmd53_if.v
tuningFile:=    ../../tb/user_tuning_pattern.v
voFile:=		../../project/src/sdio_slave_controller/sdio_slave_controller.vo
tbpath:=        ../../tb
vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog	\
	-v  ../../tb/prim_sim.v						\
	$(tbFile)                                   \
	$(cmdFile)									\
	$(user52ifFile)								\
	$(user53ifFile)								\
	$(tuningFile)								\
	$(voFile)									\
	+define+VCS_SIM   							\
	+incdir+$(tbpath)

vd:
	verdi -sverilog								\
	-v ../../tb/prim_sim.v				 		\
	$(tbFile)                                   \
	$(cmdFile)									\
	$(user52ifFile)								\
	$(user53ifFile)								\
	$(tuningFile)								\
	$(voFile)									\
	+define+VCS_SIM   							\
	+incdir+$(tbpath)                           \
	-ssf sdio.fsdb								\
	&

clean:
	rm -rf compile  *.err *.log csrc  run.do  simv  simv.daidir  ucli.key  vc_hdrs.h  work novas.rc  nWaveLog   vcd2fsdbLog  verilog.vcd  verilog.vcd.fsdb vsim.wlf simv.vdb INCA_libs waves.shm .simvision *.rc cov_work dataset.asdb  fcover.acdb  library.cfg elab_file *.ucdb verdiLog inter.vpd novas.conf wave.ses.png sdio.fsdb data

