@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MT206 |Auto Constrain mode is enabled
@N: MO231 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\top.v":325:0:325:5|Found counter in view:work.top(verilog) instance led_reg[24:0] 
@N: MO231 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\user_sdio_cmd53_if.v":160:0:160:5|Found counter in view:work.user_sdio_cmd53_if_xmr0(verilog) instance cnt[11:0] 
@N: MO231 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\user_sdio_cmd53_if.v":145:0:145:5|Found counter in view:work.user_sdio_cmd53_if_xmr0(verilog) instance buf_full_cnt[7:0] 
@N: MF179 :|Found 13 by 13 bit equality operator ('==') un1_cnt_2 (in view: work.user_sdio_cmd53_if_xmr0(verilog))
@N: MO231 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\user_tuning_pattern.v":32:0:32:5|Found counter in view:work.user_tuning_pattern(verilog) instance cnt[7:0] 
@N: MO231 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\button.v":24:0:24:5|Found counter in view:work.deUstb_1(verilog) instance cnt[19:0] 
@N: MO231 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\button.v":24:0:24:5|Found counter in view:work.deUstb_0(verilog) instance cnt[19:0] 
@N: MO231 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\user_cpu_slave_reg_if.v":85:0:85:5|Found counter in view:work.user_cpu_slave_reg_if(verilog) instance cnt[9:0] 
@N: MO106 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\user_tuning_pattern.v":48:42:48:67|Found ROM u_user_tuning_pattern.un11_sdio_tuning_data[3:0] (in view: work.top(verilog)) with 144 words by 4 bits.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
