Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\impl\synthesize\rev_1\sdio_test.vm
Physical Constraints File	C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\sdio_test.cst
Timing Constraint File	C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\sdio_test.sdc
GOWIN version	V1.9.2.02Beta
Part Number	GW2A-LV18PG256C8/I7
Created Time	Tue Nov 12 10:10:24 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	5750
Numbers of Endpoints Analyzed	7082
Numbers of Falling Endpoints	25
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
sdio_clkin	Base	10.000	100.000	0.000	5.000			clk

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	sdio_clkin	119.077(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
sdio_clkin	Setup	0.000	0
sdio_clkin	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.602	user_sdio_cmd53_rd_ready_Z/Q	u_la0_top/genblk1.u_ao_match_0/match_sep/D	sdio_clkin:[R]	sdio_clkin:[R]	10.000	0.000	8.163
2	1.652	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	3.145
3	1.658	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	3.139
4	1.658	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	3.139
5	1.680	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en/CE	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	3.118
6	2.148	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	2.650
7	2.429	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d3_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	2.369
8	2.429	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	2.369
9	2.453	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[4]/D	sdio_clkin:[R]	sdio_clkin:[R]	10.000	0.000	7.312
10	2.537	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	2.261
11	2.537	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	2.261
12	2.566	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[3]/D	sdio_clkin:[R]	sdio_clkin:[R]	10.000	0.000	7.199
13	2.637	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[4]/D	sdio_clkin:[R]	sdio_clkin:[R]	10.000	0.000	7.128
14	2.820	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_bit_oen/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.978
15	2.904	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_tx_rx/o_dat3/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.894
16	2.979	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cccr_blk_size_1[4]/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[2]/D	sdio_clkin:[R]	sdio_clkin:[R]	10.000	0.000	6.786
17	2.991	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.807
18	2.991	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.807
19	2.991	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.807
20	2.999	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.799
21	2.999	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.799
22	2.999	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.799
23	2.999	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.799
24	3.002	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[6]/D	sdio_clkin:[R]	sdio_clkin:[R]	10.000	0.000	6.763
25	3.012	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_Z/D	sdio_clkin:[R]	sdio_clkin:[F]	5.000	-0.033	1.786

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.074	u_la0_top/u_ao_mem_ctrl/data_reg_Z[124]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI16	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.323
2	0.074	u_la0_top/u_ao_mem_ctrl/data_reg_Z[123]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI15	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.323
3	0.074	u_la0_top/u_ao_mem_ctrl/data_reg_Z[112]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI4	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.323
4	0.076	u_la0_top/u_ao_mem_ctrl/data_reg_Z[122]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI14	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.325
5	0.076	u_la0_top/u_ao_mem_ctrl/data_reg_Z[121]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI13	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.325
6	0.076	u_la0_top/u_ao_mem_ctrl/data_reg_Z[120]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI12	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.325
7	0.076	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI11	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.325
8	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_7/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
9	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
10	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
11	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
12	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
13	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
14	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
15	0.194	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/WREA	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.335
16	0.202	u_la0_top/u_ao_mem_ctrl/data_reg_Z[117]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI9	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.451
17	0.202	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI8	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.451
18	0.202	u_la0_top/u_ao_mem_ctrl/data_reg_Z[115]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI7	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.451
19	0.202	u_la0_top/u_ao_mem_ctrl/data_reg_Z[114]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI6	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.451
20	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[125]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI17	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.462
21	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI10	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.462
22	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[113]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI5	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.462
23	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[110]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI2	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.462
24	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[111]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI3	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.462
25	0.225	u_la0_top/u_ao_mem_ctrl/data_reg_Z[107]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5/DI17	sdio_clkin:[R]	sdio_clkin:[R]	0.000	0.000	0.474

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.599	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.133
2	3.599	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.133
3	3.664	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.068
4	3.664	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.068
5	3.664	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[2]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.068
6	3.664	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[3]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.068
7	3.667	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.065
8	3.667	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.065
9	3.667	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[2]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.065
10	3.667	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel[3]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.065
11	3.672	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.060
12	3.681	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.051
13	3.681	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.051
14	3.681	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.051
15	3.681	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.051
16	3.684	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.048
17	3.684	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.048
18	3.684	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[6]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.048
19	3.684	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	1.048
20	3.909	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	0.823
21	3.909	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[9]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	0.823
22	3.909	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	0.823
23	3.909	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	0.823
24	3.909	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	0.823
25	3.909	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	5.000	0.033	0.823

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.397	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.595
2	5.397	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.595
3	5.397	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.595
4	5.397	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[2]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.595
5	5.402	u_la0_top/rst_ao_Z/Q	u_la0_top/trigger_seq_start_Z/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.600
6	5.402	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.600
7	5.402	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_dly_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.600
8	5.402	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.600
9	5.402	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_end_dly_Z/PRESET	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.600
10	5.403	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.601
11	5.403	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.601
12	5.403	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.601
13	5.403	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.601
14	5.404	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_syn_Z[1]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.602
15	5.407	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.605
16	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
17	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
18	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
19	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
20	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[3]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
21	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[5]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
22	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
23	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[7]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
24	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[4]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607
25	5.409	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[8]/CLEAR	sdio_clkin:[F]	sdio_clkin:[R]	-5.000	0.013	0.607

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	user_sdio_cmd52_if_user_sdio_cmd52_ack_Z
2	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	user_sdio_cmd53_wr_abort_Z
3	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	user_sdio_cmd53_rd_en_Z
4	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	user_sdio_cmd52_if_user_sdio_cmd52_cs_Z
5	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	user_sdio_cmd52_if_user_sdio_cmd52_addr_Z[4]
6	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	user_sdio_cmd53_addr_Z[7]
7	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/cmd5_check_ocr_val_Z[13]
8	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/io53_addr_Z[3]
9	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_byte_tmp_Z[1]
10	3.662	4.662	1.000	Low Pulse Width	sdio_clkin	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.602
Data Arrival Time	10.046
Data Required Time	11.648
From	user_sdio_cmd53_rd_ready_Z
To	u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C36[0][B]	user_sdio_cmd53_rd_ready_Z/CLK
2.115	0.232	tC2Q	RF	6	R42C36[0][B]	user_sdio_cmd53_rd_ready_Z/Q
5.175	3.060	tNET	FF	1	R5C5[2][A]	u_la0_top/genblk1.u_ao_match_0/m8_d_1_cZ/I2
5.730	0.555	tINS	FF	1	R5C5[2][A]	u_la0_top/genblk1.u_ao_match_0/m8_d_1_cZ/F
6.248	0.518	tNET	FF	1	R5C5[2][B]	u_la0_top/genblk1.u_ao_match_0/m8_d_cZ/I2
6.818	0.570	tINS	FR	1	R5C5[2][B]	u_la0_top/genblk1.u_ao_match_0/m8_d_cZ/F
6.991	0.172	tNET	RR	1	R5C4[2][B]	u_la0_top/genblk1.u_ao_match_0/m8/I0
7.508	0.517	tINS	RF	2	R5C4[2][B]	u_la0_top/genblk1.u_ao_match_0/m8/F
7.759	0.252	tNET	FF	1	R5C2[3][A]	u_la0_top/genblk1.u_ao_match_0/match_sep_9_1_cZ/I2
8.308	0.549	tINS	FR	1	R5C2[3][A]	u_la0_top/genblk1.u_ao_match_0/match_sep_9_1_cZ/F
8.452	0.144	tNET	RR	1	R5C2[3][B]	u_la0_top/genblk1.u_ao_match_0/match_sep_9_cZ/I2
9.007	0.555	tINS	RF	1	R5C2[3][B]	u_la0_top/genblk1.u_ao_match_0/match_sep_9_cZ/F
9.497	0.490	tNET	FF	1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep_10_u/I3
10.046	0.549	tINS	FR	1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep_10_u/F
10.046	0.000	tNET	RR	1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/match_sep
11.648	-0.035	tSu		1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.295, 40.365%; route: 4.636, 56.792%; tC2Q: 0.232, 2.842%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.652
Data Arrival Time	5.029
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R24C12[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1/CLK
2.115	0.232	tC2Q	RF	12	R24C12[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1/Q
3.598	1.483	tNET	FF	1	R32C21[3][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en_5_m0_cZ/I2
4.153	0.555	tINS	FF	1	R32C21[3][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en_5_m0_cZ/F
4.567	0.413	tNET	FF	1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en_5_cZ/I3
5.029	0.462	tINS	FR	1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en_5_cZ/F
5.029	0.000	tNET	RR	1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en
6.681	-0.035	tSu		1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 1.017, 32.333%; route: 1.896, 60.292%; tC2Q: 0.232, 7.376%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path3

Path Summary:

Slack	1.658
Data Arrival Time	5.023
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
4.453	2.337	tNET	FF	1	R18C43[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq_RNO/I0
5.023	0.570	tINS	FR	1	R18C43[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq_RNO/F
5.023	0.000	tNET	RR	1	R18C43[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R18C43[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq
6.681	-0.035	tSu		1	R18C43[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_sync_irq

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 18.156%; route: 2.337, 74.454%; tC2Q: 0.232, 7.390%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path4

Path Summary:

Slack	1.658
Data Arrival Time	5.023
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
4.453	2.337	tNET	FF	1	R18C43[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel_RNO/I0
5.023	0.570	tINS	FR	1	R18C43[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel_RNO/F
5.023	0.000	tNET	RR	1	R18C43[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R18C43[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel
6.681	-0.035	tSu		1	R18C43[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_irq_gen/negedge_sdio_irq_sel

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 18.156%; route: 2.337, 74.454%; tC2Q: 0.232, 7.390%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path5

Path Summary:

Slack	1.680
Data Arrival Time	5.001
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R24C12[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1/CLK
2.115	0.232	tC2Q	RF	12	R24C12[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/bit_resp_flag_d1/Q
3.598	1.483	tNET	FF	1	R32C22[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/g0_1_RNO/I1
4.168	0.570	tINS	FR	1	R32C22[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/g0_1_RNO/F
4.170	0.001	tNET	RR	1	R32C22[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/g0_1/I3
4.719	0.549	tINS	RR	1	R32C22[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/g0_1/F
5.001	0.282	tNET	RR	1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en
6.681	-0.035	tSu		1	R32C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 1.119, 35.890%; route: 1.767, 56.668%; tC2Q: 0.232, 7.441%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path6

Path Summary:

Slack	2.148
Data Arrival Time	4.533
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
4.162	2.047	tNET	FF	1	R35C21[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_3_cZ/I0
4.533	0.371	tINS	FF	1	R35C21[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_3_cZ/F
4.533	0.000	tNET	FF	1	R35C21[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R35C21[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_Z
6.681	-0.035	tSu		1	R35C21[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d1_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.371, 14.001%; route: 2.047, 77.243%; tC2Q: 0.232, 8.756%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path7

Path Summary:

Slack	2.429
Data Arrival Time	4.252
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d3_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.682	1.567	tNET	FF	1	R32C20[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en_0_sqmuxa_cZ/I0
4.252	0.570	tINS	FR	1	R32C20[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/pos_edge_clk_send_en_0_sqmuxa_cZ/F
4.252	0.000	tNET	RR	1	R32C20[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d3_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R32C20[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d3_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d3_Z
6.681	-0.035	tSu		1	R32C20[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d3_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 24.061%; route: 1.567, 66.146%; tC2Q: 0.232, 9.793%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path8

Path Summary:

Slack	2.429
Data Arrival Time	4.252
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.682	1.567	tNET	FF	1	R32C20[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_3_cZ/I0
4.252	0.570	tINS	FR	1	R32C20[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_3_cZ/F
4.252	0.000	tNET	RR	1	R32C20[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R32C20[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z
6.681	-0.035	tSu		1	R32C20[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 24.061%; route: 1.567, 66.146%; tC2Q: 0.232, 9.793%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path9

Path Summary:

Slack	2.453
Data Arrival Time	9.195
Data Required Time	11.648
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[4]
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R29C32[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch/CLK
2.115	0.232	tC2Q	RF	6	R29C32[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch/Q
3.124	1.009	tNET	FF	1	R23C36[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_0_i/I1
3.641	0.517	tINS	FF	3	R23C36[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_0_i/F
4.758	1.117	tNET	FF	1	R21C36[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43_0_cZ/I1
5.129	0.371	tINS	FF	8	R21C36[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43_0_cZ/F
5.807	0.678	tNET	FF	1	R22C39[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43/I0
6.377	0.570	tINS	FR	1	R22C39[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43/F
6.550	0.172	tNET	RR	1	R22C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state35_3_0_cZ/I2
7.105	0.555	tINS	RF	2	R22C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state35_3_0_cZ/F
7.765	0.660	tNET	FF	1	R25C37[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_ns_i_a3_0[4]/I2
8.320	0.555	tINS	FF	1	R25C37[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_ns_i_a3_0[4]/F
8.733	0.413	tNET	FF	1	R24C35[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_83_i_cZ/I2
9.195	0.462	tINS	FR	1	R24C35[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_83_i_cZ/F
9.195	0.000	tNET	RR	1	R24C35[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R24C35[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[4]/CLK
11.683	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[4]
11.648	-0.035	tSu		1	R24C35[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[4]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.030, 41.439%; route: 4.050, 55.388%; tC2Q: 0.232, 3.173%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	2.537
Data Arrival Time	4.144
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.682	1.567	tNET	FF	1	R33C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_3_cZ/I0
4.144	0.462	tINS	FR	1	R33C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_3_cZ/F
4.144	0.000	tNET	RR	1	R33C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R33C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_Z
6.681	-0.035	tSu		1	R33C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d2_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.462, 20.433%; route: 1.567, 69.306%; tC2Q: 0.232, 10.261%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path11

Path Summary:

Slack	2.537
Data Arrival Time	4.144
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.682	1.567	tNET	FF	1	R33C22[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_3_cZ/I0
4.144	0.462	tINS	FR	1	R33C22[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_3_cZ/F
4.144	0.000	tNET	RR	1	R33C22[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R33C22[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_Z
6.681	-0.035	tSu		1	R33C22[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/current_tx_clk_edge_d1_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.462, 20.433%; route: 1.567, 69.306%; tC2Q: 0.232, 10.261%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path12

Path Summary:

Slack	2.566
Data Arrival Time	9.082
Data Required Time	11.648
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[3]
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R29C32[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch/CLK
2.115	0.232	tC2Q	RF	6	R29C32[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_latch/Q
3.124	1.009	tNET	FF	1	R23C36[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_0_i/I1
3.641	0.517	tINS	FF	3	R23C36[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/fn0_abort_0_i/F
4.758	1.117	tNET	FF	1	R21C36[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43_0_cZ/I1
5.129	0.371	tINS	FF	8	R21C36[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43_0_cZ/F
5.807	0.678	tNET	FF	1	R22C39[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43/I0
6.377	0.570	tINS	FR	1	R22C39[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_ctrl/n_state43/F
6.550	0.172	tNET	RR	1	R22C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state35_3_0_cZ/I2
7.105	0.555	tINS	RF	2	R22C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state35_3_0_cZ/F
7.522	0.418	tNET	FF	1	R25C38[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_ns_i_a3_1[3]/I1
7.893	0.371	tINS	FF	1	R25C38[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_ns_i_a3_1[3]/F
8.533	0.640	tNET	FF	1	R29C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_81_i_cZ/I1
9.082	0.549	tINS	FR	1	R29C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_81_i_cZ/F
9.082	0.000	tNET	RR	1	R29C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R29C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[3]/CLK
11.683	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[3]
11.648	-0.035	tSu		1	R29C38[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 2.933, 40.743%; route: 4.034, 56.034%; tC2Q: 0.232, 3.223%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	2.637
Data Arrival Time	9.012
Data Required Time	11.648
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[4]
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R17C23[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]/CLK
2.115	0.232	tC2Q	RF	99	R17C23[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]/Q
4.346	2.231	tNET	FF	1	R34C15[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_18[4]/I2
4.799	0.453	tINS	FF	1	R34C15[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_18[4]/F
5.754	0.955	tNET	FF	1	R27C20[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_36[4]/I1
6.324	0.570	tINS	FR	1	R27C20[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_36[4]/F
6.325	0.001	tNET	RR	1	R27C20[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_42[4]/I1
6.778	0.453	tINS	RF	1	R27C20[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_42[4]/F
6.778	0.000	tNET	FF	1	R27C20[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_45[4]/I0
6.881	0.103	tINS	FF	1	R27C20[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_45[4]/O
7.377	0.496	tNET	FF	1	R27C23[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_46[4]/I1
7.894	0.517	tINS	FF	1	R27C23[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_46[4]/F
8.550	0.656	tNET	FF	1	R22C23[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_cZ[4]/I1
9.012	0.462	tINS	FR	1	R22C23[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_cZ[4]/F
9.012	0.000	tNET	RR	1	R22C23[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R22C23[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[4]/CLK
11.683	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[4]
11.648	-0.035	tSu		1	R22C23[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[4]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 2.558, 35.884%; route: 4.338, 60.861%; tC2Q: 0.232, 3.255%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	2.820
Data Arrival Time	3.861
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_bit_oen
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R35C29[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_bit_oen/CLK
2.115	0.232	tC2Q	RF	27	R35C29[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_bit_oen/Q
3.490	1.375	tNET	FF	1	R25C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_RNO/I1
3.861	0.371	tINS	FF	1	R25C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_RNO/F
3.861	0.000	tNET	FF	1	R25C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R25C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_Z
6.681	-0.035	tSu		1	R25C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_en_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.371, 18.759%; route: 1.375, 69.511%; tC2Q: 0.232, 11.730%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path15

Path Summary:

Slack	2.904
Data Arrival Time	3.777
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_tx_rx/o_dat3
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R17C36[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_tx_rx/o_dat3/CLK
2.115	0.232	tC2Q	RF	2	R17C36[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd53_tx_rx/o_dat3/Q
3.315	1.200	tNET	FF	1	R26C26[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_3_0_a2/I1
3.777	0.462	tINS	FR	1	R26C26[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_3_0_a2/F
3.777	0.000	tNET	RR	1	R26C26[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R26C26[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_Z
6.681	-0.035	tSu		1	R26C26[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat3_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.462, 24.395%; route: 1.200, 63.355%; tC2Q: 0.232, 12.250%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path16

Path Summary:

Slack	2.979
Data Arrival Time	8.669
Data Required Time	11.648
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cccr_blk_size_1[4]
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[2]
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R27C25[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cccr_blk_size_1[4]/CLK
2.115	0.232	tC2Q	RF	7	R27C25[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cccr_blk_size_1[4]/Q
3.309	1.194	tNET	FF	2	R31C30[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_4_0/I0
3.858	0.549	tINS	FR	1	R31C30[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_4_0/COUT
3.858	0.000	tNET	RR	2	R31C30[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_5_0/CIN
3.894	0.035	tINS	RF	1	R31C30[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_5_0/COUT
3.894	0.000	tNET	FF	2	R31C31[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_6_0/CIN
3.929	0.035	tINS	FF	1	R31C31[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_6_0/COUT
3.929	0.000	tNET	FF	2	R31C31[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_7_0/CIN
3.964	0.035	tINS	FF	1	R31C31[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_7_0/COUT
3.964	0.000	tNET	FF	2	R31C31[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_8_0/CIN
3.999	0.035	tINS	FF	1	R31C31[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_8_0/COUT
3.999	0.000	tNET	FF	2	R31C31[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_9_0/CIN
4.034	0.035	tINS	FF	1	R31C31[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_9_0/COUT
4.034	0.000	tNET	FF	2	R31C31[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_10_0/CIN
4.070	0.035	tINS	FF	1	R31C31[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_10_0/COUT
4.070	0.000	tNET	FF	2	R31C31[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_11_0/CIN
4.105	0.035	tINS	FF	1	R31C31[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_11_0/COUT
4.105	0.000	tNET	FF	2	R31C32[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_12_0/CIN
4.140	0.035	tINS	FF	1	R31C32[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_12_0/COUT
4.140	0.000	tNET	FF	2	R31C32[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_13_0/CIN
4.175	0.035	tINS	FF	1	R31C32[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_13_0/COUT
4.175	0.000	tNET	FF	2	R31C32[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_14_0/CIN
4.210	0.035	tINS	FF	1	R31C32[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_14_0/COUT
4.210	0.000	tNET	FF	2	R31C32[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_15_0/CIN
4.246	0.035	tINS	FF	3	R31C32[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/un25_io53_fn0_reg_wr_cry_15_0/COUT
5.411	1.166	tNET	FF	1	R26C33[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/cmd_out_of_range_0_m2_1/I3
5.966	0.555	tINS	FF	5	R26C33[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/cmd_out_of_range_0_m2_1/F
6.644	0.677	tNET	FF	1	R26C38[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb_N_3L3_0_0_cZ/I1
7.097	0.453	tINS	FF	1	R26C38[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb_N_3L3_0_0_cZ/F
7.097	0.000	tNET	FF	1	R26C38[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb_N_3L3_0_cZ/I0
7.200	0.103	tINS	FF	1	R26C38[3][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb_N_3L3_0_cZ/O
7.200	0.000	tNET	FF	1	R26C38[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb_N_3L3/I0
7.303	0.103	tINS	FF	1	R26C38[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb_N_3L3/O
8.207	0.904	tNET	FF	1	R26C38[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb/I0
8.669	0.462	tINS	FR	1	R26C38[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/N_79_i_mb/F
8.669	0.000	tNET	RR	1	R26C38[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R26C38[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[2]/CLK
11.683	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[2]
11.648	-0.035	tSu		1	R26C38[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_Z[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 2.612, 38.495%; route: 3.942, 58.086%; tC2Q: 0.232, 3.419%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	2.991
Data Arrival Time	3.690
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.120	1.005	tNET	FF	1	R25C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_RNO/I0
3.690	0.570	tINS	FR	1	R25C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_RNO/F
3.690	0.000	tNET	RR	1	R25C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R25C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_Z
6.681	-0.035	tSu		1	R25C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_data_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 31.544%; route: 1.005, 55.617%; tC2Q: 0.232, 12.839%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path18

Path Summary:

Slack	2.991
Data Arrival Time	3.690
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.120	1.005	tNET	FF	1	R25C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_3_0_a2_0_a2/I0
3.690	0.570	tINS	FR	1	R25C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_3_0_a2_0_a2/F
3.690	0.000	tNET	RR	1	R25C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R25C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_Z
6.681	-0.035	tSu		1	R25C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_cmd_di_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 31.544%; route: 1.005, 55.617%; tC2Q: 0.232, 12.839%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path19

Path Summary:

Slack	2.991
Data Arrival Time	3.690
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.120	1.005	tNET	FF	1	R25C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_RNO/I0
3.690	0.570	tINS	FR	1	R25C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_RNO/F
3.690	0.000	tNET	RR	1	R25C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R25C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_Z
6.681	-0.035	tSu		1	R25C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_volt_sw_valid_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 31.544%; route: 1.005, 55.617%; tC2Q: 0.232, 12.839%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path20

Path Summary:

Slack	2.999
Data Arrival Time	3.682
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.112	0.997	tNET	FF	1	R26C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_3_0_a2/I0
3.682	0.570	tINS	FR	1	R26C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_3_0_a2/F
3.682	0.000	tNET	RR	1	R26C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R26C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_Z
6.681	-0.035	tSu		1	R26C28[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 31.682%; route: 0.997, 55.423%; tC2Q: 0.232, 12.895%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path21

Path Summary:

Slack	2.999
Data Arrival Time	3.682
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.112	0.997	tNET	FF	1	R26C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_RNO/I0
3.682	0.570	tINS	FR	1	R26C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_RNO/F
3.682	0.000	tNET	RR	1	R26C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R26C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_Z
6.681	-0.035	tSu		1	R26C28[1][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 31.682%; route: 0.997, 55.423%; tC2Q: 0.232, 12.895%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path22

Path Summary:

Slack	2.999
Data Arrival Time	3.682
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.112	0.997	tNET	FF	1	R26C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_RNO/I0
3.682	0.570	tINS	FR	1	R26C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_RNO/F
3.682	0.000	tNET	RR	1	R26C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R26C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_Z
6.681	-0.035	tSu		1	R26C28[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat1_en_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 31.682%; route: 0.997, 55.423%; tC2Q: 0.232, 12.895%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path23

Path Summary:

Slack	2.999
Data Arrival Time	3.682
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.112	0.997	tNET	FF	1	R26C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_RNO/I0
3.682	0.570	tINS	FR	1	R26C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_RNO/F
3.682	0.000	tNET	RR	1	R26C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R26C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_Z
6.681	-0.035	tSu		1	R26C28[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_o_dat0_en_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.570, 31.682%; route: 0.997, 55.423%; tC2Q: 0.232, 12.895%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Path24

Path Summary:

Slack	3.002
Data Arrival Time	8.646
Data Required Time	11.648
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[6]
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R17C23[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]/CLK
2.115	0.232	tC2Q	RF	99	R17C23[0][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_Z[2]/Q
4.346	2.231	tNET	FF	1	R34C15[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_18[6]/I2
4.799	0.453	tINS	FF	1	R34C15[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_18[6]/F
5.289	0.490	tNET	FF	1	R34C19[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_36[6]/I1
5.660	0.371	tINS	FF	1	R34C19[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_36[6]/F
5.664	0.004	tNET	FF	1	R34C19[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_42[6]/I1
6.219	0.555	tINS	FF	1	R34C19[2][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_42[6]/F
6.903	0.684	tNET	FF	1	R26C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_46[6]/I0
7.420	0.517	tINS	FF	1	R26C22[2][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_46[6]/F
8.076	0.656	tNET	FF	1	R21C22[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_cZ[6]/I1
8.646	0.570	tINS	FR	1	R21C22[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_52_cZ[6]/F
8.646	0.000	tNET	RR	1	R21C22[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R21C22[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[6]/CLK
11.683	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[6]
11.648	-0.035	tSu		1	R21C22[1][A]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd53_fn0_reg_rddata_Z[6]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 2.466, 36.464%; route: 4.065, 60.105%; tC2Q: 0.232, 3.431%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	3.012
Data Arrival Time	3.669
Data Required Time	6.681
From	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast
To	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_Z
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/CLK
2.115	0.232	tC2Q	RF	53	R21C22[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/cmd52_rst_gen_fast_fast/Q
3.120	1.005	tNET	FF	1	R25C28[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_RNO/I1
3.669	0.549	tINS	FR	1	R25C28[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_RNO/F
3.669	0.000	tNET	RR	1	R25C28[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R25C28[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_Z/CLK
6.716	-0.200	tUnc				u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_Z
6.681	-0.035	tSu		1	R25C28[0][B]	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/tmp_cmd19_o_dat0_en_Z

Path Statistics:

Clock Skew	0.033
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.549, 30.739%; route: 1.005, 56.271%; tC2Q: 0.232, 12.990%
Required Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.074
Data Arrival Time	1.900
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[124]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[124]/CLK
1.778	0.201	tC2Q	RF	1	R11C12[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[124]/Q
1.900	0.122	tNET	FF	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI16

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.074
Data Arrival Time	1.900
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[123]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[123]/CLK
1.778	0.201	tC2Q	RF	1	R11C12[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[123]/Q
1.900	0.122	tNET	FF	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI15

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.074
Data Arrival Time	1.900
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[112]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[112]/CLK
1.778	0.201	tC2Q	RF	1	R11C11[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[112]/Q
1.900	0.122	tNET	FF	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.076
Data Arrival Time	1.903
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[122]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[122]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[122]/Q
1.903	0.123	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI14

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.076
Data Arrival Time	1.903
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[121]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[121]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[121]/Q
1.903	0.123	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.076
Data Arrival Time	1.903
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[120]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[120]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[120]/Q
1.903	0.123	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.076
Data Arrival Time	1.903
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]/Q
1.903	0.123	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_7
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R46[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_7/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R46[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_7/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_7
1.718	0.141	tHld		1	BSRAM_R46[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_7

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_5
1.718	0.141	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R28[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R28[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_4
1.718	0.141	tHld		1	BSRAM_R28[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R46[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R46[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
1.718	0.141	tHld		1	BSRAM_R46[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.718	0.141	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_2
1.718	0.141	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R28[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R28[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
1.718	0.141	tHld		1	BSRAM_R28[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.194
Data Arrival Time	1.912
Data Required Time	1.718
From	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.779	0.202	tC2Q	RR	11	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.912	0.133	tNET	RR	1	BSRAM_R28[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/WREA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R28[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_0
1.718	0.141	tHld		1	BSRAM_R28[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.202
Data Arrival Time	2.029
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[117]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C11[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[117]/CLK
1.779	0.202	tC2Q	RR	1	R12C11[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[117]/Q
2.029	0.249	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.202
Data Arrival Time	2.029
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C11[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]/CLK
1.779	0.202	tC2Q	RR	1	R12C11[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]/Q
2.029	0.249	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI8

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.202
Data Arrival Time	2.029
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[115]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C11[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[115]/CLK
1.779	0.202	tC2Q	RR	1	R12C11[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[115]/Q
2.029	0.249	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.202
Data Arrival Time	2.029
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[114]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C11[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[114]/CLK
1.779	0.202	tC2Q	RR	1	R12C11[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[114]/Q
2.029	0.249	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[125]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C13[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[125]/CLK
1.779	0.202	tC2Q	RR	1	R9C13[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[125]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI17

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C11[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]/CLK
1.779	0.202	tC2Q	RR	1	R12C11[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[113]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C11[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[113]/CLK
1.779	0.202	tC2Q	RR	1	R12C11[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[113]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[110]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[110]/CLK
1.779	0.202	tC2Q	RR	1	R11C11[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[110]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[111]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[111]/CLK
1.779	0.202	tC2Q	RR	1	R11C11[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[111]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.225
Data Arrival Time	2.052
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[107]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5
Launch Clk	sdio_clkin:[R]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C14[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[107]/CLK
1.779	0.202	tC2Q	RR	1	R9C14[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[107]/Q
2.052	0.272	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5/DI17

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_5
1.826	0.249	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.599
Data Arrival Time	8.049
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
8.049	0.901	tNET	FF	1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/match_sep
11.648	-0.035	tSu		1	R5C3[2][A]	u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.901, 79.529%; tC2Q: 0.232, 20.471%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	3.599
Data Arrival Time	8.049
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
8.049	0.901	tNET	FF	1	R5C3[2][B]	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C3[2][B]	u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_dly_Z[0]
11.648	-0.035	tSu		1	R5C3[2][B]	u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.901, 79.529%; tC2Q: 0.232, 20.471%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	3.664
Data Arrival Time	7.984
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.984	0.836	tNET	FF	1	R2C7[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C7[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
11.648	-0.035	tSu		1	R2C7[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.836, 78.279%; tC2Q: 0.232, 21.721%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	3.664
Data Arrival Time	7.984
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.984	0.836	tNET	FF	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.836, 78.279%; tC2Q: 0.232, 21.721%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	3.664
Data Arrival Time	7.984
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[2]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.984	0.836	tNET	FF	1	R2C7[0][B]	u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C7[0][B]	u_la0_top/triger_level_cnt_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[2]
11.648	-0.035	tSu		1	R2C7[0][B]	u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.836, 78.279%; tC2Q: 0.232, 21.721%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	3.664
Data Arrival Time	7.984
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[3]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.984	0.836	tNET	FF	1	R2C7[0][A]	u_la0_top/triger_level_cnt_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C7[0][A]	u_la0_top/triger_level_cnt_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[3]
11.648	-0.035	tSu		1	R2C7[0][A]	u_la0_top/triger_level_cnt_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.836, 78.279%; tC2Q: 0.232, 21.721%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	3.667
Data Arrival Time	7.981
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.981	0.833	tNET	FF	1	R11C2[1][A]	u_la0_top/capture_window_sel_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[1][A]	u_la0_top/capture_window_sel_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[0]
11.648	-0.035	tSu		1	R11C2[1][A]	u_la0_top/capture_window_sel_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.833, 78.216%; tC2Q: 0.232, 21.784%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	3.667
Data Arrival Time	7.981
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.981	0.833	tNET	FF	1	R11C2[1][B]	u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[1][B]	u_la0_top/capture_window_sel_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[1]
11.648	-0.035	tSu		1	R11C2[1][B]	u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.833, 78.216%; tC2Q: 0.232, 21.784%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	3.667
Data Arrival Time	7.981
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[2]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.981	0.833	tNET	FF	1	R11C2[2][A]	u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[2][A]	u_la0_top/capture_window_sel_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[2]
11.648	-0.035	tSu		1	R11C2[2][A]	u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.833, 78.216%; tC2Q: 0.232, 21.784%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	3.667
Data Arrival Time	7.981
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel[3]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.981	0.833	tNET	FF	1	R11C2[2][B]	u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[2][B]	u_la0_top/capture_window_sel[3]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel[3]
11.648	-0.035	tSu		1	R11C2[2][B]	u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.833, 78.216%; tC2Q: 0.232, 21.784%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	3.672
Data Arrival Time	7.976
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.976	0.828	tNET	FF	1	R6C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648	-0.035	tSu		1	R6C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.828, 78.112%; tC2Q: 0.232, 21.888%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	3.681
Data Arrival Time	7.967
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.967	0.819	tNET	FF	1	R4C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R4C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.819, 77.924%; tC2Q: 0.232, 22.076%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	3.681
Data Arrival Time	7.967
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.967	0.819	tNET	FF	1	R4C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R4C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.819, 77.924%; tC2Q: 0.232, 22.076%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	3.681
Data Arrival Time	7.967
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.967	0.819	tNET	FF	1	R4C3[1][A]	u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C3[1][A]	u_la0_top/triger_level_cnt_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[0]
11.648	-0.035	tSu		1	R4C3[1][A]	u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.819, 77.924%; tC2Q: 0.232, 22.076%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	3.681
Data Arrival Time	7.967
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.967	0.819	tNET	FF	1	R4C3[1][B]	u_la0_top/triger_level_cnt_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C3[1][B]	u_la0_top/triger_level_cnt_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[1]
11.648	-0.035	tSu		1	R4C3[1][B]	u_la0_top/triger_level_cnt_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.819, 77.924%; tC2Q: 0.232, 22.076%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	3.684
Data Arrival Time	7.964
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.964	0.816	tNET	FF	1	R4C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R4C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.816, 77.869%; tC2Q: 0.232, 22.131%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	3.684
Data Arrival Time	7.964
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.964	0.816	tNET	FF	1	R4C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648	-0.035	tSu		1	R4C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.816, 77.869%; tC2Q: 0.232, 22.131%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	3.684
Data Arrival Time	7.964
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[6]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.964	0.816	tNET	FF	1	R4C4[2][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C4[2][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[6]
11.648	-0.035	tSu		1	R4C4[2][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.816, 77.869%; tC2Q: 0.232, 22.131%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	3.684
Data Arrival Time	7.964
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.964	0.816	tNET	FF	1	R4C4[2][B]	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C4[2][B]	u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_syn_Z[0]
11.648	-0.035	tSu		1	R4C4[2][B]	u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.816, 77.869%; tC2Q: 0.232, 22.131%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	3.909
Data Arrival Time	7.739
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.739	0.591	tNET	FF	1	R3C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648	-0.035	tSu		1	R3C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.591, 71.809%; tC2Q: 0.232, 28.191%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	3.909
Data Arrival Time	7.739
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[9]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.739	0.591	tNET	FF	1	R3C4[0][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[0][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[9]
11.648	-0.035	tSu		1	R3C4[0][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.591, 71.809%; tC2Q: 0.232, 28.191%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	3.909
Data Arrival Time	7.739
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.739	0.591	tNET	FF	1	R3C4[0][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[0][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]
11.648	-0.035	tSu		1	R3C4[0][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.591, 71.809%; tC2Q: 0.232, 28.191%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	3.909
Data Arrival Time	7.739
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.739	0.591	tNET	FF	1	R3C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648	-0.035	tSu		1	R3C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.591, 71.809%; tC2Q: 0.232, 28.191%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	3.909
Data Arrival Time	7.739
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.739	0.591	tNET	FF	1	R3C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648	-0.035	tSu		1	R3C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.591, 71.809%; tC2Q: 0.232, 28.191%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	3.909
Data Arrival Time	7.739
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.739	0.591	tNET	FF	1	R3C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sdio_clkin(clock)
10.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	1793	IOL27[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648	-0.035	tSu		1	R3C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.591, 71.809%; tC2Q: 0.232, 28.191%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.397
Data Arrival Time	7.185
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.185	0.393	tNET	RR	1	R3C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R3C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.393, 66.047%; tC2Q: 0.202, 33.953%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	5.397
Data Arrival Time	7.185
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.185	0.393	tNET	RR	1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.393, 66.047%; tC2Q: 0.202, 33.953%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	5.397
Data Arrival Time	7.185
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.185	0.393	tNET	RR	1	R3C2[2][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C2[2][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[1]
1.788	0.011	tHld		1	R3C2[2][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.393, 66.047%; tC2Q: 0.202, 33.953%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	5.397
Data Arrival Time	7.185
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[2]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.185	0.393	tNET	RR	1	R3C2[2][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C2[2][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[2]
1.788	0.011	tHld		1	R3C2[2][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.393, 66.047%; tC2Q: 0.202, 33.953%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	5.402
Data Arrival Time	7.190
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/trigger_seq_start_Z
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.190	0.398	tNET	RR	1	R2C3[1][A]	u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C3[1][A]	u_la0_top/trigger_seq_start_Z/CLK
1.777	0.200	tUnc				u_la0_top/trigger_seq_start_Z
1.788	0.011	tHld		1	R2C3[1][A]	u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.328%; tC2Q: 0.202, 33.672%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	5.402
Data Arrival Time	7.190
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.190	0.398	tNET	RR	1	R2C3[2][B]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C3[2][B]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/internal_reg_force_triger_syn_Z[0]
1.788	0.011	tHld		1	R2C3[2][B]	u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.328%; tC2Q: 0.202, 33.672%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	5.402
Data Arrival Time	7.190
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_dly_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.190	0.398	tNET	RR	1	R2C3[0][A]	u_la0_top/internal_reg_start_dly_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C3[0][A]	u_la0_top/internal_reg_start_dly_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/internal_reg_start_dly_Z[1]
1.788	0.011	tHld		1	R2C3[0][A]	u_la0_top/internal_reg_start_dly_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.328%; tC2Q: 0.202, 33.672%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	5.402
Data Arrival Time	7.190
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_force_triger_syn_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.190	0.398	tNET	RR	1	R2C3[2][A]	u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C3[2][A]	u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/internal_reg_force_triger_syn_Z[1]
1.788	0.011	tHld		1	R2C3[2][A]	u_la0_top/internal_reg_force_triger_syn_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.328%; tC2Q: 0.202, 33.672%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	5.402
Data Arrival Time	7.190
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_end_dly_Z
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.190	0.398	tNET	RR	1	R2C3[0][B]	u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C3[0][B]	u_la0_top/capture_end_dly_Z/CLK
1.777	0.200	tUnc				u_la0_top/capture_end_dly_Z
1.788	0.011	tHld		1	R2C3[0][B]	u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.328%; tC2Q: 0.202, 33.672%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	5.403
Data Arrival Time	7.191
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.191	0.399	tNET	RR	1	R4C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R4C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R4C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.399, 66.386%; tC2Q: 0.202, 33.614%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	5.403
Data Arrival Time	7.191
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.191	0.399	tNET	RR	1	R4C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R4C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R4C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.399, 66.386%; tC2Q: 0.202, 33.614%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	5.403
Data Arrival Time	7.191
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.191	0.399	tNET	RR	1	R4C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R4C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R4C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.399, 66.386%; tC2Q: 0.202, 33.614%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	5.403
Data Arrival Time	7.191
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.191	0.399	tNET	RR	1	R4C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R4C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
1.788	0.011	tHld		1	R4C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.399, 66.386%; tC2Q: 0.202, 33.614%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	5.404
Data Arrival Time	7.193
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_syn_Z[1]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.193	0.400	tNET	RR	1	R3C3[2][A]	u_la0_top/internal_reg_start_syn_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[2][A]	u_la0_top/internal_reg_start_syn_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/internal_reg_start_syn_Z[1]
1.788	0.011	tHld		1	R3C3[2][A]	u_la0_top/internal_reg_start_syn_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 66.464%; tC2Q: 0.202, 33.536%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	5.407
Data Arrival Time	7.196
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.196	0.403	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.403, 66.630%; tC2Q: 0.202, 33.370%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
1.788	0.011	tHld		1	R2C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R2C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R2C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[3]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C5[0][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[0][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[3]
1.788	0.011	tHld		1	R2C5[0][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[5]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C5[1][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[1][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[5]
1.788	0.011	tHld		1	R2C5[1][A]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R2C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[7]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C5[1][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[1][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[7]
1.788	0.011	tHld		1	R2C5[1][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[4]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C5[0][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[0][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[4]
1.788	0.011	tHld		1	R2C5[0][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	5.409
Data Arrival Time	7.198
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[8]
Launch Clk	sdio_clkin:[F]
Latch Clk	sdio_clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sdio_clkin(clock)
5.000	0.000	tCL	FF	1	IOL27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	1793	IOL27[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R2C2[0][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	53	R2C2[0][A]	u_la0_top/rst_ao_Z/Q
7.198	0.405	tNET	RR	1	R2C4[2][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sdio_clkin(clock)
0.000	0.000	tCL	RR	1	IOL27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	1793	IOL27[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[2][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[8]
1.788	0.011	tHld		1	R2C4[2][B]	u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.405, 66.731%; tC2Q: 0.202, 33.269%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	user_sdio_cmd52_if_user_sdio_cmd52_ack_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	user_sdio_cmd52_if_user_sdio_cmd52_ack_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	user_sdio_cmd52_if_user_sdio_cmd52_ack_Z/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	user_sdio_cmd53_wr_abort_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	user_sdio_cmd53_wr_abort_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	user_sdio_cmd53_wr_abort_Z/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	user_sdio_cmd53_rd_en_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	user_sdio_cmd53_rd_en_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	user_sdio_cmd53_rd_en_Z/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	user_sdio_cmd52_if_user_sdio_cmd52_cs_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	user_sdio_cmd52_if_user_sdio_cmd52_cs_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	user_sdio_cmd52_if_user_sdio_cmd52_cs_Z/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	user_sdio_cmd52_if_user_sdio_cmd52_addr_Z[4]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	user_sdio_cmd52_if_user_sdio_cmd52_addr_Z[4]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	user_sdio_cmd52_if_user_sdio_cmd52_addr_Z[4]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	user_sdio_cmd53_addr_Z[7]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	user_sdio_cmd53_addr_Z[7]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	user_sdio_cmd53_addr_Z[7]/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/cmd5_check_ocr_val_Z[13]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/cmd5_check_ocr_val_Z[13]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/cmd5_check_ocr_val_Z[13]/CLK

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/io53_addr_Z[3]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/io53_addr_Z[3]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/io53_addr_Z[3]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_byte_tmp_Z[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_byte_tmp_Z[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_resp_conv/resp_byte_tmp_Z[1]/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sdio_clkin
Objects:	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sdio_clkin(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sdio_clkin(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_fn0_reg/manual_tx_clk_edge_d2_Z/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1793	clk_c	1.652	1.616
289	cmd52_rst_rep2	6.762	2.201
278	cmd52_rstz	5.818	3.145
276	cmd52_rst_rep1	6.099	1.961
118	cmd53_ctrl_fn0_addr_d1[0]	3.067	1.303
99	cmd53_ctrl_fn0_addr_d1[2]	2.637	3.601
97	cmd53_ctrl_fn0_addr_d1[1]	3.512	2.044
78	c_state[4]	6.252	1.323
78	cmd52_rst_fast	5.522	2.623
75	cmd52_rst_fast_rep2	5.138	2.463

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R20C22	0.750
R18C25	0.722
R27C32	0.722
R36C37	0.708
R25C30	0.708
R21C24	0.694
R31C16	0.694
R35C35	0.681
R16C36	0.681
R16C22	0.681

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name sdio_clkin -period 10 -waveform {0 5} [get_ports {clk}]