| Report Title |
Gowin Power Analysis Report |
| Design File |
E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\impl\synthesize\rev_1\psram_ref_design.vm |
| Physical Constraints File |
E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram.cst |
| Timing Constraints File |
E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram.sdc |
| GOWIN Version |
V1.9.5.02Beta |
| Part Number |
GW2AR-LV18EQ144PC8/I7 |
| Created Time |
Tue May 19 15:08:03 2020
|
| Legal Announcement |
Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
273.790 |
| Quiescent Power (mW) |
23.748 |
| Dynamic Power (mW) |
250.042 |
| Psram Power (mW) |
86.000 |
| Junction Temperature |
37.346 |
| Theta JA |
45.450 |
| Max Allowed Ambient Temperature |
72.556 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.000 |
233.871 |
14.606 |
248.477 |
| VCCX |
2.500 |
3.767 |
2.131 |
14.746 |
| VCCO18 |
1.800 |
3.751 |
2.119 |
10.567 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
30.215 |
NA |
12.564 |
| IO |
31.528
| 11.301
| 18.576
|
| BSRAM |
32.760
| NA |
NA |
| DLL |
46.080
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
| psram_syn_top |
213.299 |
92.675(92.675) |
120.623(119.386) |
| psram_syn_top/u5/ |
4.107 |
1.943(0.000) |
2.164(0.000) |
| psram_syn_top/u_psram_top/ |
173.134 |
70.305(70.305) |
102.830(102.830) |
| psram_syn_top/u_psram_top/u_psram_top/ |
173.134 |
70.305(21.990) |
102.830(88.999) |
| psram_syn_top/u_psram_top/u_psram_top/u_psram_init/ |
54.597 |
13.453(0.000) |
41.143(0.000) |
| psram_syn_top/u_psram_top/u_psram_top/u_psram_sync/ |
7.185 |
2.052(0.000) |
5.133(0.000) |
| psram_syn_top/u_psram_top/u_psram_top/u_psram_wd/ |
49.207 |
6.485(5.118) |
42.722(41.500) |
| psram_syn_top/u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
30.859 |
3.207(0.000) |
27.652(0.000) |
| psram_syn_top/u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
15.759 |
1.911(0.000) |
13.849(0.000) |
| psram_syn_top/u_test/ |
34.820 |
20.427(0.000) |
14.392(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| clk_x1 |
100.000 |
163.009 |
| clk_x2 |
200.000 |
49.887 |
| u_PLL/CLKOUT.default_gen_clk |
160.000 |
0.539 |