@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":22:7:22:10|Tristate driver j8_5 (in view: work.topS(verilog)) on net j8_5 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":23:7:23:10|Tristate driver j8_6 (in view: work.topS(verilog)) on net j8_6 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":24:7:24:10|Tristate driver j8_7 (in view: work.topS(verilog)) on net j8_7 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":25:7:25:10|Tristate driver j8_8 (in view: work.topS(verilog)) on net j8_8 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":38:7:38:11|Tristate driver j8_21 (in view: work.topS(verilog)) on net j8_21 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":39:7:39:11|Tristate driver j8_22 (in view: work.topS(verilog)) on net j8_22 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":40:7:40:11|Tristate driver j8_23 (in view: work.topS(verilog)) on net j8_23 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":41:7:41:11|Tristate driver j8_24 (in view: work.topS(verilog)) on net j8_24 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":42:7:42:11|Tristate driver j8_25 (in view: work.topS(verilog)) on net j8_25 (in view: work.topS(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\slave.sv":43:7:43:11|Tristate driver j8_26 (in view: work.topS(verilog)) on net j8_26 (in view: work.topS(verilog)) has its enable tied to GND.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":51:0:51:5|Removing sequential instance keyPos_0 (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":51:0:51:5|Removing sequential instance keyNeg_0 (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":51:0:51:5|Removing sequential instance keyPos_0 (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":51:0:51:5|Removing sequential instance keyNeg_0 (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":47:0:47:5|Removing sequential instance keyValue[1] (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":47:0:47:5|Removing sequential instance keyValue[1] (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":47:0:47:5|Removing sequential instance keyValue[0] (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_s\src\dejitter.sv":47:0:47:5|Removing sequential instance keyValue[0] (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: MF974 |Total number of latches (multibit) processed = 0 
@N: MF975 |Total number of latches (bit blasted) processed = 0 
@N: MF976 |Total number of (multibit) opaque latches found = 0 
@N: MF977 |Total number of (bit blasted) opaque latches found = 0 
@N: MF578 |Incompatible asynchronous control logic preventing generated clock conversion.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\impl\synthesize\rev_1\slave.sap.
