@W: CG921 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":215:4:215:8|pcInc is already declared in this scope.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":16:7:16:11|Removing wire led_4, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":17:7:17:11|Removing wire led_5, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":18:7:18:11|Removing wire led_6, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":22:7:22:10|Removing wire j8_5, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":23:7:23:10|Removing wire j8_6, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":24:7:24:10|Removing wire j8_7, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":25:7:25:10|Removing wire j8_8, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":38:7:38:11|Removing wire j8_21, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":39:7:39:11|Removing wire j8_22, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":40:7:40:11|Removing wire j8_23, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":41:7:41:11|Removing wire j8_24, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":42:7:42:11|Removing wire j8_25, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":43:7:43:11|Removing wire j8_26, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":44:7:44:11|Removing wire j8_27, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":45:7:45:11|Removing wire j8_28, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":46:7:46:11|Removing wire j8_29, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":47:7:47:11|Removing wire j8_30, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":48:7:48:11|Removing wire j8_31, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":49:7:49:11|Removing wire j8_32, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":50:7:50:11|Removing wire j8_33, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":51:7:51:11|Removing wire j8_34, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":52:7:52:11|Removing wire j8_35, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":53:7:53:11|Removing wire j8_36, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":54:7:54:11|Removing wire j8_37, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":55:7:55:11|Removing wire j8_38, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":60:7:60:10|Removing wire j9_6, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":61:7:61:10|Removing wire j9_7, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":62:7:62:10|Removing wire j9_8, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":63:7:63:10|Removing wire j9_9, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":72:7:72:11|Removing wire j9_18, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":73:7:73:11|Removing wire j9_19, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":74:7:74:11|Removing wire j9_20, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":75:7:75:11|Removing wire j9_21, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":76:7:76:11|Removing wire j9_22, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":77:7:77:11|Removing wire j9_23, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":78:7:78:11|Removing wire j9_24, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":79:7:79:11|Removing wire j9_25, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":80:7:80:11|Removing wire j9_26, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":81:7:81:11|Removing wire j9_27, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":82:7:82:11|Removing wire j9_28, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":83:7:83:11|Removing wire j9_29, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":84:7:84:11|Removing wire j9_30, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":85:7:85:11|Removing wire j9_31, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":86:7:86:11|Removing wire j9_32, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":87:7:87:11|Removing wire j9_33, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":88:7:88:11|Removing wire j9_34, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":89:7:89:11|Removing wire j9_35, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":90:7:90:11|Removing wire j9_36, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":91:7:91:11|Removing wire j9_37, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":92:7:92:11|Removing wire j9_38, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":97:8:97:12|Removing wire j10_6, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":98:8:98:12|Removing wire j10_9, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":99:8:99:13|Removing wire j10_10, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":181:18:181:21|Removing wire key3, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":181:23:181:26|Removing wire key4, as there is no assignment to it.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":16:7:16:11|*Output led_4 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":17:7:17:11|*Output led_5 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":18:7:18:11|*Output led_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":22:7:22:10|*Output j8_5 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":23:7:23:10|*Output j8_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":24:7:24:10|*Output j8_7 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":25:7:25:10|*Output j8_8 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":38:7:38:11|*Output j8_21 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":39:7:39:11|*Output j8_22 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":40:7:40:11|*Output j8_23 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":41:7:41:11|*Output j8_24 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":42:7:42:11|*Output j8_25 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":43:7:43:11|*Output j8_26 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":44:7:44:11|*Output j8_27 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":45:7:45:11|*Output j8_28 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":46:7:46:11|*Output j8_29 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":47:7:47:11|*Output j8_30 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":48:7:48:11|*Output j8_31 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":49:7:49:11|*Output j8_32 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":50:7:50:11|*Output j8_33 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":51:7:51:11|*Output j8_34 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":52:7:52:11|*Output j8_35 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":53:7:53:11|*Output j8_36 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":54:7:54:11|*Output j8_37 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":55:7:55:11|*Output j8_38 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":60:7:60:10|*Output j9_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":61:7:61:10|*Output j9_7 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":62:7:62:10|*Output j9_8 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":63:7:63:10|*Output j9_9 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":72:7:72:11|*Output j9_18 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":73:7:73:11|*Output j9_19 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":74:7:74:11|*Output j9_20 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":75:7:75:11|*Output j9_21 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":76:7:76:11|*Output j9_22 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":77:7:77:11|*Output j9_23 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":78:7:78:11|*Output j9_24 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":79:7:79:11|*Output j9_25 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":80:7:80:11|*Output j9_26 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":81:7:81:11|*Output j9_27 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":82:7:82:11|*Output j9_28 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":83:7:83:11|*Output j9_29 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":84:7:84:11|*Output j9_30 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":85:7:85:11|*Output j9_31 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":86:7:86:11|*Output j9_32 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":87:7:87:11|*Output j9_33 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":88:7:88:11|*Output j9_34 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":89:7:89:11|*Output j9_35 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":90:7:90:11|*Output j9_36 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":91:7:91:11|*Output j9_37 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":92:7:92:11|*Output j9_38 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":97:8:97:12|*Output j10_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":98:8:98:12|*Output j10_9 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":99:8:99:13|*Output j10_10 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":244:0:244:5|Pruning unused register ptr_SL[10:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":244:0:244:5|Pruning unused register data_tmp[7:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":244:0:244:5|Optimizing register bit addr[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":244:0:244:5|Optimizing register bit addr[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\project_S\src\slave.sv":244:0:244:5|Pruning register bits 9 to 8 of addr[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

