@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":19:7:19:11|Tristate driver led_6 (in view: work.topM(verilog)) on net led_6 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":18:7:18:11|Tristate driver led_5 (in view: work.topM(verilog)) on net led_5 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":17:7:17:11|Tristate driver led_4 (in view: work.topM(verilog)) on net led_4 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":100:8:100:13|Tristate driver j10_10 (in view: work.topM(verilog)) on net j10_10 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":99:8:99:12|Tristate driver j10_9 (in view: work.topM(verilog)) on net j10_9 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":98:8:98:12|Tristate driver j10_6 (in view: work.topM(verilog)) on net j10_6 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":93:7:93:11|Tristate driver j9_38 (in view: work.topM(verilog)) on net j9_38 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":92:7:92:11|Tristate driver j9_37 (in view: work.topM(verilog)) on net j9_37 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":91:7:91:11|Tristate driver j9_36 (in view: work.topM(verilog)) on net j9_36 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":90:7:90:11|Tristate driver j9_35 (in view: work.topM(verilog)) on net j9_35 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\dejitter.sv":51:0:51:5|Removing sequential instance keyPos_0 (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\dejitter.sv":51:0:51:5|Removing sequential instance keyNeg_0 (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\dejitter.sv":51:0:51:5|Removing sequential instance keyNeg_0 (in view: work.deJitter_1s_15_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\dejitter.sv":47:0:47:5|Removing sequential instance keyValue[1] (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\dejitter.sv":47:0:47:5|Removing sequential instance keyValue[0] (in view: work.deJitter_1s_15_3_1(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: MF974 |Total number of latches (multibit) processed = 0 
@N: MF975 |Total number of latches (bit blasted) processed = 0 
@N: MF976 |Total number of (multibit) opaque latches found = 0 
@N: MF977 |Total number of (bit blasted) opaque latches found = 0 
@N: MF578 |Incompatible asynchronous control logic preventing generated clock conversion.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\impl\synthesize\rev_1\master.sap.
