@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":100:8:100:13|Tristate driver j10_10 (in view: work.topM(verilog)) on net j10_10 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":99:8:99:12|Tristate driver j10_9 (in view: work.topM(verilog)) on net j10_9 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":98:8:98:12|Tristate driver j10_6 (in view: work.topM(verilog)) on net j10_6 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":93:7:93:11|Tristate driver j9_38 (in view: work.topM(verilog)) on net j9_38 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":92:7:92:11|Tristate driver j9_37 (in view: work.topM(verilog)) on net j9_37 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":91:7:91:11|Tristate driver j9_36 (in view: work.topM(verilog)) on net j9_36 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":90:7:90:11|Tristate driver j9_35 (in view: work.topM(verilog)) on net j9_35 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":89:7:89:11|Tristate driver j9_34 (in view: work.topM(verilog)) on net j9_34 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":88:7:88:11|Tristate driver j9_33 (in view: work.topM(verilog)) on net j9_33 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\master.sv":87:7:87:11|Tristate driver j9_32 (in view: work.topM(verilog)) on net j9_32 (in view: work.topM(verilog)) has its enable tied to GND.
@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "1" on instance deKey2.keyO.
@N: FX493 |Applying initial value "111" on instance deKey2.keyIn_r[2:0].
@N: FX493 |Applying initial value "00000000" on instance deKey2.counter[7:0].
@N: FX493 |Applying initial value "1" on instance deKey2.keyO.
@N: FX493 |Applying initial value "0" on instance deKey2.keyPos.
@N: FX493 |Applying initial value "11" on instance deKey2.keyValue[1:0].
@N: FX493 |Applying initial value "111" on instance deKey2.keyIn_r[2:0].
@N: FX493 |Applying initial value "00000000" on instance deKey2.counter[7:0].
@N: FX493 |Applying initial value "00000000" on instance cnt[7:0].
@N: FX493 |Applying initial value "0" on instance wre.
@N: FX493 |Applying initial value "000000000000" on instance addr[11:0].
@N: FX493 |Applying initial value "00000000" on instance dataNI[7:0].
@N: FX493 |Applying initial value "00000000" on instance dataNum[7:0].
@N: FX493 |Applying initial value "00000000000" on instance ptr_M[10:0].
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
