Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller.v D:\Gowin\Gowin_V1.9.8.09\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.09 |
| Part Number | GW1NZ-LV1FN32C5/I4 |
| Device | GW1NZ-1 |
| Created Time | Mon Oct 24 16:50:20 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_Flash_Controller_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.263s, Peak memory usage = 46.289MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 46.289MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 46.289MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 46.289MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 46.289MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 46.289MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 46.289MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 46.289MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 46.289MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 46.289MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 46.289MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 46.289MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.883MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 57.883MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 57.883MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.883MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 81 |
| I/O Buf | 81 |
| IBUF | 48 |
| OBUF | 33 |
| Register | 340 |
| DFFC | 262 |
| DFFCE | 78 |
| LUT | 469 |
| LUT2 | 103 |
| LUT3 | 116 |
| LUT4 | 250 |
| INV | 1 |
| INV | 1 |
| User Flash | 1 |
| FLASH64KZ | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 470(470 LUTs, 0 ALUs) / 1152 | 41% |
| Register | 340 / 939 | 36% |
| --Register as Latch | 0 / 939 | 0% |
| --Register as FF | 340 / 939 | 36% |
| BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk_i | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_i_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 50.0(MHz) | 104.5(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 10.432 |
| Data Arrival Time | 10.749 |
| Data Required Time | 21.181 |
| From | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_1_s0 |
| To | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_15_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 1.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 1.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_1_s0/CLK |
| 2.254 | 0.573 | tC2Q | RF | 5 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_1_s0/Q |
| 2.854 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n242_s20/I1 |
| 4.228 | 1.374 | tINS | FF | 8 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n242_s20/F |
| 4.828 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n233_s20/I1 |
| 6.202 | 1.374 | tINS | FF | 7 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n233_s20/F |
| 6.802 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n232_s20/I1 |
| 8.175 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n232_s20/F |
| 8.775 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n231_s19/I1 |
| 10.149 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n231_s19/F |
| 10.749 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_15_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk_i | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 21.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 21.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_15_s0/CLK |
| 21.181 | -0.500 | tSu | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_15_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
| Arrival Data Path Delay: | cell: 5.495, 60.598%; route: 3.000, 33.084%; tC2Q: 0.573, 6.318% |
| Required Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
Path 2
Path Summary:| Slack | 10.516 |
| Data Arrival Time | 10.665 |
| Data Required Time | 21.181 |
| From | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_5_s0 |
| To | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_1_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 1.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 1.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_5_s0/CLK |
| 2.254 | 0.573 | tC2Q | RF | 3 | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_5_s0/Q |
| 2.854 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n265_s20/I1 |
| 4.228 | 1.374 | tINS | FF | 2 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n265_s20/F |
| 4.828 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n275_s24/I1 |
| 6.202 | 1.374 | tINS | FF | 4 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n275_s24/F |
| 6.802 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n277_s29/I0 |
| 8.092 | 1.290 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n277_s29/F |
| 8.692 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n277_s27/I1 |
| 10.065 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n277_s27/F |
| 10.665 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk_i | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 21.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 21.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_1_s1/CLK |
| 21.181 | -0.500 | tSu | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
| Arrival Data Path Delay: | cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377% |
| Required Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
Path 3
Path Summary:| Slack | 10.516 |
| Data Arrival Time | 10.665 |
| Data Required Time | 21.181 |
| From | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_5_s0 |
| To | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_0_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 1.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 1.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_5_s0/CLK |
| 2.254 | 0.573 | tC2Q | RF | 3 | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_5_s0/Q |
| 2.854 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n265_s20/I1 |
| 4.228 | 1.374 | tINS | FF | 2 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n265_s20/F |
| 4.828 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n275_s24/I1 |
| 6.202 | 1.374 | tINS | FF | 4 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n275_s24/F |
| 6.802 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n271_s21/I0 |
| 8.092 | 1.290 | tINS | FF | 9 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n271_s21/F |
| 8.692 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n271_s19/I1 |
| 10.065 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n271_s19/F |
| 10.665 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk_i | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 21.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 21.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_0_s0/CLK |
| 21.181 | -0.500 | tSu | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/rcv_cnt_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
| Arrival Data Path Delay: | cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377% |
| Required Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
Path 4
Path Summary:| Slack | 10.516 |
| Data Arrival Time | 10.665 |
| Data Required Time | 21.181 |
| From | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_21_s0 |
| To | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_0_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 1.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 1.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_21_s0/CLK |
| 2.254 | 0.573 | tC2Q | RF | 3 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_21_s0/Q |
| 2.854 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s28/I1 |
| 4.228 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s28/F |
| 4.828 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s21/I1 |
| 6.202 | 1.374 | tINS | FF | 2 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s21/F |
| 6.802 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n246_s20/I0 |
| 8.092 | 1.290 | tINS | FF | 23 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n246_s20/F |
| 8.692 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n246_s19/I1 |
| 10.065 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n246_s19/F |
| 10.665 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk_i | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 21.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 21.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_0_s0/CLK |
| 21.181 | -0.500 | tSu | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
| Arrival Data Path Delay: | cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377% |
| Required Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
Path 5
Path Summary:| Slack | 10.516 |
| Data Arrival Time | 10.665 |
| Data Required Time | 21.181 |
| From | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_14_s0 |
| To | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_0_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 1.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 1.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_14_s0/CLK |
| 2.254 | 0.573 | tC2Q | RF | 4 | u_Flash_Ctroller_64K/u_ER_UFM_64K/erase_cnt_14_s0/Q |
| 2.854 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n229_s20/I1 |
| 4.228 | 1.374 | tINS | FF | 4 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n229_s20/F |
| 4.828 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s22/I1 |
| 6.202 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s22/F |
| 6.802 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s18/I1 |
| 8.175 | 1.374 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s18/F |
| 8.775 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s17/I0 |
| 10.065 | 1.290 | tINS | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/n278_s17/F |
| 10.665 | 0.600 | tNET | FF | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk_i | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 21.227 | 1.227 | tINS | RR | 340 | clk_i_ibuf/O |
| 21.681 | 0.454 | tNET | RR | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_0_s0/CLK |
| 21.181 | -0.500 | tSu | 1 | u_Flash_Ctroller_64K/u_ER_UFM_64K/e_state_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |
| Arrival Data Path Delay: | cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377% |
| Required Clock Path Delay: | cell: 1.227, 73.009%; route: 0.454, 26.991% |