Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_1v4_hs.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_1v4_hs.sdc
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW5A-LV25UG324C1/I0
Device	GW5A-25
Device Version	B
Created Time	Fri Feb 28 16:30:19 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C1/I0
Hold Delay Model	Fast 0.945V 85C C1/I0
Numbers of Paths Analyzed	14871
Numbers of Endpoints Analyzed	21634
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Objects
1	clk4x	Base	2.500	400.000	1.250	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2	clk1x	Base	10.000	100.000	5.000	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
3	clkin	Base	20.000	50.000	10.000	clk_g

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk4x	400.000(MHz)	2016.128(MHz)	1	TOP
2	clk1x	100.000(MHz)	142.336(MHz)	6	TOP
3	clkin	50.000(MHz)	273.831(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk4x	Setup	0.000	0
clk4x	Hold	0.000	0
clk1x	Setup	0.000	0
clk1x	Hold	0.000	0
clkin	Setup	0.000	0
clkin	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
2	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
3	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
4	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
5	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
6	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
7	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
8	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
9	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
10	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
11	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
12	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
13	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
14	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
15	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
16	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
17	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
18	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
19	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
20	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
21	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
22	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496
23	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1]	clk4x:[R]	clk4x:[R]	2.500	0.496
24	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0]	clk4x:[R]	clk4x:[R]	2.500	0.496
25	2.004	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]	clk4x:[R]	clk4x:[R]	2.500	0.496

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.139	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[13]	clk1x:[R]	clk1x:[R]	0.001	0.175
2	0.139	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13]	clk1x:[R]	clk1x:[R]	0.001	0.175
3	0.142	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/D4	clk1x:[R]	clk1x:[R]	-0.002	0.239
4	0.142	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D2	clk1x:[R]	clk1x:[R]	-0.002	0.239
5	0.142	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D4	clk1x:[R]	clk1x:[R]	-0.002	0.239
6	0.143	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D6	clk1x:[R]	clk1x:[R]	-0.002	0.240
7	0.144	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[6]	clk1x:[R]	clk1x:[R]	-0.014	0.195
8	0.144	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_51_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[3]	clk1x:[R]	clk1x:[R]	-0.014	0.195
9	0.144	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[5]	clk1x:[R]	clk1x:[R]	-0.014	0.195
10	0.149	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[15]	clk1x:[R]	clk1x:[R]	-0.009	0.195
11	0.149	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[14]	clk1x:[R]	clk1x:[R]	-0.009	0.195
12	0.149	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[13]	clk1x:[R]	clk1x:[R]	-0.009	0.195
13	0.149	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13]	clk1x:[R]	clk1x:[R]	-0.009	0.195
14	0.153	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[7]	clk1x:[R]	clk1x:[R]	-0.005	0.195
15	0.153	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[6]	clk1x:[R]	clk1x:[R]	-0.005	0.195
16	0.153	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[7]	clk1x:[R]	clk1x:[R]	-0.005	0.195
17	0.153	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_50_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[2]	clk1x:[R]	clk1x:[R]	-0.005	0.195
18	0.154	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D5	clk1x:[R]	clk1x:[R]	-0.002	0.239
19	0.154	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D3	clk1x:[R]	clk1x:[R]	-0.002	0.239
20	0.154	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/D5	clk1x:[R]	clk1x:[R]	-0.002	0.239
21	0.155	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D7	clk1x:[R]	clk1x:[R]	-0.002	0.240
22	0.157	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13]	clk1x:[R]	clk1x:[R]	-0.001	0.195
23	0.157	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_44_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[12]	clk1x:[R]	clk1x:[R]	-0.001	0.195
24	0.159	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_r_53_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/D5	clk1x:[R]	clk1x:[R]	-0.001	0.243
25	0.160	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_44_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/D1	clk1x:[R]	clk1x:[R]	-0.002	0.245

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.994	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.055	2.604
2	6.994	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.055	2.604
3	6.994	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.055	2.604
4	6.994	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.055	2.604
5	7.015	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.043	2.595
6	7.203	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.038	2.411
7	7.203	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.038	2.411
8	7.203	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_2_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.038	2.411
9	7.203	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_3_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.038	2.411
10	7.203	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.038	2.411
11	7.206	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.035	2.411
12	7.206	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.035	2.411
13	7.206	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.035	2.411
14	7.206	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.035	2.411
15	7.206	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.035	2.411
16	7.206	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET	clk1x:[R]	clk1x:[R]	10.000	0.035	2.411
17	7.227	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.031	2.394
18	7.227	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.031	2.394
19	7.227	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.031	2.394
20	7.249	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	-0.001	2.404
21	7.249	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	-0.001	2.404
22	7.249	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	-0.001	2.404
23	7.249	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	-0.001	2.404
24	7.253	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.019	2.380
25	7.253	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR	clk1x:[R]	clk1x:[R]	10.000	0.019	2.380

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.395	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.004	0.338
2	0.395	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.004	0.338
3	0.694	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLEAR	clkin:[R]	clkin:[R]	0.038	0.603
4	0.694	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0/CLEAR	clkin:[R]	clkin:[R]	0.038	0.603
5	0.694	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.038	0.603
6	0.694	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.038	0.603
7	0.698	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.603
8	0.698	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.603
9	0.698	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.603
10	0.698	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.603
11	0.698	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.603
12	0.702	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.046	0.603
13	0.702	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.046	0.603
14	0.702	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLEAR	clkin:[R]	clkin:[R]	0.046	0.603
15	0.802	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLEAR	clkin:[R]	clkin:[R]	0.046	0.703
16	0.913	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_5_s1/CLEAR	clkin:[R]	clkin:[R]	0.038	0.822
17	0.913	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLEAR	clkin:[R]	clkin:[R]	0.038	0.822
18	0.913	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLEAR	clkin:[R]	clkin:[R]	0.038	0.822
19	0.917	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.822
20	0.917	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.822
21	0.917	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.822
22	0.917	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_4_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.822
23	0.917	btn/out_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1/CLEAR	clkin:[R]	clkin:[R]	0.042	0.822
24	1.013	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR	clk1x:[R]	clk1x:[R]	0.002	0.958
25	1.013	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR	clk1x:[R]	clk1x:[R]	0.002	0.958

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.759	3.759	1.000	Low Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s
2	2.759	3.759	1.000	Low Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
3	2.759	3.759	1.000	Low Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s
4	2.759	3.759	1.000	Low Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
5	2.760	3.760	1.000	High Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s
6	2.760	3.760	1.000	High Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
7	2.760	3.760	1.000	High Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s
8	2.760	3.760	1.000	High Pulse Width	clk1x	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
9	2.765	3.765	1.000	Low Pulse Width	clk1x	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
10	2.765	3.765	1.000	Low Pulse Width	clk1x	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path2

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path3

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB71[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path4

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path5

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path6

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB79[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path7

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path8

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path9

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB71[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path10

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path11

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path12

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB77[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path13

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path14

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path15

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB69[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path16

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path17

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path18

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB79[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path19

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path20

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path21

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB73[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path22

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path23

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path24

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C64	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB77[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Path25

Path Summary:

Slack	2.004
Data Arrival Time	0.937
Data Required Time	2.941
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk	clk4x:[R]
Latch Clk	clk4x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk4x
0.000	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.441	0.441	tNET	RR	5	R38C92	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.937	0.496	tC2Q	RF	8	R38C92	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOB89[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					clk4x
2.500	0.000	tCL	RR	102	PLL_T	Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.941	0.441	tNET	RR	1	IOB89[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
2.941	0.000	tSu		1	IOB89[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.441, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.139
Data Arrival Time	0.876
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.701	0.701	tNET	RR	1	R9C81[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/CLK
0.842	0.141	tC2Q	RF	1	R9C81[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/Q
0.876	0.034	tNET	FF	1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path2

Path Summary:

Slack	0.139
Data Arrival Time	0.872
Data Required Time	0.733
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.697	0.697	tNET	RR	1	R9C78[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/CLK
0.838	0.141	tC2Q	RF	1	R9C78[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q
0.872	0.034	tNET	FF	1	BSRAM_R10[24]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R10[24]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.733	0.037	tHld		1	BSRAM_R10[24]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path3

Path Summary:

Slack	0.142
Data Arrival Time	0.963
Data Required Time	0.821
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R2C68[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0/CLK
0.868	0.144	tC2Q	RR	2	R2C68[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0/Q
0.963	0.095	tNET	RR	1	IOT68[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/D4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.725	0.725	tNET	RR	1	IOT68[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/PCLK
0.821	0.095	tHld		1	IOT68[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path4

Path Summary:

Slack	0.142
Data Arrival Time	0.955
Data Required Time	0.813
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.716	0.716	tNET	RR	1	R2C74[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0/CLK
0.860	0.144	tC2Q	RR	2	R2C74[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0/Q
0.955	0.095	tNET	RR	1	IOT74[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.717	0.717	tNET	RR	1	IOT74[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK
0.813	0.095	tHld		1	IOT74[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path5

Path Summary:

Slack	0.142
Data Arrival Time	0.959
Data Required Time	0.817
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.720	0.720	tNET	RR	1	R2C83[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0/CLK
0.864	0.144	tC2Q	RR	2	R2C83[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0/Q
0.959	0.095	tNET	RR	1	IOT83[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.722	0.722	tNET	RR	1	IOT83[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK
0.817	0.095	tHld		1	IOT83[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.722, 100.000%

Path6

Path Summary:

Slack	0.143
Data Arrival Time	0.964
Data Required Time	0.821
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R2C84[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0/CLK
0.868	0.144	tC2Q	RR	2	R2C84[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0/Q
0.964	0.096	tNET	RR	1	IOT83[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.725	0.725	tNET	RR	1	IOT83[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/PCLK
0.821	0.095	tHld		1	IOT83[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path7

Path Summary:

Slack	0.144
Data Arrival Time	0.873
Data Required Time	0.729
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.678	0.678	tNET	RR	1	R30C74[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0/CLK
0.819	0.141	tC2Q	RF	1	R30C74[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0/Q
0.873	0.054	tNET	FF	1	BSRAM_R28[23]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[23]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[23]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path8

Path Summary:

Slack	0.144
Data Arrival Time	0.873
Data Required Time	0.729
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_51_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.678	0.678	tNET	RR	1	R30C74[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_51_s0/CLK
0.819	0.141	tC2Q	RF	1	R30C74[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_51_s0/Q
0.873	0.054	tNET	FF	1	BSRAM_R28[23]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[23]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[23]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path9

Path Summary:

Slack	0.144
Data Arrival Time	0.881
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.686	0.686	tNET	RR	1	R30C80[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0/CLK
0.827	0.141	tC2Q	RF	1	R30C80[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0/Q
0.881	0.054	tNET	FF	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path10

Path Summary:

Slack	0.149
Data Arrival Time	0.886
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.691	0.691	tNET	RR	1	R29C81[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/CLK
0.832	0.141	tC2Q	RF	1	R29C81[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/Q
0.886	0.054	tNET	FF	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path11

Path Summary:

Slack	0.149
Data Arrival Time	0.886
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.691	0.691	tNET	RR	1	R29C81[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/CLK
0.832	0.141	tC2Q	RF	1	R29C81[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/Q
0.886	0.054	tNET	FF	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path12

Path Summary:

Slack	0.149
Data Arrival Time	0.886
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.691	0.691	tNET	RR	1	R29C81[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/CLK
0.832	0.141	tC2Q	RF	1	R29C81[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/Q
0.886	0.054	tNET	FF	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path13

Path Summary:

Slack	0.149
Data Arrival Time	0.882
Data Required Time	0.733
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.687	0.687	tNET	RR	1	R29C78[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/CLK
0.828	0.141	tC2Q	RF	1	R29C78[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q
0.882	0.054	tNET	FF	1	BSRAM_R28[24]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[24]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[24]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.687, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path14

Path Summary:

Slack	0.153
Data Arrival Time	0.890
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.695	0.695	tNET	RR	1	R29C80[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/CLK
0.836	0.141	tC2Q	RF	1	R29C80[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/Q
0.890	0.054	tNET	FF	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R28[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path15

Path Summary:

Slack	0.153
Data Arrival Time	0.886
Data Required Time	0.733
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.691	0.691	tNET	RR	1	R29C59[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/CLK
0.832	0.141	tC2Q	RF	1	R29C59[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q
0.886	0.054	tNET	FF	1	BSRAM_R28[18]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[18]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[18]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path16

Path Summary:

Slack	0.153
Data Arrival Time	0.890
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.695	0.695	tNET	RR	1	R11C80[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/CLK
0.836	0.141	tC2Q	RF	1	R11C80[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/Q
0.890	0.054	tNET	FF	1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path17

Path Summary:

Slack	0.153
Data Arrival Time	0.890
Data Required Time	0.737
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_50_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.695	0.695	tNET	RR	1	R11C80[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_50_s0/CLK
0.836	0.141	tC2Q	RF	1	R11C80[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_50_s0/Q
0.890	0.054	tNET	FF	1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA
0.737	0.037	tHld		1	BSRAM_R10[25]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path18

Path Summary:

Slack	0.154
Data Arrival Time	0.959
Data Required Time	0.805
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.720	0.720	tNET	RR	1	R2C83[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0/CLK
0.864	0.144	tC2Q	RR	2	R2C83[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_82_s0/Q
0.959	0.095	tNET	RR	1	IOT83[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.722	0.722	tNET	RR	1	IOT83[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK
0.805	0.083	tHld		1	IOT83[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.722, 100.000%

Path19

Path Summary:

Slack	0.154
Data Arrival Time	0.955
Data Required Time	0.800
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.716	0.716	tNET	RR	1	R2C74[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0/CLK
0.860	0.144	tC2Q	RR	2	R2C74[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_37_s0/Q
0.955	0.095	tNET	RR	1	IOT74[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.717	0.717	tNET	RR	1	IOT74[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK
0.800	0.083	tHld		1	IOT74[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path20

Path Summary:

Slack	0.154
Data Arrival Time	0.963
Data Required Time	0.808
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R2C68[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0/CLK
0.868	0.144	tC2Q	RR	2	R2C68[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_26_s0/Q
0.963	0.095	tNET	RR	1	IOT68[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/D5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.725	0.725	tNET	RR	1	IOT68[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/PCLK
0.808	0.083	tHld		1	IOT68[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path21

Path Summary:

Slack	0.155
Data Arrival Time	0.964
Data Required Time	0.808
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R2C84[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0/CLK
0.868	0.144	tC2Q	RR	2	R2C84[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_43_s0/Q
0.964	0.096	tNET	RR	1	IOT83[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.725	0.725	tNET	RR	1	IOT83[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/PCLK
0.808	0.083	tHld		1	IOT83[B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path22

Path Summary:

Slack	0.157
Data Arrival Time	0.890
Data Required Time	0.733
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.695	0.695	tNET	RR	1	R11C72[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/CLK
0.836	0.141	tC2Q	RF	1	R11C72[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q
0.890	0.054	tNET	FF	1	BSRAM_R10[22]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R10[22]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.733	0.037	tHld		1	BSRAM_R10[22]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path23

Path Summary:

Slack	0.157
Data Arrival Time	0.890
Data Required Time	0.733
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_44_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.695	0.695	tNET	RR	1	R11C72[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_44_s0/CLK
0.836	0.141	tC2Q	RF	1	R11C72[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_44_s0/Q
0.890	0.054	tNET	FF	1	BSRAM_R10[22]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R10[22]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.733	0.037	tHld		1	BSRAM_R10[22]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path24

Path Summary:

Slack	0.159
Data Arrival Time	0.941
Data Required Time	0.782
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_r_53_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.698	0.698	tNET	RR	1	R36C81[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_r_53_s0/CLK
0.842	0.144	tC2Q	RR	1	R36C81[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_r_53_s0/Q
0.941	0.099	tNET	RR	1	IOB81[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/D5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.699	0.699	tNET	RR	1	IOB81[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
0.782	0.083	tHld		1	IOB81[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.698, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.699, 100.000%

Path25

Path Summary:

Slack	0.160
Data Arrival Time	0.961
Data Required Time	0.800
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_44_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.716	0.716	tNET	RR	1	R2C70[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_44_s0/CLK
0.860	0.144	tC2Q	RR	2	R2C70[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_44_s0/Q
0.961	0.101	tNET	RR	1	IOT70[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.717	0.717	tNET	RR	1	IOT70[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/PCLK
0.800	0.083	tHld		1	IOT70[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.994
Data Arrival Time	4.554
Data Required Time	11.548
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.554	1.643	tNET	FF	1	R30C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.896	1.896	tNET	RR	1	R30C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLK
11.548	-0.347	tSu		1	R30C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew	-0.055
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 16.179%; route: 1.800, 69.131%; tC2Q: 0.382, 14.690%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.896, 100.000%

Path2

Path Summary:

Slack	6.994
Data Arrival Time	4.554
Data Required Time	11.548
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.554	1.643	tNET	FF	1	R30C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.896	1.896	tNET	RR	1	R30C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLK
11.548	-0.347	tSu		1	R30C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew	-0.055
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 16.179%; route: 1.800, 69.131%; tC2Q: 0.382, 14.690%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.896, 100.000%

Path3

Path Summary:

Slack	6.994
Data Arrival Time	4.554
Data Required Time	11.548
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.554	1.643	tNET	FF	1	R30C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.896	1.896	tNET	RR	1	R30C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLK
11.548	-0.347	tSu		1	R30C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	-0.055
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 16.179%; route: 1.800, 69.131%; tC2Q: 0.382, 14.690%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.896, 100.000%

Path4

Path Summary:

Slack	6.994
Data Arrival Time	4.554
Data Required Time	11.548
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.554	1.643	tNET	FF	1	R30C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.896	1.896	tNET	RR	1	R30C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0/CLK
11.548	-0.347	tSu		1	R30C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew	-0.055
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 16.179%; route: 1.800, 69.131%; tC2Q: 0.382, 14.690%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.896, 100.000%

Path5

Path Summary:

Slack	7.015
Data Arrival Time	4.546
Data Required Time	11.560
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.546	1.634	tNET	FF	1	R14C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.908	1.908	tNET	RR	1	R14C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK
11.560	-0.347	tSu		1	R14C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew	-0.043
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 16.233%; route: 1.791, 69.027%; tC2Q: 0.382, 14.740%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.908, 100.000%

Path6

Path Summary:

Slack	7.203
Data Arrival Time	4.362
Data Required Time	11.565
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R29C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.913	1.912	tNET	RR	1	R29C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLK
11.565	-0.347	tSu		1	R29C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew	-0.038
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.912, 100.000%

Path7

Path Summary:

Slack	7.203
Data Arrival Time	4.362
Data Required Time	11.565
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R29C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.913	1.912	tNET	RR	1	R29C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLK
11.565	-0.347	tSu		1	R29C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew	-0.038
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.912, 100.000%

Path8

Path Summary:

Slack	7.203
Data Arrival Time	4.362
Data Required Time	11.565
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_2_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R29C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.913	1.912	tNET	RR	1	R29C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_2_s0/CLK
11.565	-0.347	tSu		1	R29C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew	-0.038
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.912, 100.000%

Path9

Path Summary:

Slack	7.203
Data Arrival Time	4.362
Data Required Time	11.565
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_3_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R29C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.913	1.912	tNET	RR	1	R29C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_3_s0/CLK
11.565	-0.347	tSu		1	R29C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew	-0.038
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.912, 100.000%

Path10

Path Summary:

Slack	7.203
Data Arrival Time	4.362
Data Required Time	11.565
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R29C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.913	1.912	tNET	RR	1	R29C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0/CLK
11.565	-0.347	tSu		1	R29C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew	-0.038
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.912, 100.000%

Path11

Path Summary:

Slack	7.206
Data Arrival Time	4.362
Data Required Time	11.568
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R16C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.916	1.916	tNET	RR	1	R16C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK
11.568	-0.347	tSu		1	R16C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.916, 100.000%

Path12

Path Summary:

Slack	7.206
Data Arrival Time	4.362
Data Required Time	11.568
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R16C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.916	1.916	tNET	RR	1	R16C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK
11.568	-0.347	tSu		1	R16C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.916, 100.000%

Path13

Path Summary:

Slack	7.206
Data Arrival Time	4.362
Data Required Time	11.568
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R16C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.916	1.916	tNET	RR	1	R16C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK
11.568	-0.347	tSu		1	R16C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.916, 100.000%

Path14

Path Summary:

Slack	7.206
Data Arrival Time	4.362
Data Required Time	11.568
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R16C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.916	1.916	tNET	RR	1	R16C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK
11.568	-0.347	tSu		1	R16C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.916, 100.000%

Path15

Path Summary:

Slack	7.206
Data Arrival Time	4.362
Data Required Time	11.568
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R16C70[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.916	1.916	tNET	RR	1	R16C70[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLK
11.568	-0.347	tSu		1	R16C70[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.916, 100.000%

Path16

Path Summary:

Slack	7.206
Data Arrival Time	4.362
Data Required Time	11.568
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.362	1.450	tNET	FF	1	R16C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.916	1.916	tNET	RR	1	R16C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/CLK
11.568	-0.347	tSu		1	R16C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.470%; route: 1.607, 66.667%; tC2Q: 0.382, 15.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.916, 100.000%

Path17

Path Summary:

Slack	7.227
Data Arrival Time	4.344
Data Required Time	11.572
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.344	1.432	tNET	FF	1	R18C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.919	1.919	tNET	RR	1	R18C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLK
11.572	-0.347	tSu		1	R18C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew	-0.031
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.598%; route: 1.590, 66.423%; tC2Q: 0.382, 15.979%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.919, 100.000%

Path18

Path Summary:

Slack	7.227
Data Arrival Time	4.344
Data Required Time	11.572
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.344	1.432	tNET	FF	1	R18C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.919	1.919	tNET	RR	1	R18C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK
11.572	-0.347	tSu		1	R18C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	-0.031
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.598%; route: 1.590, 66.423%; tC2Q: 0.382, 15.979%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.919, 100.000%

Path19

Path Summary:

Slack	7.227
Data Arrival Time	4.344
Data Required Time	11.572
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.344	1.432	tNET	FF	1	R18C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.919	1.919	tNET	RR	1	R18C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLK
11.572	-0.347	tSu		1	R18C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew	-0.031
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.598%; route: 1.590, 66.423%; tC2Q: 0.382, 15.979%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.919, 100.000%

Path20

Path Summary:

Slack	7.249
Data Arrival Time	4.354
Data Required Time	11.604
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.354	1.442	tNET	FF	1	R21C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.951	1.951	tNET	RR	1	R21C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLK
11.604	-0.347	tSu		1	R21C70[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.525%; route: 1.600, 66.563%; tC2Q: 0.382, 15.913%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path21

Path Summary:

Slack	7.249
Data Arrival Time	4.354
Data Required Time	11.604
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.354	1.442	tNET	FF	1	R21C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.951	1.951	tNET	RR	1	R21C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLK
11.604	-0.347	tSu		1	R21C70[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.525%; route: 1.600, 66.563%; tC2Q: 0.382, 15.913%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path22

Path Summary:

Slack	7.249
Data Arrival Time	4.354
Data Required Time	11.604
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.354	1.442	tNET	FF	1	R21C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.951	1.951	tNET	RR	1	R21C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLK
11.604	-0.347	tSu		1	R21C70[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.525%; route: 1.600, 66.563%; tC2Q: 0.382, 15.913%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path23

Path Summary:

Slack	7.249
Data Arrival Time	4.354
Data Required Time	11.604
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.354	1.442	tNET	FF	1	R21C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.951	1.951	tNET	RR	1	R21C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLK
11.604	-0.347	tSu		1	R21C70[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.525%; route: 1.600, 66.563%; tC2Q: 0.382, 15.913%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path24

Path Summary:

Slack	7.253
Data Arrival Time	4.331
Data Required Time	11.584
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.331	1.419	tNET	FF	1	R29C68[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.931	1.931	tNET	RR	1	R29C68[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLK
11.584	-0.347	tSu		1	R29C68[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.700%; route: 1.576, 66.229%; tC2Q: 0.382, 16.071%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.931, 100.000%

Path25

Path Summary:

Slack	7.253
Data Arrival Time	4.331
Data Required Time	11.584
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.951	1.951	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.333	0.382	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.491	0.157	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.912	0.421	tINS	RF	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.331	1.419	tNET	FF	1	R29C68[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1x
10.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.931	1.931	tNET	RR	1	R29C68[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0/CLK
11.584	-0.347	tSu		1	R29C68[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 0.421, 17.700%; route: 1.576, 66.229%; tC2Q: 0.382, 16.071%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.931, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.395
Data Arrival Time	1.740
Data Required Time	1.345
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
1.740	0.194	tNET	RR	1	R2C58[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.398	0.723	tNET	RR	1	R2C58[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/CLK
1.345	-0.053	tHld		1	R2C58[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path2

Path Summary:

Slack	0.395
Data Arrival Time	1.740
Data Required Time	1.345
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
1.740	0.194	tNET	RR	1	R2C58[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.398	0.723	tNET	RR	1	R2C58[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_1_s0/CLK
1.345	-0.053	tHld		1	R2C58[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_1_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path3

Path Summary:

Slack	0.694
Data Arrival Time	2.005
Data Required Time	1.312
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.365	0.689	tNET	RR	1	R12C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK
1.312	-0.053	tHld		1	R12C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1

Path Statistics:

Clock Skew	-0.038
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path4

Path Summary:

Slack	0.694
Data Arrival Time	2.005
Data Required Time	1.312
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C61[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.365	0.689	tNET	RR	1	R12C61[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0/CLK
1.312	-0.053	tHld		1	R12C61[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0

Path Statistics:

Clock Skew	-0.038
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path5

Path Summary:

Slack	0.694
Data Arrival Time	2.005
Data Required Time	1.312
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C61[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.365	0.689	tNET	RR	1	R12C61[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0/CLK
1.312	-0.053	tHld		1	R12C61[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0

Path Statistics:

Clock Skew	-0.038
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path6

Path Summary:

Slack	0.694
Data Arrival Time	2.005
Data Required Time	1.312
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C61[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.365	0.689	tNET	RR	1	R12C61[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLK
1.312	-0.053	tHld		1	R12C61[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0

Path Statistics:

Clock Skew	-0.038
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path7

Path Summary:

Slack	0.698
Data Arrival Time	2.005
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C60[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C60[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK
1.308	-0.053	tHld		1	R12C60[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path8

Path Summary:

Slack	0.698
Data Arrival Time	2.005
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C60[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C60[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLK
1.308	-0.053	tHld		1	R12C60[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path9

Path Summary:

Slack	0.698
Data Arrival Time	2.005
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C60[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C60[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/CLK
1.308	-0.053	tHld		1	R12C60[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path10

Path Summary:

Slack	0.698
Data Arrival Time	2.005
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C60[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C60[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLK
1.308	-0.053	tHld		1	R12C60[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path11

Path Summary:

Slack	0.698
Data Arrival Time	2.005
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C60[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C60[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1/CLK
1.308	-0.053	tHld		1	R12C60[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path12

Path Summary:

Slack	0.702
Data Arrival Time	2.005
Data Required Time	1.303
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C59[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.356	0.681	tNET	RR	1	R12C59[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0/CLK
1.303	-0.053	tHld		1	R12C59[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0

Path Statistics:

Clock Skew	-0.046
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%

Path13

Path Summary:

Slack	0.702
Data Arrival Time	2.005
Data Required Time	1.303
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C59[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.356	0.681	tNET	RR	1	R12C59[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0/CLK
1.303	-0.053	tHld		1	R12C59[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0

Path Statistics:

Clock Skew	-0.046
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%

Path14

Path Summary:

Slack	0.702
Data Arrival Time	2.005
Data Required Time	1.303
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.005	0.459	tNET	RR	1	R12C59[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.356	0.681	tNET	RR	1	R12C59[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK
1.303	-0.053	tHld		1	R12C59[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0

Path Statistics:

Clock Skew	-0.046
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.459, 76.119%; tC2Q: 0.144, 23.881%
Required Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%

Path15

Path Summary:

Slack	0.802
Data Arrival Time	2.105
Data Required Time	1.303
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.105	0.559	tNET	RR	1	R12C63[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.356	0.681	tNET	RR	1	R12C63[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK
1.303	-0.053	tHld		1	R12C63[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3

Path Statistics:

Clock Skew	-0.046
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.559, 79.516%; tC2Q: 0.144, 20.484%
Required Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%

Path16

Path Summary:

Slack	0.913
Data Arrival Time	2.224
Data Required Time	1.312
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_5_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C65[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.365	0.689	tNET	RR	1	R12C65[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_5_s1/CLK
1.312	-0.053	tHld		1	R12C65[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_5_s1

Path Statistics:

Clock Skew	-0.038
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path17

Path Summary:

Slack	0.913
Data Arrival Time	2.224
Data Required Time	1.312
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C65[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.365	0.689	tNET	RR	1	R12C65[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLK
1.312	-0.053	tHld		1	R12C65[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1

Path Statistics:

Clock Skew	-0.038
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path18

Path Summary:

Slack	0.913
Data Arrival Time	2.224
Data Required Time	1.312
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C65[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.365	0.689	tNET	RR	1	R12C65[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLK
1.312	-0.053	tHld		1	R12C65[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1

Path Statistics:

Clock Skew	-0.038
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path19

Path Summary:

Slack	0.917
Data Arrival Time	2.224
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C64[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C64[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/CLK
1.308	-0.053	tHld		1	R12C64[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path20

Path Summary:

Slack	0.917
Data Arrival Time	2.224
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C64[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C64[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1/CLK
1.308	-0.053	tHld		1	R12C64[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path21

Path Summary:

Slack	0.917
Data Arrival Time	2.224
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C64[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C64[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1/CLK
1.308	-0.053	tHld		1	R12C64[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path22

Path Summary:

Slack	0.917
Data Arrival Time	2.224
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_4_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C64[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C64[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_4_s1/CLK
1.308	-0.053	tHld		1	R12C64[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_4_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path23

Path Summary:

Slack	0.917
Data Arrival Time	2.224
Data Required Time	1.308
From	btn/out_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.402	0.727	tNET	RR	1	R2C61[1][A]	btn/out_s0/CLK
1.546	0.144	tC2Q	RR	42	R2C61[1][A]	btn/out_s0/Q
2.224	0.678	tNET	RR	1	R12C64[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_g_ibuf/I
0.675	0.675	tINS	RR	90	IOB29[A]	clk_g_ibuf/O
1.361	0.685	tNET	RR	1	R12C64[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1/CLK
1.308	-0.053	tHld		1	R12C64[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1

Path Statistics:

Clock Skew	-0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.678, 82.482%; tC2Q: 0.144, 17.518%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path24

Path Summary:

Slack	1.013
Data Arrival Time	1.669
Data Required Time	0.656
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.711	0.711	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.855	0.144	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.948	0.093	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.218	0.270	tINS	RR	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.669	0.451	tNET	RR	1	R6C70[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.709	0.709	tNET	RR	1	R6C70[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLK
0.656	-0.053	tHld		1	R6C70[3][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay	cell: 0.270, 28.184%; route: 0.544, 56.785%; tC2Q: 0.144, 15.031%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path25

Path Summary:

Slack	1.013
Data Arrival Time	1.669
Data Required Time	0.656
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk	clk1x:[R]
Latch Clk	clk1x:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.711	0.711	tNET	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.855	0.144	tC2Q	RR	1	R7C61[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.948	0.093	tNET	RR	1	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.218	0.270	tINS	RR	80	R7C62[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.669	0.451	tNET	RR	1	R6C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1x
0.000	0.000	tCL	RR	6242	RIGHTSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.709	0.709	tNET	RR	1	R6C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLK
0.656	-0.053	tHld		1	R6C70[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay	cell: 0.270, 28.184%; route: 0.544, 56.785%; tC2Q: 0.144, 15.031%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.759
Actual Width:	3.759
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.944	1.944	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1x
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.703	0.704	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

MPW2

MPW Summary:

Slack:	2.759
Actual Width:	3.759
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.944	1.944	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1x
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.703	0.704	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKB

MPW3

MPW Summary:

Slack:	2.759
Actual Width:	3.759
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.944	1.944	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1x
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.703	0.704	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA

MPW4

MPW Summary:

Slack:	2.759
Actual Width:	3.759
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.944	1.944	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1x
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.703	0.704	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA

MPW5

MPW Summary:

Slack:	2.760
Actual Width:	3.760
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk1x
0.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.948	1.948	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.708	0.708	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

MPW6

MPW Summary:

Slack:	2.760
Actual Width:	3.760
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk1x
0.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.948	1.948	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.708	0.708	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKB

MPW7

MPW Summary:

Slack:	2.760
Actual Width:	3.760
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk1x
0.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.948	1.948	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.708	0.708	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA

MPW8

MPW Summary:

Slack:	2.760
Actual Width:	3.760
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk1x
0.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.948	1.948	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.708	0.708	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA

MPW9

MPW Summary:

Slack:	2.765
Actual Width:	3.765
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.935	1.935	tNET	FF	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1x
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.700	0.700	tNET	RR	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

MPW10

MPW Summary:

Slack:	2.765
Actual Width:	3.765
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1x
Objects:	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk1x
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.935	1.935	tNET	FF	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1x
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.700	0.700	tNET	RR	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
6242	clk_x1	2.974	1.991
343	eye_calib_start_rr	5.960	3.142
335	ddr_init_internal_rr	6.045	3.272
292	dqsts1	5.946	3.100
291	dqs_reg	6.017	3.081
128	raddr[2]	3.316	2.128
108	n258_6	5.621	3.145
102	memory_clk	2.004	0.441
90	clk_g_d	16.311	2.123
80	if_wrreset_Z	6.994	1.688

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R29C63	56.94%
R33C41	55.56%
R11C65	51.39%
R34C40	50.00%
R12C53	50.00%
R27C66	48.61%
R28C62	48.61%
R29C62	48.61%
R12C62	48.61%
R26C66	48.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk4x -period 2.5 -waveform {0 1.25} [get_pins {Gowin_PLL_inst/PLLA_inst/CLKOUT2}]
TC_CLOCK	Actived	create_clock -name clk1x -period 10 -waveform {0 5} [get_pins {u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT}]
TC_CLOCK	Actived	create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk_g}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {clk4x}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk4x}] -group [get_clocks {clk1x}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {clk1x}]