Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\button.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_memory_interface\ddr3_memory_interface.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\ddrtest.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\pll_mDRP_intf.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a25k\project\src\top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW5A-LV25UG324C1/I0 |
| Device | GW5A-25 |
| Device Version | B |
| Created Time | Fri Feb 28 16:29:40 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 585.996MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.181s, Peak memory usage = 585.996MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.19s, Peak memory usage = 585.996MB Optimizing Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.199s, Peak memory usage = 585.996MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 585.996MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 585.996MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 585.996MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 585.996MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.378s, Peak memory usage = 585.996MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 585.996MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 585.996MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 585.996MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.348s, Peak memory usage = 585.996MB Generate output files: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.647s, Peak memory usage = 585.996MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 585.996MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 76 |
| I/O Buf | 71 |
| IBUF | 2 |
| OBUF | 28 |
| TBUF | 4 |
| IOBUF | 32 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 4 |
| Register | 6166 |
| DFFSE | 2 |
| DFFRE | 286 |
| DFFPE | 75 |
| DFFCE | 5803 |
| LUT | 3504 |
| LUT2 | 484 |
| LUT3 | 1551 |
| LUT4 | 1469 |
| ALU | 448 |
| ALU | 448 |
| INV | 24 |
| INV | 24 |
| IOLOGIC | 128 |
| IDES8_MEM | 32 |
| OSER8 | 24 |
| OSER8_MEM | 40 |
| IODELAY | 32 |
| BSRAM | 16 |
| SDPB | 8 |
| SDPX9B | 8 |
| CLOCK | 7 |
| CLKDIV | 1 |
| DQS | 4 |
| DDRDLL | 1 |
| PLLA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3976(3528 LUT, 448 ALU) / 23040 | 18% |
| Register | 6166 / 23685 | 27% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 6166 / 23685 | 27% |
| BSRAM | 16 / 56 | 29% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_g | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_g_ibuf/I | ||
| 2 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk_g_ibuf/I | clk_g | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 3 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_g | 50.000(MHz) | 191.113(MHz) | 6 | TOP |
| 2 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1164.144(MHz) | 1 | TOP |
| 3 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 173.160(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.034 |
| Data Arrival Time | 2.396 |
| Data Required Time | 1.363 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 6210 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 10 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0 |
| 2.021 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.531 | 0.281 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 1.882 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.847 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.363 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.106 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | -1.034 |
| Data Arrival Time | 2.396 |
| Data Required Time | 1.363 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 6210 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 10 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0 |
| 2.021 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.531 | 0.281 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 1.882 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.847 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.363 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.106 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | -1.034 |
| Data Arrival Time | 2.396 |
| Data Required Time | 1.363 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 6210 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 10 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 2.021 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.531 | 0.281 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 1.882 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.847 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.363 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.106 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | -1.034 |
| Data Arrival Time | 2.396 |
| Data Required Time | 1.363 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 6210 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 10 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 2.021 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 2.396 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.531 | 0.281 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 1.882 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.847 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.363 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.106 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 1.626 |
| Data Arrival Time | 1.495 |
| Data Required Time | 3.121 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 6210 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 8 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/CALIB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 2.781 | 0.281 | tCL | RR | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 3.156 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
| 3.121 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem | ||
| 3.121 | 0.000 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Clock Skew: | -0.081 |
| Setup Relationship: | 2.500 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |