Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Fri Feb 28 16:50:32 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR3_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.594MB Running netlist conversion: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 181.594MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.54s, Peak memory usage = 181.594MB Optimizing Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.367s, Peak memory usage = 181.594MB Optimizing Phase 2: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.901s, Peak memory usage = 181.594MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.663s, Peak memory usage = 181.594MB Inferring Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.214s, Peak memory usage = 181.594MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 181.594MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 181.594MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.595s, Peak memory usage = 181.594MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.235s, Peak memory usage = 181.594MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 181.594MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 189.434MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.729s, Peak memory usage = 189.434MB Generate output files: CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.632s, Peak memory usage = 208.727MB |
| Total Time and Memory Usage | CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 208.727MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 665 |
| I/O Buf | 657 |
| IBUF | 326 |
| OBUF | 290 |
| TBUF | 4 |
| IOBUF | 32 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 4 |
| Register | 5413 |
| DFFSE | 1 |
| DFFRE | 249 |
| DFFPE | 74 |
| DFFCE | 5089 |
| LUT | 3066 |
| LUT2 | 429 |
| LUT3 | 1453 |
| LUT4 | 1184 |
| ALU | 189 |
| ALU | 189 |
| INV | 24 |
| INV | 24 |
| IOLOGIC | 128 |
| IDES8_MEM | 32 |
| OSER8 | 24 |
| OSER8_MEM | 40 |
| IODELAY | 32 |
| BSRAM | 16 |
| SDPB | 8 |
| SDPX9B | 8 |
| CLOCK | 6 |
| CLKDIV | 1 |
| DQS | 4 |
| DDRDLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3279(3090 LUT, 189 ALU) / 138240 | 3% |
| Register | 5413 / 139140 | 4% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 5413 / 139140 | 4% |
| BSRAM | 16 / 340 | 5% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | memory_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| 2 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.000(MHz) | 1115.449(MHz) | 1 | TOP |
| 2 | clk | 100.000(MHz) | 149.477(MHz) | 7 | TOP |
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 161.225(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.287 |
| Data Arrival Time | 2.579 |
| Data Required Time | 4.866 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.381 | 0.381 | tCL | RR | 5506 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.793 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 1.176 | 0.382 | tC2Q | RR | 12 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.588 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 2.167 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 2.579 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.408 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 2.287 |
| Data Arrival Time | 2.579 |
| Data Required Time | 4.866 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.381 | 0.381 | tCL | RR | 5506 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.793 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 1.176 | 0.382 | tC2Q | RR | 10 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.588 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 2.167 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 2.579 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.408 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 2.287 |
| Data Arrival Time | 2.579 |
| Data Required Time | 4.866 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.381 | 0.381 | tCL | RR | 5506 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.793 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK |
| 1.176 | 0.382 | tC2Q | RR | 10 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q |
| 1.588 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0 |
| 2.167 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F |
| 2.579 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.408 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 2.287 |
| Data Arrival Time | 2.579 |
| Data Required Time | 4.866 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.381 | 0.381 | tCL | RR | 5506 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.793 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK |
| 1.176 | 0.382 | tC2Q | RR | 10 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q |
| 1.588 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0 |
| 2.167 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F |
| 2.579 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.408 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.310 |
| Data Arrival Time | 7.039 |
| Data Required Time | 10.349 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3 |
| To | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q |
| 1.207 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
| 2.199 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/I1 |
| 2.766 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/F |
| 3.179 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/I1 |
| 3.746 | 0.567 | tINS | RR | 4 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/F |
| 4.159 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n46_s3/I1 |
| 4.726 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n46_s3/F |
| 5.139 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s2/I2 |
| 5.646 | 0.507 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s2/F |
| 6.059 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s3/I1 |
| 6.626 | 0.567 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s3/F |
| 7.039 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLK |
| 10.349 | -0.064 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.356, 50.651%; route: 2.887, 43.577%; tC2Q: 0.382, 5.772% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |