Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\impl\gwsynthesis\ddr3_1v4_hs.vg |
| Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_1v4_hs.cst |
| Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_1v4_hs.sdc |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Fri Feb 28 16:51:51 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.855V 0C ES |
| Hold Delay Model | Fast 0.945V 85C ES |
| Numbers of Paths Analyzed | 14737 |
| Numbers of Endpoints Analyzed | 21490 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk400 | Base | 2.500 | 400.000 | 0.000 | 1.250 | memory_clk | ||
| 2 | clk100 | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk | ||
| 3 | sysclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk400 | 400.000(MHz) | 2016.129(MHz) | 1 | TOP |
| 2 | clk100 | 100.000(MHz) | 203.471(MHz) | 7 | TOP |
| 3 | sysclk | 100.000(MHz) | 120.400(MHz) | 6 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| clk400 | Setup | 0.000 | 0 |
| clk400 | Hold | 0.000 | 0 |
| clk100 | Setup | 0.000 | 0 |
| clk100 | Hold | 0.000 | 0 |
| sysclk | Setup | 0.000 | 0 |
| sysclk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.694 | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate_13_s7/Q | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_empty_s1/CE | sysclk:[R] | sysclk:[R] | 10.000 | -0.043 | 8.038 |
| 2 | 1.810 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TX1 | sysclk:[R] | sysclk:[R] | 10.000 | 0.109 | 7.818 |
| 3 | 1.812 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX1 | sysclk:[R] | sysclk:[R] | 10.000 | 0.107 | 7.818 |
| 4 | 1.956 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TX3 | sysclk:[R] | sysclk:[R] | 10.000 | 0.109 | 7.671 |
| 5 | 1.956 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TX2 | sysclk:[R] | sysclk:[R] | 10.000 | 0.109 | 7.671 |
| 6 | 1.958 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX3 | sysclk:[R] | sysclk:[R] | 10.000 | 0.107 | 7.671 |
| 7 | 1.958 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX2 | sysclk:[R] | sysclk:[R] | 10.000 | 0.107 | 7.671 |
| 8 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 9 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 10 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 11 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 12 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 13 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 14 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 15 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 16 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 17 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 18 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 19 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 20 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 21 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 22 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 23 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 24 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
| 25 | 2.004 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0] | clk400:[R] | clk400:[R] | 2.500 | 0.000 | 0.496 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.167 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[2] | sysclk:[R] | sysclk:[R] | 0.000 | 0.001 | 0.203 |
| 2 | 0.197 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_15_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[15] | sysclk:[R] | sysclk:[R] | 0.000 | -0.001 | 0.235 |
| 3 | 0.202 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_3_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/ADA[8] | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 0.244 |
| 4 | 0.202 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_1_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/ADA[6] | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 0.244 |
| 5 | 0.207 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_253_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[1] | sysclk:[R] | sysclk:[R] | 0.000 | -0.014 | 0.258 |
| 6 | 0.220 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[14] | sysclk:[R] | sysclk:[R] | 0.000 | -0.001 | 0.258 |
| 7 | 0.228 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[14] | sysclk:[R] | sysclk:[R] | 0.000 | 0.014 | 0.251 |
| 8 | 0.228 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/ADA[7] | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 0.270 |
| 9 | 0.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[4] | sysclk:[R] | sysclk:[R] | 0.000 | 0.001 | 0.266 |
| 10 | 0.240 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_137_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/DI[11] | sysclk:[R] | sysclk:[R] | 0.000 | -0.009 | 0.286 |
| 11 | 0.240 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_128_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/DI[2] | sysclk:[R] | sysclk:[R] | 0.000 | -0.009 | 0.286 |
| 12 | 0.244 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_203_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_5_s/DI[5] | sysclk:[R] | sysclk:[R] | 0.000 | -0.010 | 0.291 |
| 13 | 0.244 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_143_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/DI[17] | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 0.286 |
| 14 | 0.246 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[1] | sysclk:[R] | sysclk:[R] | 0.000 | -0.001 | 0.284 |
| 15 | 0.263 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[4] | sysclk:[R] | sysclk:[R] | 0.000 | -0.009 | 0.309 |
| 16 | 0.263 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3] | sysclk:[R] | sysclk:[R] | 0.000 | -0.009 | 0.309 |
| 17 | 0.272 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_0_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/ADA[5] | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 0.314 |
| 18 | 0.273 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_227_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[11] | sysclk:[R] | sysclk:[R] | 0.000 | -0.014 | 0.324 |
| 19 | 0.275 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/Q | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/D | clk100:[R] | clk100:[R] | 0.000 | 0.000 | 0.300 |
| 20 | 0.275 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3/D | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 0.300 |
| 21 | 0.275 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3/D | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 0.300 |
| 22 | 0.275 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3/D | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 0.300 |
| 23 | 0.275 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4/D | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 0.300 |
| 24 | 0.275 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3/D | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 0.300 |
| 25 | 0.275 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3/D | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 0.300 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 5.439 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.012 | 4.226 |
| 2 | 5.439 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.012 | 4.226 |
| 3 | 5.439 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.012 | 4.226 |
| 4 | 5.439 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.012 | 4.226 |
| 5 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.019 | 4.153 |
| 6 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.019 | 4.153 |
| 7 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.019 | 4.153 |
| 8 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.019 | 4.153 |
| 9 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.019 | 4.153 |
| 10 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.019 | 4.153 |
| 11 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.019 | 4.153 |
| 12 | 5.518 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.026 | 4.161 |
| 13 | 5.526 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.009 | 4.136 |
| 14 | 5.671 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.031 | 4.013 |
| 15 | 5.743 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.041 | 3.951 |
| 16 | 5.756 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.009 | 3.906 |
| 17 | 5.756 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.009 | 3.906 |
| 18 | 5.756 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.009 | 3.906 |
| 19 | 5.756 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.009 | 3.906 |
| 20 | 5.803 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.015 | 3.865 |
| 21 | 5.803 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.015 | 3.865 |
| 22 | 5.803 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.015 | 3.865 |
| 23 | 5.803 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.015 | 3.865 |
| 24 | 5.803 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.015 | 3.865 |
| 25 | 5.803 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.015 | 3.865 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.812 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.026 | 0.785 |
| 2 | 0.812 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.026 | 0.785 |
| 3 | 0.812 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.026 | 0.785 |
| 4 | 0.904 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.030 | 0.881 |
| 5 | 1.668 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.007 | 1.622 |
| 6 | 1.668 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.007 | 1.622 |
| 7 | 1.668 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.007 | 1.622 |
| 8 | 1.668 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.007 | 1.622 |
| 9 | 1.668 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.007 | 1.622 |
| 10 | 1.677 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.023 | 1.647 |
| 11 | 1.677 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.023 | 1.647 |
| 12 | 1.677 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.023 | 1.647 |
| 13 | 1.677 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.023 | 1.647 |
| 14 | 1.685 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.019 | 1.651 |
| 15 | 1.685 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.019 | 1.651 |
| 16 | 1.685 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.019 | 1.651 |
| 17 | 1.685 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.015 | 1.647 |
| 18 | 1.685 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.024 | 1.656 |
| 19 | 1.732 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.026 | 1.705 |
| 20 | 1.751 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.012 | 1.710 |
| 21 | 1.760 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | 0.003 | 1.704 |
| 22 | 1.760 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | 0.003 | 1.704 |
| 23 | 1.760 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET | sysclk:[R] | sysclk:[R] | 0.000 | 0.003 | 1.704 |
| 24 | 1.760 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | 0.003 | 1.704 |
| 25 | 1.772 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.003 | 1.722 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 1.797 | 2.797 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s |
| 2 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
| 3 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s |
| 4 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
| 5 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s |
| 6 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
| 7 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
| 8 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
| 9 | 1.803 | 2.803 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
| 10 | 1.808 | 2.808 | 1.000 | High Pulse Width | sysclk | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.694 |
| Data Arrival Time | 11.928 |
| Data Required Time | 13.623 |
| From | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate_13_s7 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_empty_s1 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.891 | 3.891 | tNET | RR | 1 | R53C112[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate_13_s7/CLK |
| 4.273 | 0.382 | tC2Q | RR | 4 | R53C112[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate_13_s7/Q |
| 5.117 | 0.844 | tNET | RR | 1 | R50C109[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n223_s7/I3 |
| 5.684 | 0.567 | tINS | RR | 12 | R50C109[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n223_s7/F |
| 6.533 | 0.849 | tNET | RR | 1 | R52C112[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n223_s17/I3 |
| 7.101 | 0.567 | tINS | RR | 4 | R52C112[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n223_s17/F |
| 7.489 | 0.389 | tNET | RR | 1 | R50C112[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n223_s1/I0 |
| 7.997 | 0.507 | tINS | RR | 19 | R50C112[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n223_s1/F |
| 9.444 | 1.448 | tNET | RR | 1 | R53C117[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/cmd_accept_Z_s1/I1 |
| 10.023 | 0.579 | tINS | RR | 4 | R53C117[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/cmd_accept_Z_s1/F |
| 10.813 | 0.790 | tNET | RR | 1 | R57C117[3][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_empty_s3/I1 |
| 11.104 | 0.291 | tINS | RR | 1 | R57C117[3][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_empty_s3/F |
| 11.928 | 0.824 | tNET | RR | 1 | R57C117[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_empty_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.934 | 3.934 | tNET | RR | 1 | R57C117[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_empty_s1/CLK |
| 13.623 | -0.311 | tSu | 1 | R57C117[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_empty_s1 |
Path Statistics:
| Clock Skew | 0.043 |
| Setup Relationship | 10.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.891, 100.000% |
| Arrival Data Path Delay | cell: 2.513, 31.260%; route: 5.143, 63.981%; tC2Q: 0.382, 4.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.934, 100.000% |
Path2
Path Summary:
| Slack | 1.810 |
| Data Arrival Time | 11.766 |
| Data Required Time | 13.576 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.949 | 3.949 | tNET | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/CLK |
| 4.331 | 0.382 | tC2Q | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q |
| 4.483 | 0.151 | tNET | RR | 1 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
| 4.774 | 0.291 | tINS | RR | 108 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
| 11.766 | 6.993 | tNET | RR | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TX1 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.839 | 3.839 | tNET | RR | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK |
| 13.576 | -0.263 | tSu | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem |
Path Statistics:
| Clock Skew | -0.109 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.949, 100.000% |
| Arrival Data Path Delay | cell: 0.291, 3.726%; route: 7.144, 91.382%; tC2Q: 0.382, 4.893% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.839, 100.000% |
Path3
Path Summary:
| Slack | 1.812 |
| Data Arrival Time | 11.766 |
| Data Required Time | 13.578 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.949 | 3.949 | tNET | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/CLK |
| 4.331 | 0.382 | tC2Q | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q |
| 4.483 | 0.151 | tNET | RR | 1 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
| 4.774 | 0.291 | tINS | RR | 108 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
| 11.766 | 6.993 | tNET | RR | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX1 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.841 | 3.841 | tNET | RR | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK |
| 13.578 | -0.263 | tSu | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Path Statistics:
| Clock Skew | -0.107 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.949, 100.000% |
| Arrival Data Path Delay | cell: 0.291, 3.726%; route: 7.144, 91.382%; tC2Q: 0.382, 4.893% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.841, 100.000% |
Path4
Path Summary:
| Slack | 1.956 |
| Data Arrival Time | 11.620 |
| Data Required Time | 13.576 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.949 | 3.949 | tNET | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/CLK |
| 4.331 | 0.382 | tC2Q | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q |
| 4.483 | 0.151 | tNET | RR | 1 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
| 4.801 | 0.319 | tINS | RF | 108 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
| 11.620 | 6.819 | tNET | FF | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TX3 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.839 | 3.839 | tNET | RR | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK |
| 13.576 | -0.263 | tSu | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem |
Path Statistics:
| Clock Skew | -0.109 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.949, 100.000% |
| Arrival Data Path Delay | cell: 0.319, 4.155%; route: 6.970, 90.859%; tC2Q: 0.382, 4.986% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.839, 100.000% |
Path5
Path Summary:
| Slack | 1.956 |
| Data Arrival Time | 11.620 |
| Data Required Time | 13.576 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.949 | 3.949 | tNET | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/CLK |
| 4.331 | 0.382 | tC2Q | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q |
| 4.483 | 0.151 | tNET | RR | 1 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
| 4.801 | 0.319 | tINS | RF | 108 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
| 11.620 | 6.819 | tNET | FF | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TX2 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.839 | 3.839 | tNET | RR | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK |
| 13.576 | -0.263 | tSu | 1 | IOL105[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem |
Path Statistics:
| Clock Skew | -0.109 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.949, 100.000% |
| Arrival Data Path Delay | cell: 0.319, 4.155%; route: 6.970, 90.859%; tC2Q: 0.382, 4.986% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.839, 100.000% |
Path6
Path Summary:
| Slack | 1.958 |
| Data Arrival Time | 11.620 |
| Data Required Time | 13.578 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.949 | 3.949 | tNET | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/CLK |
| 4.331 | 0.382 | tC2Q | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q |
| 4.483 | 0.151 | tNET | RR | 1 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
| 4.801 | 0.319 | tINS | RF | 108 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
| 11.620 | 6.819 | tNET | FF | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX3 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.841 | 3.841 | tNET | RR | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK |
| 13.578 | -0.263 | tSu | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Path Statistics:
| Clock Skew | -0.107 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.949, 100.000% |
| Arrival Data Path Delay | cell: 0.319, 4.155%; route: 6.970, 90.859%; tC2Q: 0.382, 4.986% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.841, 100.000% |
Path7
Path Summary:
| Slack | 1.958 |
| Data Arrival Time | 11.620 |
| Data Required Time | 13.578 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.949 | 3.949 | tNET | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/CLK |
| 4.331 | 0.382 | tC2Q | RR | 1 | R45C44[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_r_s0/Q |
| 4.483 | 0.151 | tNET | RR | 1 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
| 4.801 | 0.319 | tINS | RF | 108 | R45C44[3][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
| 11.620 | 6.819 | tNET | FF | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX2 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.841 | 3.841 | tNET | RR | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK |
| 13.578 | -0.263 | tSu | 1 | IOL107[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Path Statistics:
| Clock Skew | -0.107 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.949, 100.000% |
| Arrival Data Path Delay | cell: 0.319, 4.155%; route: 6.970, 90.859%; tC2Q: 0.382, 4.986% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.841, 100.000% |
Path8
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path9
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path10
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL62[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path11
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path12
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path13
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL56[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path14
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path15
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path16
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL58[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path17
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path18
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path19
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL58[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path20
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path21
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path22
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL60[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path23
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path24
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Path25
Path Summary:
| Slack | 2.004 |
| Data Arrival Time | 0.498 |
| Data Required Time | 2.503 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem |
| Launch Clk | clk400:[R] |
| Latch Clk | clk400:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk400 | ||||
| 0.000 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 0.003 | 0.003 | tNET | RR | 5 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.498 | 0.496 | tC2Q | RF | 8 | R64C0 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
| 0.498 | 0.000 | tNET | FF | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.500 | 2.500 | active clock edge time | ||||
| 2.500 | 0.000 | clk400 | ||||
| 2.500 | 0.000 | tCL | RR | 102 | PLL_L[0] | Gowin_PLL_inst/PLL_inst/CLKOUT2 |
| 2.503 | 0.003 | tNET | RR | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK |
| 2.503 | 0.000 | tSu | 1 | IOL56[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 2.500 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.003, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.167 |
| Data Arrival Time | 1.649 |
| Data Required Time | 1.482 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.446 | 1.446 | tNET | RR | 1 | R53C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/CLK |
| 1.587 | 0.141 | tC2Q | RF | 1 | R53C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/Q |
| 1.649 | 0.062 | tNET | FF | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.445 | 1.445 | tNET | RR | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA |
| 1.482 | 0.037 | tHld | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | -0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.446, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.062, 30.542%; tC2Q: 0.141, 69.458% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.445, 100.000% |
Path2
Path Summary:
| Slack | 0.197 |
| Data Arrival Time | 1.675 |
| Data Required Time | 1.478 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_15_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C72[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_15_s0/CLK |
| 1.581 | 0.141 | tC2Q | RF | 1 | R65C72[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_15_s0/Q |
| 1.675 | 0.094 | tNET | FF | 1 | BSRAM_R64[14][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[15] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.441 | 1.441 | tNET | RR | 1 | BSRAM_R64[14][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA |
| 1.478 | 0.037 | tHld | 1 | BSRAM_R64[14][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | 0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
Path3
Path Summary:
| Slack | 0.202 |
| Data Arrival Time | 1.679 |
| Data Required Time | 1.477 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_3_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R47C119[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_3_s0/CLK |
| 1.576 | 0.141 | tC2Q | RF | 20 | R47C119[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_3_s0/Q |
| 1.679 | 0.103 | tNET | FF | 1 | BSRAM_R46[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/ADA[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | BSRAM_R46[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA |
| 1.477 | 0.037 | tHld | 1 | BSRAM_R46[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.103, 42.213%; tC2Q: 0.141, 57.787% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
Path4
Path Summary:
| Slack | 0.202 |
| Data Arrival Time | 1.683 |
| Data Required Time | 1.481 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_1_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.439 | 1.439 | tNET | RR | 1 | R47C116[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_1_s0/CLK |
| 1.580 | 0.141 | tC2Q | RF | 19 | R47C116[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_1_s0/Q |
| 1.683 | 0.103 | tNET | FF | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/ADA[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.444 | 1.444 | tNET | RR | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
| 1.481 | 0.037 | tHld | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.439, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.103, 42.213%; tC2Q: 0.141, 57.787% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.444, 100.000% |
Path5
Path Summary:
| Slack | 0.207 |
| Data Arrival Time | 1.692 |
| Data Required Time | 1.485 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_253_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.434 | 1.434 | tNET | RR | 1 | R48C125[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_253_s0/CLK |
| 1.575 | 0.141 | tC2Q | RF | 1 | R48C125[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_253_s0/Q |
| 1.692 | 0.117 | tNET | FF | 1 | BSRAM_R46[26] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.448 | 1.448 | tNET | RR | 1 | BSRAM_R46[26] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/CLKA |
| 1.485 | 0.037 | tHld | 1 | BSRAM_R46[26] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s |
Path Statistics:
| Clock Skew | 0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.434, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.448, 100.000% |
Path6
Path Summary:
| Slack | 0.220 |
| Data Arrival Time | 1.698 |
| Data Required Time | 1.478 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C72[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0/CLK |
| 1.581 | 0.141 | tC2Q | RF | 1 | R65C72[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0/Q |
| 1.698 | 0.117 | tNET | FF | 1 | BSRAM_R64[14][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[14] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.441 | 1.441 | tNET | RR | 1 | BSRAM_R64[14][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA |
| 1.478 | 0.037 | tHld | 1 | BSRAM_R64[14][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | 0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
Path7
Path Summary:
| Slack | 0.228 |
| Data Arrival Time | 1.710 |
| Data Required Time | 1.482 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.459 | 1.459 | tNET | RR | 1 | R62C69[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/CLK |
| 1.600 | 0.141 | tC2Q | RF | 1 | R62C69[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/Q |
| 1.710 | 0.110 | tNET | FF | 1 | BSRAM_R46[14][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/DI[14] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.445 | 1.445 | tNET | RR | 1 | BSRAM_R46[14][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA |
| 1.482 | 0.037 | tHld | 1 | BSRAM_R46[14][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.459, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.110, 43.825%; tC2Q: 0.141, 56.175% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.445, 100.000% |
Path8
Path Summary:
| Slack | 0.228 |
| Data Arrival Time | 1.709 |
| Data Required Time | 1.481 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.439 | 1.439 | tNET | RR | 1 | R47C116[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0/CLK |
| 1.580 | 0.141 | tC2Q | RF | 18 | R47C116[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0/Q |
| 1.709 | 0.129 | tNET | FF | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/ADA[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.444 | 1.444 | tNET | RR | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
| 1.481 | 0.037 | tHld | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.439, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.129, 47.778%; tC2Q: 0.141, 52.222% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.444, 100.000% |
Path9
Path Summary:
| Slack | 0.230 |
| Data Arrival Time | 1.712 |
| Data Required Time | 1.482 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.446 | 1.446 | tNET | RR | 1 | R53C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/CLK |
| 1.587 | 0.141 | tC2Q | RF | 1 | R53C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q |
| 1.712 | 0.125 | tNET | FF | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.445 | 1.445 | tNET | RR | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA |
| 1.482 | 0.037 | tHld | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | -0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.446, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 46.992%; tC2Q: 0.141, 53.008% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.445, 100.000% |
Path10
Path Summary:
| Slack | 0.240 |
| Data Arrival Time | 1.725 |
| Data Required Time | 1.485 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_137_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.439 | 1.439 | tNET | RR | 1 | R52C115[3][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_137_s0/CLK |
| 1.583 | 0.144 | tC2Q | RR | 1 | R52C115[3][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_137_s0/Q |
| 1.725 | 0.142 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/DI[11] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.448 | 1.448 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/CLKA |
| 1.485 | 0.037 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s |
Path Statistics:
| Clock Skew | 0.009 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.439, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.448, 100.000% |
Path11
Path Summary:
| Slack | 0.240 |
| Data Arrival Time | 1.725 |
| Data Required Time | 1.485 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_128_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.439 | 1.439 | tNET | RR | 1 | R52C115[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_128_s0/CLK |
| 1.583 | 0.144 | tC2Q | RR | 1 | R52C115[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_128_s0/Q |
| 1.725 | 0.142 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.448 | 1.448 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/CLKA |
| 1.485 | 0.037 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s |
Path Statistics:
| Clock Skew | 0.009 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.439, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.448, 100.000% |
Path12
Path Summary:
| Slack | 0.244 |
| Data Arrival Time | 1.721 |
| Data Required Time | 1.477 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_203_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_5_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.430 | 1.430 | tNET | RR | 1 | R49C119[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_203_s0/CLK |
| 1.571 | 0.141 | tC2Q | RF | 1 | R49C119[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_203_s0/Q |
| 1.721 | 0.150 | tNET | FF | 1 | BSRAM_R64[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_5_s/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | BSRAM_R64[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_5_s/CLKA |
| 1.477 | 0.037 | tHld | 1 | BSRAM_R64[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_5_s |
Path Statistics:
| Clock Skew | 0.010 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.430, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.150, 51.546%; tC2Q: 0.141, 48.454% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
Path13
Path Summary:
| Slack | 0.244 |
| Data Arrival Time | 1.729 |
| Data Required Time | 1.485 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_143_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R52C112[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_143_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R52C112[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_143_s0/Q |
| 1.729 | 0.142 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/DI[17] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.448 | 1.448 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s/CLKA |
| 1.485 | 0.037 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/gowin_add_SDPX9B_mem_mem_0_3_s |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.448, 100.000% |
Path14
Path Summary:
| Slack | 0.246 |
| Data Arrival Time | 1.728 |
| Data Required Time | 1.482 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.444 | 1.444 | tNET | RR | 1 | R52C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/CLK |
| 1.588 | 0.144 | tC2Q | RR | 1 | R52C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q |
| 1.728 | 0.140 | tNET | RR | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.445 | 1.445 | tNET | RR | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA |
| 1.482 | 0.037 | tHld | 1 | BSRAM_R46[15] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | 0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.444, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.445, 100.000% |
Path15
Path Summary:
| Slack | 0.263 |
| Data Arrival Time | 1.749 |
| Data Required Time | 1.486 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C64[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/CLK |
| 1.581 | 0.141 | tC2Q | RF | 1 | R65C64[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q |
| 1.749 | 0.168 | tNET | FF | 1 | BSRAM_R64[13] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.449 | 1.449 | tNET | RR | 1 | BSRAM_R64[13] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA |
| 1.486 | 0.037 | tHld | 1 | BSRAM_R64[13] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | 0.009 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.168, 54.369%; tC2Q: 0.141, 45.631% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.449, 100.000% |
Path16
Path Summary:
| Slack | 0.263 |
| Data Arrival Time | 1.749 |
| Data Required Time | 1.486 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C64[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/CLK |
| 1.581 | 0.141 | tC2Q | RF | 1 | R65C64[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q |
| 1.749 | 0.168 | tNET | FF | 1 | BSRAM_R64[13] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.449 | 1.449 | tNET | RR | 1 | BSRAM_R64[13] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA |
| 1.486 | 0.037 | tHld | 1 | BSRAM_R64[13] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | 0.009 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.168, 54.369%; tC2Q: 0.141, 45.631% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.449, 100.000% |
Path17
Path Summary:
| Slack | 0.272 |
| Data Arrival Time | 1.753 |
| Data Required Time | 1.481 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_0_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.439 | 1.439 | tNET | RR | 1 | R47C116[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_0_s0/CLK |
| 1.580 | 0.141 | tC2Q | RF | 20 | R47C116[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_0_s0/Q |
| 1.753 | 0.173 | tNET | FF | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/ADA[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.444 | 1.444 | tNET | RR | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
| 1.481 | 0.037 | tHld | 1 | BSRAM_R46[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.439, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.173, 55.096%; tC2Q: 0.141, 44.904% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.444, 100.000% |
Path18
Path Summary:
| Slack | 0.273 |
| Data Arrival Time | 1.754 |
| Data Required Time | 1.481 |
| From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_227_s0 |
| To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.430 | 1.430 | tNET | RR | 1 | R49C123[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_227_s0/CLK |
| 1.574 | 0.144 | tC2Q | RR | 1 | R49C123[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_227_s0/Q |
| 1.754 | 0.180 | tNET | RR | 1 | BSRAM_R46[25][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[11] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.444 | 1.444 | tNET | RR | 1 | BSRAM_R46[25][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA |
| 1.481 | 0.037 | tHld | 1 | BSRAM_R46[25][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s |
Path Statistics:
| Clock Skew | 0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.430, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.180, 55.556%; tC2Q: 0.144, 44.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.444, 100.000% |
Path19
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 3.067 |
| Data Required Time | 2.792 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1 |
| Launch Clk | clk100:[R] |
| Latch Clk | clk100:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100 | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOR103[B] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 41 | IOR103[B] | clk_ibuf/O |
| 2.766 | 2.091 | tNET | RR | 1 | R62C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK |
| 2.908 | 0.141 | tC2Q | RF | 3 | R62C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/Q |
| 2.914 | 0.006 | tNET | FF | 1 | R62C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n47_s1/I2 |
| 3.067 | 0.153 | tINS | FF | 1 | R62C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n47_s1/F |
| 3.067 | 0.000 | tNET | FF | 1 | R62C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100 | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOR103[B] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 41 | IOR103[B] | clk_ibuf/O |
| 2.766 | 2.091 | tNET | RR | 1 | R62C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK |
| 2.792 | 0.025 | tHld | 1 | R62C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.675, 24.417%; route: 2.091, 75.583% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.675, 24.417%; route: 2.091, 75.583% |
Path20
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.735 |
| Data Required Time | 1.460 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R50C83[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3/CLK |
| 1.576 | 0.141 | tC2Q | RF | 5 | R50C83[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3/Q |
| 1.582 | 0.006 | tNET | FF | 1 | R50C83[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n3613_s3/I2 |
| 1.735 | 0.153 | tINS | FF | 1 | R50C83[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n3613_s3/F |
| 1.735 | 0.000 | tNET | FF | 1 | R50C83[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R50C83[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3/CLK |
| 1.460 | 0.025 | tHld | 1 | R50C83[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_21_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
Path21
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.735 |
| Data Required Time | 1.460 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R49C84[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3/CLK |
| 1.576 | 0.141 | tC2Q | RF | 3 | R49C84[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3/Q |
| 1.582 | 0.006 | tNET | FF | 1 | R49C84[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2890_s3/I2 |
| 1.735 | 0.153 | tINS | FF | 1 | R49C84[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2890_s3/F |
| 1.735 | 0.000 | tNET | FF | 1 | R49C84[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R49C84[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3/CLK |
| 1.460 | 0.025 | tHld | 1 | R49C84[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rdback_check_cnt_0_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
Path22
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.744 |
| Data Required Time | 1.469 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.444 | 1.444 | tNET | RR | 1 | R52C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3/CLK |
| 1.585 | 0.141 | tC2Q | RF | 4 | R52C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3/Q |
| 1.591 | 0.006 | tNET | FF | 1 | R52C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2779_s5/I2 |
| 1.744 | 0.153 | tINS | FF | 1 | R52C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2779_s5/F |
| 1.744 | 0.000 | tNET | FF | 1 | R52C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.444 | 1.444 | tNET | RR | 1 | R52C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3/CLK |
| 1.469 | 0.025 | tHld | 1 | R52C82[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/rvalid_cnt_7_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.444, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.444, 100.000% |
Path23
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.769 |
| Data Required Time | 1.494 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.469 | 1.469 | tNET | RR | 1 | R56C84[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4/CLK |
| 1.610 | 0.141 | tC2Q | RF | 14 | R56C84[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4/Q |
| 1.616 | 0.006 | tNET | FF | 1 | R56C84[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2415_s4/I1 |
| 1.769 | 0.153 | tINS | FF | 1 | R56C84[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2415_s4/F |
| 1.769 | 0.000 | tNET | FF | 1 | R56C84[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.469 | 1.469 | tNET | RR | 1 | R56C84[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4/CLK |
| 1.494 | 0.025 | tHld | 1 | R56C84[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/filter_first_burst_s4 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.469, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.469, 100.000% |
Path24
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.735 |
| Data Required Time | 1.460 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R50C79[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3/CLK |
| 1.576 | 0.141 | tC2Q | RF | 2 | R50C79[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3/Q |
| 1.582 | 0.006 | tNET | FF | 1 | R50C79[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2013_s3/I0 |
| 1.735 | 0.153 | tINS | FF | 1 | R50C79[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n2013_s3/F |
| 1.735 | 0.000 | tNET | FF | 1 | R50C79[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R50C79[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3/CLK |
| 1.460 | 0.025 | tHld | 1 | R50C79[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_3_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
Path25
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.735 |
| Data Required Time | 1.460 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R50C79[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3/CLK |
| 1.576 | 0.141 | tC2Q | RF | 2 | R50C79[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3/Q |
| 1.582 | 0.006 | tNET | FF | 1 | R50C79[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1905_s3/I0 |
| 1.735 | 0.153 | tINS | FF | 1 | R50C79[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1905_s3/F |
| 1.735 | 0.000 | tNET | FF | 1 | R50C79[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.435 | 1.435 | tNET | RR | 1 | R50C79[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3/CLK |
| 1.460 | 0.025 | tHld | 1 | R50C79[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/pre_dq_1_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.435, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 5.439 |
| Data Arrival Time | 8.157 |
| Data Required Time | 13.596 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.158 | 2.947 | tNET | FF | 1 | R65C69[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.944 | 3.944 | tNET | RR | 1 | R65C69[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK |
| 13.596 | -0.347 | tSu | 1 | R65C69[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.012 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.519%; route: 3.483, 82.429%; tC2Q: 0.382, 9.052% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.944, 100.000% |
Path2
Path Summary:
| Slack | 5.439 |
| Data Arrival Time | 8.157 |
| Data Required Time | 13.596 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.158 | 2.947 | tNET | FF | 1 | R65C69[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.944 | 3.944 | tNET | RR | 1 | R65C69[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK |
| 13.596 | -0.347 | tSu | 1 | R65C69[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.012 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.519%; route: 3.483, 82.429%; tC2Q: 0.382, 9.052% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.944, 100.000% |
Path3
Path Summary:
| Slack | 5.439 |
| Data Arrival Time | 8.157 |
| Data Required Time | 13.596 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.158 | 2.947 | tNET | FF | 1 | R65C69[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.944 | 3.944 | tNET | RR | 1 | R65C69[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLK |
| 13.596 | -0.347 | tSu | 1 | R65C69[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.012 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.519%; route: 3.483, 82.429%; tC2Q: 0.382, 9.052% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.944, 100.000% |
Path4
Path Summary:
| Slack | 5.439 |
| Data Arrival Time | 8.157 |
| Data Required Time | 13.596 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.158 | 2.947 | tNET | FF | 1 | R65C69[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.944 | 3.944 | tNET | RR | 1 | R65C69[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLK |
| 13.596 | -0.347 | tSu | 1 | R65C69[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.012 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.519%; route: 3.483, 82.429%; tC2Q: 0.382, 9.052% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.944, 100.000% |
Path5
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.085 |
| Data Required Time | 13.603 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.085 | 2.875 | tNET | FF | 1 | R54C73[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.951 | 3.951 | tNET | RR | 1 | R54C73[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLK |
| 13.603 | -0.347 | tSu | 1 | R54C73[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.668%; route: 3.411, 82.123%; tC2Q: 0.382, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.951, 100.000% |
Path6
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.085 |
| Data Required Time | 13.603 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.085 | 2.875 | tNET | FF | 1 | R54C73[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.951 | 3.951 | tNET | RR | 1 | R54C73[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLK |
| 13.603 | -0.347 | tSu | 1 | R54C73[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.668%; route: 3.411, 82.123%; tC2Q: 0.382, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.951, 100.000% |
Path7
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.085 |
| Data Required Time | 13.603 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.085 | 2.875 | tNET | FF | 1 | R54C73[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.951 | 3.951 | tNET | RR | 1 | R54C73[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0/CLK |
| 13.603 | -0.347 | tSu | 1 | R54C73[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.668%; route: 3.411, 82.123%; tC2Q: 0.382, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.951, 100.000% |
Path8
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.085 |
| Data Required Time | 13.603 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.085 | 2.875 | tNET | FF | 1 | R54C73[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.951 | 3.951 | tNET | RR | 1 | R54C73[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLK |
| 13.603 | -0.347 | tSu | 1 | R54C73[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.668%; route: 3.411, 82.123%; tC2Q: 0.382, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.951, 100.000% |
Path9
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.085 |
| Data Required Time | 13.603 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.085 | 2.875 | tNET | FF | 1 | R54C73[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.951 | 3.951 | tNET | RR | 1 | R54C73[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLK |
| 13.603 | -0.347 | tSu | 1 | R54C73[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.668%; route: 3.411, 82.123%; tC2Q: 0.382, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.951, 100.000% |
Path10
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.085 |
| Data Required Time | 13.603 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.085 | 2.875 | tNET | FF | 1 | R54C73[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.951 | 3.951 | tNET | RR | 1 | R54C73[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLK |
| 13.603 | -0.347 | tSu | 1 | R54C73[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.668%; route: 3.411, 82.123%; tC2Q: 0.382, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.951, 100.000% |
Path11
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.085 |
| Data Required Time | 13.603 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.085 | 2.875 | tNET | FF | 1 | R54C73[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.951 | 3.951 | tNET | RR | 1 | R54C73[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLK |
| 13.603 | -0.347 | tSu | 1 | R54C73[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.668%; route: 3.411, 82.123%; tC2Q: 0.382, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.951, 100.000% |
Path12
Path Summary:
| Slack | 5.518 |
| Data Arrival Time | 8.092 |
| Data Required Time | 13.611 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.093 | 2.882 | tNET | FF | 1 | R63C69[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.958 | 3.958 | tNET | RR | 1 | R63C69[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLK |
| 13.611 | -0.347 | tSu | 1 | R63C69[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0 |
Path Statistics:
| Clock Skew | 0.026 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.653%; route: 3.418, 82.154%; tC2Q: 0.382, 9.193% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.958, 100.000% |
Path13
Path Summary:
| Slack | 5.526 |
| Data Arrival Time | 8.068 |
| Data Required Time | 13.594 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 8.068 | 2.857 | tNET | FF | 1 | R54C72[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.941 | 3.941 | tNET | RR | 1 | R54C72[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLK |
| 13.594 | -0.347 | tSu | 1 | R54C72[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.704%; route: 3.393, 82.048%; tC2Q: 0.382, 9.248% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.941, 100.000% |
Path14
Path Summary:
| Slack | 5.671 |
| Data Arrival Time | 7.944 |
| Data Required Time | 13.616 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.944 | 2.734 | tNET | FF | 1 | R61C76[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.963 | 3.963 | tNET | RR | 1 | R61C76[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLK |
| 13.616 | -0.347 | tSu | 1 | R61C76[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 8.972%; route: 3.270, 81.495%; tC2Q: 0.382, 9.533% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.963, 100.000% |
Path15
Path Summary:
| Slack | 5.743 |
| Data Arrival Time | 7.882 |
| Data Required Time | 13.625 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.883 | 2.672 | tNET | FF | 1 | R61C69[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.972 | 3.973 | tNET | RR | 1 | R61C69[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLK |
| 13.625 | -0.347 | tSu | 1 | R61C69[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0 |
Path Statistics:
| Clock Skew | 0.041 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.112%; route: 3.208, 81.206%; tC2Q: 0.382, 9.682% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.973, 100.000% |
Path16
Path Summary:
| Slack | 5.756 |
| Data Arrival Time | 7.838 |
| Data Required Time | 13.594 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.838 | 2.627 | tNET | FF | 1 | R54C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.941 | 3.941 | tNET | RR | 1 | R54C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLK |
| 13.594 | -0.347 | tSu | 1 | R54C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.217%; route: 3.163, 80.990%; tC2Q: 0.382, 9.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.941, 100.000% |
Path17
Path Summary:
| Slack | 5.756 |
| Data Arrival Time | 7.838 |
| Data Required Time | 13.594 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.838 | 2.627 | tNET | FF | 1 | R54C74[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.941 | 3.941 | tNET | RR | 1 | R54C74[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLK |
| 13.594 | -0.347 | tSu | 1 | R54C74[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.217%; route: 3.163, 80.990%; tC2Q: 0.382, 9.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.941, 100.000% |
Path18
Path Summary:
| Slack | 5.756 |
| Data Arrival Time | 7.838 |
| Data Required Time | 13.594 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.838 | 2.627 | tNET | FF | 1 | R54C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.941 | 3.941 | tNET | RR | 1 | R54C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLK |
| 13.594 | -0.347 | tSu | 1 | R54C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.217%; route: 3.163, 80.990%; tC2Q: 0.382, 9.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.941, 100.000% |
Path19
Path Summary:
| Slack | 5.756 |
| Data Arrival Time | 7.838 |
| Data Required Time | 13.594 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.838 | 2.627 | tNET | FF | 1 | R54C74[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.941 | 3.941 | tNET | RR | 1 | R54C74[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLK |
| 13.594 | -0.347 | tSu | 1 | R54C74[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.217%; route: 3.163, 80.990%; tC2Q: 0.382, 9.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.941, 100.000% |
Path20
Path Summary:
| Slack | 5.803 |
| Data Arrival Time | 7.797 |
| Data Required Time | 13.599 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.797 | 2.586 | tNET | FF | 1 | R62C75[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.947 | 3.947 | tNET | RR | 1 | R62C75[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLK |
| 13.599 | -0.347 | tSu | 1 | R62C75[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.315%; route: 3.122, 80.788%; tC2Q: 0.382, 9.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.947, 100.000% |
Path21
Path Summary:
| Slack | 5.803 |
| Data Arrival Time | 7.797 |
| Data Required Time | 13.599 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.797 | 2.586 | tNET | FF | 1 | R62C75[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.947 | 3.947 | tNET | RR | 1 | R62C75[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLK |
| 13.599 | -0.347 | tSu | 1 | R62C75[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.315%; route: 3.122, 80.788%; tC2Q: 0.382, 9.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.947, 100.000% |
Path22
Path Summary:
| Slack | 5.803 |
| Data Arrival Time | 7.797 |
| Data Required Time | 13.599 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.797 | 2.586 | tNET | FF | 1 | R62C75[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.947 | 3.947 | tNET | RR | 1 | R62C75[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLK |
| 13.599 | -0.347 | tSu | 1 | R62C75[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.315%; route: 3.122, 80.788%; tC2Q: 0.382, 9.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.947, 100.000% |
Path23
Path Summary:
| Slack | 5.803 |
| Data Arrival Time | 7.797 |
| Data Required Time | 13.599 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.797 | 2.586 | tNET | FF | 1 | R62C75[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.947 | 3.947 | tNET | RR | 1 | R62C75[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLK |
| 13.599 | -0.347 | tSu | 1 | R62C75[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.315%; route: 3.122, 80.788%; tC2Q: 0.382, 9.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.947, 100.000% |
Path24
Path Summary:
| Slack | 5.803 |
| Data Arrival Time | 7.797 |
| Data Required Time | 13.599 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.797 | 2.586 | tNET | FF | 1 | R62C75[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.947 | 3.947 | tNET | RR | 1 | R62C75[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_1_s0/CLK |
| 13.599 | -0.347 | tSu | 1 | R62C75[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_1_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.315%; route: 3.122, 80.788%; tC2Q: 0.382, 9.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.947, 100.000% |
Path25
Path Summary:
| Slack | 5.803 |
| Data Arrival Time | 7.797 |
| Data Required Time | 13.599 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.932 | 3.932 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 4.314 | 0.382 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 4.851 | 0.536 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 5.211 | 0.360 | tINS | RF | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 7.797 | 2.586 | tNET | FF | 1 | R62C75[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sysclk | ||||
| 10.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 13.947 | 3.947 | tNET | RR | 1 | R62C75[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0/CLK |
| 13.599 | -0.347 | tSu | 1 | R62C75[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 10.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.932, 100.000% |
| Arrival Data Path Delay | cell: 0.360, 9.315%; route: 3.122, 80.788%; tC2Q: 0.382, 9.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.947, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.812 |
| Data Arrival Time | 2.228 |
| Data Required Time | 1.416 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 2.228 | 0.183 | tNET | RR | 1 | R56C76[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.469 | 1.469 | tNET | RR | 1 | R56C76[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK |
| 1.416 | -0.053 | tHld | 1 | R56C76[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.026 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 25.987%; route: 0.437, 55.669%; tC2Q: 0.144, 18.344% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.469, 100.000% |
Path2
Path Summary:
| Slack | 0.812 |
| Data Arrival Time | 2.228 |
| Data Required Time | 1.416 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 2.228 | 0.183 | tNET | RR | 1 | R56C76[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.469 | 1.469 | tNET | RR | 1 | R56C76[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLK |
| 1.416 | -0.053 | tHld | 1 | R56C76[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0 |
Path Statistics:
| Clock Skew | 0.026 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 25.987%; route: 0.437, 55.669%; tC2Q: 0.144, 18.344% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.469, 100.000% |
Path3
Path Summary:
| Slack | 0.812 |
| Data Arrival Time | 2.228 |
| Data Required Time | 1.416 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 2.228 | 0.183 | tNET | RR | 1 | R56C76[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.469 | 1.469 | tNET | RR | 1 | R56C76[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLK |
| 1.416 | -0.053 | tHld | 1 | R56C76[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.026 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 25.987%; route: 0.437, 55.669%; tC2Q: 0.144, 18.344% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.469, 100.000% |
Path4
Path Summary:
| Slack | 0.904 |
| Data Arrival Time | 2.324 |
| Data Required Time | 1.420 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 2.324 | 0.279 | tNET | RR | 1 | R56C77[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.473 | 1.473 | tNET | RR | 1 | R56C77[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK |
| 1.420 | -0.053 | tHld | 1 | R56C77[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0 |
Path Statistics:
| Clock Skew | 0.030 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 23.156%; route: 0.533, 60.499%; tC2Q: 0.144, 16.345% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.473, 100.000% |
Path5
Path Summary:
| Slack | 1.668 |
| Data Arrival Time | 3.065 |
| Data Required Time | 1.397 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.065 | 1.020 | tNET | RR | 1 | R63C74[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.450 | 1.450 | tNET | RR | 1 | R63C74[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLK |
| 1.397 | -0.053 | tHld | 1 | R63C74[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.577%; route: 1.274, 78.545%; tC2Q: 0.144, 8.878% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
Path6
Path Summary:
| Slack | 1.668 |
| Data Arrival Time | 3.065 |
| Data Required Time | 1.397 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.065 | 1.020 | tNET | RR | 1 | R63C74[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.450 | 1.450 | tNET | RR | 1 | R63C74[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0/CLK |
| 1.397 | -0.053 | tHld | 1 | R63C74[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.577%; route: 1.274, 78.545%; tC2Q: 0.144, 8.878% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
Path7
Path Summary:
| Slack | 1.668 |
| Data Arrival Time | 3.065 |
| Data Required Time | 1.397 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.065 | 1.020 | tNET | RR | 1 | R63C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.450 | 1.450 | tNET | RR | 1 | R63C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLK |
| 1.397 | -0.053 | tHld | 1 | R63C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.577%; route: 1.274, 78.545%; tC2Q: 0.144, 8.878% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
Path8
Path Summary:
| Slack | 1.668 |
| Data Arrival Time | 3.065 |
| Data Required Time | 1.397 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.065 | 1.020 | tNET | RR | 1 | R63C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.450 | 1.450 | tNET | RR | 1 | R63C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLK |
| 1.397 | -0.053 | tHld | 1 | R63C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.577%; route: 1.274, 78.545%; tC2Q: 0.144, 8.878% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
Path9
Path Summary:
| Slack | 1.668 |
| Data Arrival Time | 3.065 |
| Data Required Time | 1.397 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.065 | 1.020 | tNET | RR | 1 | R63C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.450 | 1.450 | tNET | RR | 1 | R63C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLK |
| 1.397 | -0.053 | tHld | 1 | R63C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.577%; route: 1.274, 78.545%; tC2Q: 0.144, 8.878% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
Path10
Path Summary:
| Slack | 1.677 |
| Data Arrival Time | 3.090 |
| Data Required Time | 1.413 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.090 | 1.045 | tNET | RR | 1 | R60C73[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.466 | 1.466 | tNET | RR | 1 | R60C73[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK |
| 1.413 | -0.053 | tHld | 1 | R60C73[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0 |
Path Statistics:
| Clock Skew | 0.023 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.386%; route: 1.299, 78.871%; tC2Q: 0.144, 8.743% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.466, 100.000% |
Path11
Path Summary:
| Slack | 1.677 |
| Data Arrival Time | 3.090 |
| Data Required Time | 1.413 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.090 | 1.045 | tNET | RR | 1 | R60C73[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.466 | 1.466 | tNET | RR | 1 | R60C73[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLK |
| 1.413 | -0.053 | tHld | 1 | R60C73[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.023 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.386%; route: 1.299, 78.871%; tC2Q: 0.144, 8.743% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.466, 100.000% |
Path12
Path Summary:
| Slack | 1.677 |
| Data Arrival Time | 3.090 |
| Data Required Time | 1.413 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.090 | 1.045 | tNET | RR | 1 | R60C73[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.466 | 1.466 | tNET | RR | 1 | R60C73[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK |
| 1.413 | -0.053 | tHld | 1 | R60C73[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.023 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.386%; route: 1.299, 78.871%; tC2Q: 0.144, 8.743% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.466, 100.000% |
Path13
Path Summary:
| Slack | 1.677 |
| Data Arrival Time | 3.090 |
| Data Required Time | 1.413 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.090 | 1.045 | tNET | RR | 1 | R60C73[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.466 | 1.466 | tNET | RR | 1 | R60C73[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLK |
| 1.413 | -0.053 | tHld | 1 | R60C73[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0 |
Path Statistics:
| Clock Skew | 0.023 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.386%; route: 1.299, 78.871%; tC2Q: 0.144, 8.743% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.466, 100.000% |
Path14
Path Summary:
| Slack | 1.685 |
| Data Arrival Time | 3.094 |
| Data Required Time | 1.409 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.094 | 1.049 | tNET | RR | 1 | R60C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.462 | 1.462 | tNET | RR | 1 | R60C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0/CLK |
| 1.409 | -0.053 | tHld | 1 | R60C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_3_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.356%; route: 1.303, 78.922%; tC2Q: 0.144, 8.722% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.462, 100.000% |
Path15
Path Summary:
| Slack | 1.685 |
| Data Arrival Time | 3.094 |
| Data Required Time | 1.409 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.094 | 1.049 | tNET | RR | 1 | R60C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.462 | 1.462 | tNET | RR | 1 | R60C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK |
| 1.409 | -0.053 | tHld | 1 | R60C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.356%; route: 1.303, 78.922%; tC2Q: 0.144, 8.722% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.462, 100.000% |
Path16
Path Summary:
| Slack | 1.685 |
| Data Arrival Time | 3.094 |
| Data Required Time | 1.409 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.094 | 1.049 | tNET | RR | 1 | R60C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.462 | 1.462 | tNET | RR | 1 | R60C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLK |
| 1.409 | -0.053 | tHld | 1 | R60C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.356%; route: 1.303, 78.922%; tC2Q: 0.144, 8.722% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.462, 100.000% |
Path17
Path Summary:
| Slack | 1.685 |
| Data Arrival Time | 3.090 |
| Data Required Time | 1.405 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.090 | 1.045 | tNET | RR | 1 | R60C71[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.458 | 1.458 | tNET | RR | 1 | R60C71[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK |
| 1.405 | -0.053 | tHld | 1 | R60C71[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.386%; route: 1.299, 78.871%; tC2Q: 0.144, 8.743% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.458, 100.000% |
Path18
Path Summary:
| Slack | 1.685 |
| Data Arrival Time | 3.099 |
| Data Required Time | 1.414 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.099 | 1.054 | tNET | RR | 1 | R57C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.467 | 1.467 | tNET | RR | 1 | R57C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLK |
| 1.414 | -0.053 | tHld | 1 | R57C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0 |
Path Statistics:
| Clock Skew | 0.024 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 12.317%; route: 1.308, 78.989%; tC2Q: 0.144, 8.694% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.467, 100.000% |
Path19
Path Summary:
| Slack | 1.732 |
| Data Arrival Time | 3.148 |
| Data Required Time | 1.416 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.148 | 1.103 | tNET | RR | 1 | R56C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.469 | 1.469 | tNET | RR | 1 | R56C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLK |
| 1.416 | -0.053 | tHld | 1 | R56C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0 |
Path Statistics:
| Clock Skew | 0.026 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 11.963%; route: 1.357, 79.592%; tC2Q: 0.144, 8.445% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.469, 100.000% |
Path20
Path Summary:
| Slack | 1.751 |
| Data Arrival Time | 3.153 |
| Data Required Time | 1.402 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.153 | 1.108 | tNET | RR | 1 | R62C72[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.455 | 1.455 | tNET | RR | 1 | R62C72[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0/CLK |
| 1.402 | -0.053 | tHld | 1 | R62C72[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0 |
Path Statistics:
| Clock Skew | 0.012 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 11.930%; route: 1.362, 79.649%; tC2Q: 0.144, 8.421% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.455, 100.000% |
Path21
Path Summary:
| Slack | 1.760 |
| Data Arrival Time | 3.147 |
| Data Required Time | 1.387 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.147 | 1.102 | tNET | RR | 1 | R65C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLK |
| 1.387 | -0.053 | tHld | 1 | R65C74[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0 |
Path Statistics:
| Clock Skew | -0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 11.972%; route: 1.356, 79.577%; tC2Q: 0.144, 8.451% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
Path22
Path Summary:
| Slack | 1.760 |
| Data Arrival Time | 3.147 |
| Data Required Time | 1.387 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.147 | 1.102 | tNET | RR | 1 | R65C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0/CLK |
| 1.387 | -0.053 | tHld | 1 | R65C74[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0 |
Path Statistics:
| Clock Skew | -0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 11.972%; route: 1.356, 79.577%; tC2Q: 0.144, 8.451% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
Path23
Path Summary:
| Slack | 1.760 |
| Data Arrival Time | 3.147 |
| Data Required Time | 1.387 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.147 | 1.102 | tNET | RR | 1 | R65C74[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C74[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/CLK |
| 1.387 | -0.053 | tHld | 1 | R65C74[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0 |
Path Statistics:
| Clock Skew | -0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 11.972%; route: 1.356, 79.577%; tC2Q: 0.144, 8.451% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
Path24
Path Summary:
| Slack | 1.760 |
| Data Arrival Time | 3.147 |
| Data Required Time | 1.387 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.147 | 1.102 | tNET | RR | 1 | R65C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.440 | 1.440 | tNET | RR | 1 | R65C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLK |
| 1.387 | -0.053 | tHld | 1 | R65C74[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0 |
Path Statistics:
| Clock Skew | -0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 11.972%; route: 1.356, 79.577%; tC2Q: 0.144, 8.451% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.440, 100.000% |
Path25
Path Summary:
| Slack | 1.772 |
| Data Arrival Time | 3.165 |
| Data Required Time | 1.393 |
| From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
| To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0 |
| Launch Clk | sysclk:[R] |
| Latch Clk | sysclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.443 | 1.443 | tNET | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R54C83[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
| 1.841 | 0.254 | tNET | RR | 1 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
| 2.045 | 0.204 | tINS | RR | 80 | R54C77[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
| 3.165 | 1.120 | tNET | RR | 1 | R63C75[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sysclk | ||||
| 0.000 | 0.000 | tCL | RR | 6242 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.446 | 1.446 | tNET | RR | 1 | R63C75[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLK |
| 1.393 | -0.053 | tHld | 1 | R63C75[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.204, 11.847%; route: 1.374, 79.791%; tC2Q: 0.144, 8.362% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.446, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 1.797 |
| Actual Width: | 2.797 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.960 | 3.960 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.757 | 1.757 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB |
MPW2
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA |
MPW3
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB |
MPW4
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB |
MPW5
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA |
MPW6
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA |
MPW7
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA |
MPW8
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKB |
MPW9
MPW Summary:
| Slack: | 1.803 |
| Actual Width: | 2.803 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.951 | 3.951 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.754 | 1.754 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB |
MPW10
MPW Summary:
| Slack: | 1.808 |
| Actual Width: | 2.808 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | sysclk |
| Objects: | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | sysclk | ||
| 0.000 | 0.000 | tCL | RR | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 3.942 | 3.942 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sysclk | ||
| 5.000 | 0.000 | tCL | FF | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 6.750 | 1.750 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 6242 | clk_x1 | 1.694 | 4.004 |
| 343 | eye_calib_start_rr | 5.241 | 3.769 |
| 335 | ddr_init_internal_rr | 4.364 | 4.666 |
| 292 | dqsts1 | 4.961 | 4.002 |
| 291 | dqs_reg | 3.534 | 5.518 |
| 128 | raddr[2] | 2.982 | 2.510 |
| 108 | n258_6 | 1.810 | 6.993 |
| 102 | memory_clk | 2.004 | 0.005 |
| 80 | if_wrreset_Z | 5.439 | 3.223 |
| 76 | rvalid_cnt_clr | 6.605 | 1.351 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R48C90 | 69.44% |
| R62C83 | 69.44% |
| R50C90 | 69.44% |
| R50C109 | 69.44% |
| R47C123 | 68.06% |
| R49C108 | 68.06% |
| R52C109 | 66.67% |
| R63C82 | 66.67% |
| R45C129 | 66.67% |
| R47C86 | 66.67% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name clk400 -period 2.5 -waveform {0 1.25} [get_nets {memory_clk}] |
| TC_CLOCK | Actived | create_clock -name clk100 -period 10 -waveform {0 5} [get_ports {clk}] |
| TC_CLOCK | Actived | create_clock -name sysclk -period 10 -waveform {0 5} [get_pins {u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk100}] -group [get_clocks {sysclk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {sysclk}] -group [get_clocks {clk400}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk100}] -group [get_clocks {clk400}] |