Power Messages

Report Title	Power Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_1v4_hs.cst
Timing Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_1v4_hs.sdc
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Fri Feb 28 16:51:51 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	424.262
Quiescent Power (mW)	95.436
Dynamic Power (mW)	328.826

Thermal Information:

Junction Temperature	30.185
Theta JA	12.222
Max Allowed Ambient Temperature	79.815

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	241.020	79.962	288.884
VCCX	1.800	6.789	7.200	25.180
VCCIO15	1.500	6.520	2.687	13.810
VCCIO33	3.300	0.296	0.218	1.696
VCC_LDO	1.200	74.110	4.800	94.692

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	3.116	NA	12.483
IO	42.003	12.080	61.910
BSRAM	173.664	NA	NA
PLL	88.932	NA	NA
DDRDLL	33.178	NA	NA
DQS	166.536	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	465.426	465.426(465.393)
top/Gowin_PLL_inst/	88.932	88.932(0.000)
top/u_ddr3/	375.891	375.891(375.891)
top/u_ddr3/gw3_top/	375.891	375.891(375.891)
top/u_ddr3/gw3_top/u_ddr_phy_top/	287.599	287.599(254.229)
top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/	0.030	0.030(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/	0.480	0.480(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/	253.142	253.142(253.133)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/	63.257	63.257(63.177)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/	41.663	41.663(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/	21.514	21.514(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/	63.254	63.254(63.174)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/	41.660	41.660(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/	21.514	21.514(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/	63.254	63.254(63.174)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/	41.660	41.660(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/	21.514	21.514(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/	63.254	63.254(63.174)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/	41.660	41.660(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/	21.514	21.514(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/	0.014	0.014(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/	0.014	0.014(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/	0.014	0.014(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/	0.014	0.014(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/	0.057	0.057(0.035)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/	0.035	0.035(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/	0.000	0.000(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib/	0.185	0.185(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/	0.088	0.088(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/	0.303	0.303(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/	88.292	88.292(88.156)
top/u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/	0.182	0.182(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/	87.799	87.799(87.638)
top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/	87.638	87.638(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/	0.139	0.139(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_rank_ctrl/	0.024	0.024(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_timing_ctrl/	0.013	0.013(0.000)
top/u_rd/	0.569	0.569(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
sysclk	100.000	176.755
clk100	100.000	88.970
NO CLOCK DOMAIN	0.000	0.000
clk400	400.000	199.714