Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_memory_interface\ddr3_memory_interface.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddrtest.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\gowin_pll\gowin_pll.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Fri Feb 28 16:50:52 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 670.758MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 670.758MB
    Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.206s, Peak memory usage = 670.758MB
    Optimizing Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.212s, Peak memory usage = 670.758MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.181s, Peak memory usage = 670.758MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 670.758MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 670.758MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 670.758MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.398s, Peak memory usage = 670.758MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 670.758MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 670.758MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 670.758MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.355s, Peak memory usage = 670.758MB
Generate output files:
    CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.688s, Peak memory usage = 670.758MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 670.758MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 75
I/O Buf 70
    IBUF 1
    OBUF 28
    TBUF 4
    IOBUF 32
    ELVDS_OBUF 1
    ELVDS_IOBUF 4
Register 6118
    DFFSE 1
    DFFRE 249
    DFFPE 75
    DFFCE 5793
LUT 3426
    LUT2 466
    LUT3 1553
    LUT4 1407
ALU 429
    ALU 429
INV 24
    INV 24
IOLOGIC 128
    IDES8_MEM 32
    OSER8 24
    OSER8_MEM 40
    IODELAY 32
BSRAM 16
    SDPB 8
    SDPX9B 8
CLOCK 7
    PLL 1
    CLKDIV 1
    DQS 4
    DDRDLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3879(3450 LUT, 429 ALU) / 138240 3%
Register 6118 / 139140 5%
  --Register as Latch 0 / 139140 0%
  --Register as FF 6118 / 139140 5%
BSRAM 16 / 340 5%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
2 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk Generated 2.500 400.000 0.000 1.250 clk_ibuf/I clk Gowin_PLL_inst/PLL_inst/CLKOUT2
3 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 10.000 100.000 0.000 5.000 Gowin_PLL_inst/PLL_inst/CLKOUT2 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 149.477(MHz) 7 TOP
2 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk 400.000(MHz) 1115.449(MHz) 1 TOP
3 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 100.000(MHz) 161.225(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.163
Data Arrival Time 2.579
Data Required Time 1.416
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.381 0.381 tCL RR 6210 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.793 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
1.176 0.382 tC2Q RR 12 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
1.588 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
2.167 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
2.579 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.550 0.300 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.935 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.900 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.416 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.108
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -1.163
Data Arrival Time 2.579
Data Required Time 1.416
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.381 0.381 tCL RR 6210 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.793 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
1.176 0.382 tC2Q RR 10 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
1.588 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
2.167 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
2.579 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.550 0.300 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.935 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.900 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.416 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.108
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -1.163
Data Arrival Time 2.579
Data Required Time 1.416
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.381 0.381 tCL RR 6210 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.793 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK
1.176 0.382 tC2Q RR 10 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q
1.588 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0
2.167 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F
2.579 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.550 0.300 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.935 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.900 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.416 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.108
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -1.163
Data Arrival Time 2.579
Data Required Time 1.416
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.381 0.381 tCL RR 6210 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.793 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK
1.176 0.382 tC2Q RR 10 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q
1.588 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0
2.167 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F
2.579 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.550 0.300 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.935 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.900 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.416 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.108
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 1.590
Data Arrival Time 1.588
Data Required Time 3.178
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.381 0.381 tCL RR 6210 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.793 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/CLK
1.176 0.382 tC2Q RR 8 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q
1.588 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/CALIB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
2.500 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
2.800 0.300 tCL RR 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
3.213 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.178 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
3.178 0.000 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Path Statistics:
Clock Skew: -0.080
Setup Relationship: 2.500
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%