Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Fri Feb 28 16:00:19 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR3_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 147.359MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 147.359MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.315s, Peak memory usage = 147.359MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.21s, Peak memory usage = 147.359MB Optimizing Phase 2: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.499s, Peak memory usage = 147.359MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.283s, Peak memory usage = 147.359MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 147.359MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 147.359MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 147.359MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.446s, Peak memory usage = 147.359MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 147.359MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 147.359MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 165.176MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.506s, Peak memory usage = 165.176MB Generate output files: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.316s, Peak memory usage = 165.176MB |
| Total Time and Memory Usage | CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 165.176MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 370 |
| I/O Buf | 364 |
| IBUF | 182 |
| OBUF | 161 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 3156 |
| DFF | 137 |
| DFFS | 1 |
| DFFR | 1 |
| DFFP | 54 |
| DFFPE | 12 |
| DFFC | 2433 |
| DFFCE | 518 |
| LUT | 1992 |
| LUT2 | 392 |
| LUT3 | 643 |
| LUT4 | 957 |
| ALU | 125 |
| ALU | 125 |
| SSRAM | 120 |
| RAM16S4 | 44 |
| RAM16SDP4 | 76 |
| INV | 19 |
| INV | 19 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DHCEN | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2856(2011 LUT, 125 ALU, 120 RAM16) / 20736 | 14% |
| Register | 3156 / 16173 | 20% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 3156 / 16173 | 20% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | memory_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| 2 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.000(MHz) | 1030.929(MHz) | 1 | TOP |
| 2 | clk | 100.000(MHz) | 172.891(MHz) | 6 | TOP |
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 130.736(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.176 |
| Data Arrival Time | 2.436 |
| Data Required Time | 5.612 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 3299 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 2.436 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.474 | 0.474 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 5.660 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 6.134 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.099 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.612 | -0.487 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.433 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 3.176 |
| Data Arrival Time | 2.436 |
| Data Required Time | 5.612 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 3299 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 2.436 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.474 | 0.474 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 5.660 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 6.134 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.099 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.612 | -0.487 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.433 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 4.187 |
| Data Arrival Time | 1.066 |
| Data Required Time | 5.253 |
| From | gw3_top/u_ddr_phy_top/stop_reg_2_s0 |
| To | gw3_top/u_ddr_phy_top/fclk_dhcen |
| Launch Clk | clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.474 | 0.474 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 5.439 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/fclk_dhcen | ||
| 5.253 | -0.186 | tSu | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen |
| Clock Skew: | 0.114 |
| Setup Relationship: | 5.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 4.216 |
| Data Arrival Time | 6.109 |
| Data Required Time | 10.325 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1 |
| To | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 5 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 4 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1 |
| 2.650 | 0.555 | tINS | FF | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F |
| 3.124 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/I2 |
| 3.577 | 0.453 | tINS | FF | 4 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/F |
| 4.051 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/I1 |
| 4.606 | 0.555 | tINS | FF | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/F |
| 5.080 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s4/I1 |
| 5.635 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s4/F |
| 6.109 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.673, 46.495%; route: 2.844, 49.470%; tC2Q: 0.232, 4.035% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 4.216 |
| Data Arrival Time | 6.109 |
| Data Required Time | 10.325 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1 |
| To | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 5 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 4 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1 |
| 2.650 | 0.555 | tINS | FF | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F |
| 3.124 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/I2 |
| 3.577 | 0.453 | tINS | FF | 4 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/F |
| 4.051 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/I1 |
| 4.606 | 0.555 | tINS | FF | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/F |
| 5.080 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s1/I1 |
| 5.635 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s1/F |
| 6.109 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.673, 46.495%; route: 2.844, 49.470%; tC2Q: 0.232, 4.035% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |