Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.sdc
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Device Version	C
Created Time	Fri Feb 28 17:08:41 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	9046
Numbers of Endpoints Analyzed	9488
Numbers of Falling Endpoints	2
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clkin	Base	20.000	50.000	0.000	10.000			clk
2	clk_x4	Base	2.857	350.017	0.000	1.429			clk_x4
3	clkx1	Base	10.000	100.000	0.000	5.000			u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
4	upll/rpll_inst/CLKOUTP.default_gen_clk	Generated	2.857	350.000	0.000	1.429	clk_ibuf/I	clkin	upll/rpll_inst/CLKOUTP
5	upll/rpll_inst/CLKOUTD.default_gen_clk	Generated	5.714	175.000	0.000	2.857	clk_ibuf/I	clkin	upll/rpll_inst/CLKOUTD
6	upll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	8.571	116.667	0.000	4.286	clk_ibuf/I	clkin	upll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clkin	50.000(MHz)	263.061(MHz)	6	TOP
2	clk_x4	350.017(MHz)	2016.128(MHz)	1	TOP
3	clkx1	100.000(MHz)	144.624(MHz)	3	TOP

No timing paths to get frequency of upll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of upll/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of upll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clkin	Setup	0.000	0
clkin	Hold	0.000	0
clk_x4	Setup	0.000	0
clk_x4	Hold	0.000	0
clkx1	Setup	0.000	0
clkx1	Hold	0.000	0
upll/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
upll/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
upll/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
upll/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
upll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
upll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.041	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s/DI[1]	clkin:[R]	clkx1:[R]	10.000	2.088	6.802
2	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
3	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
4	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
5	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
6	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
7	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
8	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
9	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
10	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
11	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
12	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
13	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
14	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
15	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
16	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
17	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
18	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
19	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
20	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
21	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
22	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
23	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
24	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496
25	2.361	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0]	clk_x4:[R]	clk_x4:[R]	2.857	0.000	0.496

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.234	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/D4	clkx1:[R]	clkx1:[R]	0.000	0.000	0.329
2	0.246	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/D5	clkx1:[R]	clkx1:[R]	0.000	0.000	0.329
3	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_34_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/DI[2]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
4	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_33_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/DI[1]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
5	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_32_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
6	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[3]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
7	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[2]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
8	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[1]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
9	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
10	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
11	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[2]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
12	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
13	0.313	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
14	0.313	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_101_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_25_s/DI[1]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
15	0.313	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_39_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s/DI[3]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
16	0.313	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_36_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
17	0.313	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_25_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[1]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
18	0.313	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_6_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[2]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.323
19	0.315	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s/DI[3]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.325
20	0.315	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.325
21	0.315	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_12_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.325
22	0.315	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_5_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.325
23	0.315	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.325
24	0.315	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_98_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s/DI[2]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.325
25	0.315	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_96_s0/Q	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s/DI[0]	clkx1:[R]	clkx1:[R]	0.000	0.000	0.325

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.257	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0/CLEAR	clkin:[R]	clkx1:[F]	5.000	2.085	1.588
2	1.257	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/CLEAR	clkin:[R]	clkx1:[F]	5.000	2.085	1.588
3	3.526	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.316
4	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
5	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
6	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
7	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
8	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
9	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
10	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
11	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
12	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
13	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
14	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
15	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
16	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
17	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
18	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
19	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
20	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
21	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
22	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
23	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
24	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089
25	3.753	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR	clkin:[R]	clkx1:[R]	10.000	2.088	4.089

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.841	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.852
2	1.841	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.852
3	1.841	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.852
4	1.841	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.852
5	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
6	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
7	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
8	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
9	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
10	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
11	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
12	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
13	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
14	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
15	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
16	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
17	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
18	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
19	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
20	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
21	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
22	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
23	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
24	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862
25	1.851	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR	clkx1:[R]	clkx1:[R]	0.000	0.000	1.862

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.237	4.237	1.000	Low Pulse Width	clkx1	led_cnt_31_s0
2	3.237	4.237	1.000	Low Pulse Width	clkx1	led_cnt_24_s0
3	3.237	4.237	1.000	Low Pulse Width	clkx1	led_cnt_16_s0
4	3.237	4.237	1.000	Low Pulse Width	clkx1	led_cnt_12_s0
5	3.237	4.237	1.000	Low Pulse Width	clkx1	led_cnt_10_s0
6	3.237	4.237	1.000	Low Pulse Width	clkx1	led_cnt_9_s0
7	3.237	4.237	1.000	Low Pulse Width	clkx1	u_rd/app_rd_data_r_74_s0
8	3.237	4.237	1.000	Low Pulse Width	clkx1	u_rd/app_rd_data_rr_75_s0
9	3.237	4.237	1.000	Low Pulse Width	clkx1	u_ddr3/gw3_top/u_gwmc_top/mc_address_dly_50_s0
10	3.237	4.237	1.000	Low Pulse Width	clkx1	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_93_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.041
Data Arrival Time	11.161
Data Required Time	12.202
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R17C34[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561	0.371	tINS	FF	2	R17C34[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
6.978	0.418	tNET	FF	1	R20C34[3][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.495	0.517	tINS	FF	14	R20C34[3][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.034	0.539	tNET	FF	1	R22C32[1][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s33/I0
8.551	0.517	tINS	FF	1	R22C32[1][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s33/F
9.191	0.640	tNET	FF	2	R22C35[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/I1
9.761	0.570	tINS	FR	1	R22C35[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT
9.761	0.000	tNET	RR	2	R22C35[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN
9.796	0.035	tINS	RF	1	R22C35[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT
9.796	0.000	tNET	FF	2	R22C35[1][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN
9.831	0.035	tINS	FF	1	R22C35[1][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.831	0.000	tNET	FF	2	R22C35[2][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.866	0.035	tINS	FF	1	R22C35[2][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.866	0.000	tNET	FF	2	R22C35[2][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.901	0.035	tINS	FF	1	R22C35[2][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.901	0.000	tNET	FF	2	R22C36[0][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.937	0.035	tINS	FF	1	R22C36[0][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.937	0.000	tNET	FF	2	R22C36[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.972	0.035	tINS	FF	1	R22C36[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.972	0.000	tNET	FF	2	R22C36[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
10.007	0.035	tINS	FF	1	R22C36[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
11.161	1.154	tNET	FF	1	R15C37	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R15C37	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s
12.202	-0.035	tSu		1	R15C37	u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 2.221, 32.659%; route: 4.348, 63.930%; tC2Q: 0.232, 3.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path2

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path3

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path4

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB43[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path5

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path6

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path7

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB44[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path8

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path9

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path10

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB32[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path11

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path12

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path13

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB45[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path14

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path15

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path16

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB38[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path17

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path18

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path19

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB41[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path20

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path21

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path22

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB39[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path23

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803	0.000	tNET	FF	1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path24

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803	0.000	tNET	FF	1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Path25

Path Summary:

Slack	2.361
Data Arrival Time	0.803
Data Required Time	3.164
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk	clk_x4:[R]
Latch Clk	clk_x4:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x4
0.000	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
0.000	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307	0.125	tNET	RR	5	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803	0.496	tC2Q	RF	8	R56C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803	0.000	tNET	FF	1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.857	2.857					active clock edge time
2.857	0.000					clk_x4
2.857	0.000	tCL	RR	1	PLL_L[0]	upll/rpll_inst/CLKOUT
2.857	0.000	tNET	RR	3	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.039	0.182	tINS	RR	64	R28C0	u_ddr3/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.164	0.125	tNET	RR	1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
3.164	0.000	tSu		1	IOB42[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.857
Logic Level	1
Arrival Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay	cell: 0.182, 59.219%; route: 0.125, 40.781%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.234
Data Arrival Time	1.840
Data Required Time	1.606
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R29C2[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0/CLK
1.712	0.201	tC2Q	RF	2	R29C2[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0/Q
1.840	0.128	tNET	FF	1	IOL29[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/D4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	IOL29[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK
1.606	0.095	tHld		1	IOL29[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path2

Path Summary:

Slack	0.246
Data Arrival Time	1.840
Data Required Time	1.594
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R29C2[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0/CLK
1.712	0.201	tC2Q	RF	2	R29C2[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_78_s0/Q
1.840	0.128	tNET	FF	1	IOL29[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/D5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	IOL29[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK
1.594	0.083	tHld		1	IOL29[A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path3

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_34_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C42[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_34_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C42[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_34_s0/Q
1.834	0.122	tNET	FF	1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/CLK
1.521	0.010	tHld		1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path4

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_33_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C42[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_33_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C42[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_33_s0/Q
1.834	0.122	tNET	FF	1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/CLK
1.521	0.010	tHld		1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path5

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_32_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C42[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_32_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C42[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_32_s0/Q
1.834	0.122	tNET	FF	1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s/CLK
1.521	0.010	tHld		1	R42C42	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_8_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path6

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C40[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C40[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q
1.834	0.122	tNET	FF	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/CLK
1.521	0.010	tHld		1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path7

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C40[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C40[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/Q
1.834	0.122	tNET	FF	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/CLK
1.521	0.010	tHld		1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path8

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C40[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C40[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q
1.834	0.122	tNET	FF	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/CLK
1.521	0.010	tHld		1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path9

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C40[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C40[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q
1.834	0.122	tNET	FF	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s/CLK
1.521	0.010	tHld		1	R42C40	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path10

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C38[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C38[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q
1.834	0.122	tNET	FF	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
1.521	0.010	tHld		1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path11

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C38[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C38[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/Q
1.834	0.122	tNET	FF	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
1.521	0.010	tHld		1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path12

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C38[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C38[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q
1.834	0.122	tNET	FF	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
1.521	0.010	tHld		1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path13

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C38[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/CLK
1.712	0.201	tC2Q	RF	1	R43C38[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q
1.834	0.122	tNET	FF	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
1.521	0.010	tHld		1	R42C38	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path14

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_101_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_25_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R16C16[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_101_s0/CLK
1.712	0.201	tC2Q	RF	1	R16C16[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_101_s0/Q
1.834	0.122	tNET	FF	1	R15C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_25_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R15C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_25_s/CLK
1.521	0.010	tHld		1	R15C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_25_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path15

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_39_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R16C12[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_39_s0/CLK
1.712	0.201	tC2Q	RF	1	R16C12[0][B]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_39_s0/Q
1.834	0.122	tNET	FF	1	R15C12	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R15C12	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s/CLK
1.521	0.010	tHld		1	R15C12	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path16

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_36_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R16C12[0][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_36_s0/CLK
1.712	0.201	tC2Q	RF	1	R16C12[0][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_36_s0/Q
1.834	0.122	tNET	FF	1	R15C12	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R15C12	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s/CLK
1.521	0.010	tHld		1	R15C12	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_9_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path17

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_25_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R22C11[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_25_s0/CLK
1.712	0.201	tC2Q	RF	1	R22C11[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_25_s0/Q
1.834	0.122	tNET	FF	1	R23C11	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R23C11	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLK
1.521	0.010	tHld		1	R23C11	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path18

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_6_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R14C9[2][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_6_s0/CLK
1.712	0.201	tC2Q	RF	1	R14C9[2][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_6_s0/Q
1.834	0.122	tNET	FF	1	R14C10	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R14C10	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLK
1.521	0.010	tHld		1	R14C10	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path19

Path Summary:

Slack	0.315
Data Arrival Time	1.836
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C45[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0/CLK
1.713	0.202	tC2Q	RR	1	R44C45[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0/Q
1.836	0.123	tNET	RR	1	R42C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s/CLK
1.521	0.010	tHld		1	R42C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path20

Path Summary:

Slack	0.315
Data Arrival Time	1.836
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C45[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/CLK
1.713	0.202	tC2Q	RR	1	R44C45[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/Q
1.836	0.123	tNET	RR	1	R42C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s/CLK
1.521	0.010	tHld		1	R42C45	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_14_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path21

Path Summary:

Slack	0.315
Data Arrival Time	1.836
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_12_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C44[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0/CLK
1.713	0.202	tC2Q	RR	1	R44C44[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0/Q
1.836	0.123	tNET	RR	1	R42C44	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_12_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R42C44	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_12_s/CLK
1.521	0.010	tHld		1	R42C44	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_12_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path22

Path Summary:

Slack	0.315
Data Arrival Time	1.836
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_5_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C41[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/CLK
1.713	0.202	tC2Q	RR	1	R43C41[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q
1.836	0.123	tNET	RR	1	R41C41	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_5_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C41	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_5_s/CLK
1.521	0.010	tHld		1	R41C41	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_5_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path23

Path Summary:

Slack	0.315
Data Arrival Time	1.836
Data Required Time	1.521
From	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C39[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/CLK
1.713	0.202	tC2Q	RR	1	R43C39[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q
1.836	0.123	tNET	RR	1	R41C39	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C39	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLK
1.521	0.010	tHld		1	R41C39	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path24

Path Summary:

Slack	0.315
Data Arrival Time	1.836
Data Required Time	1.521
From	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_98_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R16C16[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_98_s0/CLK
1.713	0.202	tC2Q	RR	1	R16C16[1][A]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_98_s0/Q
1.836	0.123	tNET	RR	1	R14C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R14C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s/CLK
1.521	0.010	tHld		1	R14C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path25

Path Summary:

Slack	0.315
Data Arrival Time	1.836
Data Required Time	1.521
From	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_96_s0
To	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R16C16[1][B]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_96_s0/CLK
1.713	0.202	tC2Q	RR	1	R16C16[1][B]	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_96_s0/Q
1.836	0.123	tNET	RR	1	R14C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R14C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s/CLK
1.521	0.010	tHld		1	R14C16	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_24_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.257
Data Arrival Time	5.947
Data Required Time	7.204
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
5.947	1.356	tNET	FF	1	R42C16[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clkx1
5.000	0.000	tCL	FF	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	1	R42C16[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0/CLK
7.239	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0
7.204	-0.035	tSu		1	R42C16[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0

Path Statistics:

Clock Skew	-2.085
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.356, 85.387%; tC2Q: 0.232, 14.613%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.274, 100.000%

Path2

Path Summary:

Slack	1.257
Data Arrival Time	5.947
Data Required Time	7.204
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
5.947	1.356	tNET	FF	1	R44C17[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clkx1
5.000	0.000	tCL	FF	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	1	R44C17[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/CLK
7.239	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0
7.204	-0.035	tSu		1	R44C17[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0

Path Statistics:

Clock Skew	-2.085
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.356, 85.387%; tC2Q: 0.232, 14.613%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.274, 100.000%

Path3

Path Summary:

Slack	3.526
Data Arrival Time	8.675
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.675	2.115	tNET	FF	1	R42C37[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R42C37[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0
12.201	-0.035	tSu		1	R42C37[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 8.596%; route: 3.713, 86.029%; tC2Q: 0.232, 5.375%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path4

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R41C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R41C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
12.201	-0.035	tSu		1	R41C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path5

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R41C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R41C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0
12.201	-0.035	tSu		1	R41C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path6

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R45C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R45C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0
12.201	-0.035	tSu		1	R45C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path7

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R41C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R41C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
12.201	-0.035	tSu		1	R41C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path8

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R41C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R41C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
12.201	-0.035	tSu		1	R41C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path9

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R41C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R41C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0
12.201	-0.035	tSu		1	R41C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path10

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R44C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R44C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0
12.201	-0.035	tSu		1	R44C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path11

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R45C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R45C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0
12.201	-0.035	tSu		1	R45C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path12

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R44C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R44C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0
12.201	-0.035	tSu		1	R44C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path13

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R45C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R45C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
12.201	-0.035	tSu		1	R45C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path14

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R44C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R44C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
12.201	-0.035	tSu		1	R44C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path15

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R45C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R45C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
12.201	-0.035	tSu		1	R45C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path16

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R44C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R44C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
12.201	-0.035	tSu		1	R44C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path17

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R41C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R41C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0
12.201	-0.035	tSu		1	R41C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path18

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R44C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R44C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
12.201	-0.035	tSu		1	R44C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path19

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R45C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R45C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
12.201	-0.035	tSu		1	R45C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path20

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R44C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R44C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
12.201	-0.035	tSu		1	R44C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path21

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R40C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R40C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
12.201	-0.035	tSu		1	R40C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path22

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R40C35[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R40C35[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
12.201	-0.035	tSu		1	R40C35[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path23

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R45C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R45C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
12.201	-0.035	tSu		1	R45C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path24

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R45C35[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R45C35[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0
12.201	-0.035	tSu		1	R45C35[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path25

Path Summary:

Slack	3.753
Data Arrival Time	8.448
Data Required Time	12.201
From	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
2.088	2.088	tINS	RR	41	IOT27[A]	clk_ibuf/O
4.359	2.271	tNET	RR	1	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591	0.232	tC2Q	RF	3000	R29C22[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190	1.598	tNET	FF	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561	0.371	tINS	FF	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
8.448	1.888	tNET	FF	1	R40C35[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clkx1
10.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R40C35[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLK
12.236	-0.035	tUnc				u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0
12.201	-0.035	tSu		1	R40C35[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew	-2.088
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay	cell: 0.371, 9.073%; route: 3.486, 85.254%; tC2Q: 0.232, 5.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.841
Data Arrival Time	3.363
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.363	1.080	tNET	RR	1	R40C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R40C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLK
1.522	0.011	tHld		1	R40C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.740%; route: 1.340, 72.353%; tC2Q: 0.202, 10.908%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path2

Path Summary:

Slack	1.841
Data Arrival Time	3.363
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.363	1.080	tNET	RR	1	R40C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R40C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLK
1.522	0.011	tHld		1	R40C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.740%; route: 1.340, 72.353%; tC2Q: 0.202, 10.908%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path3

Path Summary:

Slack	1.841
Data Arrival Time	3.363
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.363	1.080	tNET	RR	1	R43C34[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C34[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLK
1.522	0.011	tHld		1	R43C34[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.740%; route: 1.340, 72.353%; tC2Q: 0.202, 10.908%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path4

Path Summary:

Slack	1.841
Data Arrival Time	3.363
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.363	1.080	tNET	RR	1	R43C34[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R43C34[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLK
1.522	0.011	tHld		1	R43C34[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.740%; route: 1.340, 72.353%; tC2Q: 0.202, 10.908%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path5

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R41C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/CLK
1.522	0.011	tHld		1	R41C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path6

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R41C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLK
1.522	0.011	tHld		1	R41C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path7

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R45C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R45C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLK
1.522	0.011	tHld		1	R45C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path8

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R41C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK
1.522	0.011	tHld		1	R41C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path9

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R41C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLK
1.522	0.011	tHld		1	R41C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path10

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R41C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLK
1.522	0.011	tHld		1	R41C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path11

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R44C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLK
1.522	0.011	tHld		1	R44C36[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path12

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R45C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R45C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLK
1.522	0.011	tHld		1	R45C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path13

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R44C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLK
1.522	0.011	tHld		1	R44C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path14

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R45C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R45C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK
1.522	0.011	tHld		1	R45C36[0][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path15

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R44C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK
1.522	0.011	tHld		1	R44C36[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path16

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R45C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R45C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK
1.522	0.011	tHld		1	R45C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path17

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R44C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLK
1.522	0.011	tHld		1	R44C36[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path18

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R41C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R41C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLK
1.522	0.011	tHld		1	R41C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path19

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R44C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK
1.522	0.011	tHld		1	R44C36[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path20

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R45C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R45C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK
1.522	0.011	tHld		1	R45C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path21

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R44C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R44C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLK
1.522	0.011	tHld		1	R44C36[2][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path22

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R40C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R40C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/CLK
1.522	0.011	tHld		1	R40C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path23

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R40C35[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R40C35[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK
1.522	0.011	tHld		1	R40C35[2][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path24

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R45C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R45C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK
1.522	0.011	tHld		1	R45C35[0][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path25

Path Summary:

Slack	1.851
Data Arrival Time	3.373
Data Required Time	1.522
From	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0
Launch Clk	clkx1:[R]
Latch Clk	clkx1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R24C10[1][A]	u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.974	0.260	tNET	RR	1	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.284	0.310	tINS	RR	40	R25C11[3][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
3.373	1.089	tNET	RR	1	R45C35[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx1
0.000	0.000	tCL	RR	3728	BOTTOMSIDE[0]	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R45C35[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLK
1.522	0.011	tHld		1	R45C35[1][B]	u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.310, 16.650%; route: 1.350, 72.500%; tC2Q: 0.202, 10.850%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	led_cnt_31_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	led_cnt_31_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	led_cnt_31_s0/CLK

MPW2

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	led_cnt_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	led_cnt_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	led_cnt_24_s0/CLK

MPW3

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	led_cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	led_cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	led_cnt_16_s0/CLK

MPW4

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	led_cnt_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	led_cnt_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	led_cnt_12_s0/CLK

MPW5

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	led_cnt_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	led_cnt_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	led_cnt_10_s0/CLK

MPW6

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	led_cnt_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	led_cnt_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	led_cnt_9_s0/CLK

MPW7

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	u_rd/app_rd_data_r_74_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	u_rd/app_rd_data_r_74_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	u_rd/app_rd_data_r_74_s0/CLK

MPW8

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	u_rd/app_rd_data_rr_75_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	u_rd/app_rd_data_rr_75_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	u_rd/app_rd_data_rr_75_s0/CLK

MPW9

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	u_ddr3/gw3_top/u_gwmc_top/mc_address_dly_50_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/mc_address_dly_50_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/mc_address_dly_50_s0/CLK

MPW10

MPW Summary:

Slack:	3.237
Actual Width:	4.237
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clkx1
Objects:	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_93_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clkx1
5.000	0.000	tCL	FF	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274	2.274	tNET	FF	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_93_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clkx1
10.000	0.000	tCL	RR	u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511	1.511	tNET	RR	u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_93_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3728	clk_x1	3.086	2.274
3000	ddr_rst	1.041	1.598
148	dqsts1	6.940	2.223
147	dqs_reg	7.145	2.039
145	n28_3	5.563	1.583
87	mc_wrdata_dly_0_9	4.132	2.242
87	mc_wrdata_dly_0_10	3.086	2.959
82	mc_wrdata_dly_0_5	8.047	1.686
74	n107_10	3.086	3.806
70	n14_4	5.647	1.477

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C16	90.28%
R22C20	90.28%
R41C36	87.50%
R31C11	86.11%
R27C18	86.11%
R39C12	86.11%
R29C26	84.72%
R26C16	84.72%
R26C17	84.72%
R14C9	83.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk_x4 -period 2.857 -waveform {0 1.429} [get_nets {clk_x4}]
TC_CLOCK	Actived	create_clock -name clkx1 -period 10 -waveform {0 5} [get_pins {u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_x4}] -to [get_clocks {clkx1}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clkx1}] -to [get_clocks {clk_x4}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clkx1}] -to [get_clocks {clkin}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clkin}] -to [get_clocks {clk_x4}]