Power Messages

Report Title	Power Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.cst
Timing Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.sdc
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Device Version	C
Created Time	Fri Feb 28 17:08:40 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	306.011
Quiescent Power (mW)	121.044
Dynamic Power (mW)	184.967

Thermal Information:

Junction Temperature	34.798
Theta JA	32.020
Max Allowed Ambient Temperature	75.202

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	1.000	134.901	69.936	204.837
VCCX	3.300	10.202	15.000	83.167
VCCIO15	1.500	9.654	0.852	15.758
VCCIO33	3.300	0.582	0.100	2.249

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	5.807	NA	12.387
IO	72.272	10.445	50.554
PLL	36.611	NA	NA
DLL	80.644	NA	NA
DQS	207.458	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	330.520	330.520(330.431)
top/u_ddr3/	292.880	292.880(292.880)
top/u_ddr3/gw3_top/	292.880	292.880(292.880)
top/u_ddr3/gw3_top/u_ddr_phy_top/	291.353	291.353(210.400)
top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/	0.039	0.039(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/	0.882	0.882(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/	208.511	208.511(208.492)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/	104.132	104.132(103.909)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/	103.810	103.810(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/	0.099	0.099(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/	104.124	104.124(103.902)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/	103.803	103.803(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/	0.099	0.099(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/	0.039	0.039(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/	0.039	0.039(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/	0.157	0.157(0.097)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/	0.097	0.097(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/	0.000	0.000(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib/	0.324	0.324(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/	0.128	0.128(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/	0.515	0.515(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/	1.527	1.527(1.219)
top/u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/	0.197	0.197(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/	0.530	0.530(0.303)
top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/	0.303	0.303(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/	0.395	0.395(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_rank_ctrl/	0.067	0.067(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_timing_ctrl/	0.031	0.031(0.000)
top/u_rd/	0.940	0.940(0.000)
top/upll/	36.611	36.611(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
clkx1	100.000	5.792
NO CLOCK DOMAIN	0.000	0.000
clkin	50.000	36.657
clk_x4	350.017	288.150