Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\button.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_memory_interface\ddr3_memory_interface.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddrtest.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\gowin_rpll\gowin_rpll.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Fri Feb 28 16:02:06 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.762s, Peak memory usage = 268.086MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 268.086MB
    Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 268.086MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 268.086MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 268.086MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 268.086MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 268.086MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 268.086MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 268.086MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 268.086MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 268.086MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 286.051MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 286.629MB
Generate output files:
    CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 293.832MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 293.832MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 53
I/O Buf 50
    IBUF 1
    OBUF 28
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 3586
    DFF 137
    DFFS 1
    DFFR 1
    DFFP 55
    DFFPE 12
    DFFC 2816
    DFFCE 564
LUT 2321
    LUT2 431
    LUT3 738
    LUT4 1152
ALU 245
    ALU 245
SSRAM 120
    RAM16S4 44
    RAM16SDP4 76
INV 22
    INV 22
IOLOGIC 76
    IDES8_MEM 16
    OSER8 24
    OSER8_MEM 20
    IODELAY 16
CLOCK 5
    CLKDIV 1
    DQS 2
    DHCEN 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3308(2343 LUT, 245 ALU, 120 RAM16) / 20736 16%
Register 3586 / 16173 23%
  --Register as Latch 0 / 16173 0%
  --Register as FF 3586 / 16173 23%
BSRAM 0 / 46 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
2 upll/rpll_inst/CLKOUT.default_gen_clk Generated 2.857 350.000 0.000 1.429 clk_ibuf/I clk upll/rpll_inst/CLKOUT
3 upll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.857 350.000 0.000 1.429 clk_ibuf/I clk upll/rpll_inst/CLKOUTP
4 upll/rpll_inst/CLKOUTD.default_gen_clk Generated 5.714 175.000 0.000 2.857 clk_ibuf/I clk upll/rpll_inst/CLKOUTD
5 upll/rpll_inst/CLKOUTD3.default_gen_clk Generated 8.571 116.667 0.000 4.286 clk_ibuf/I clk upll/rpll_inst/CLKOUTD3
6 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 11.429 87.500 0.000 5.714 upll/rpll_inst/CLKOUT upll/rpll_inst/CLKOUT.default_gen_clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 172.891(MHz) 6 TOP
2 upll/rpll_inst/CLKOUT.default_gen_clk 350.000(MHz) 1030.928(MHz) 1 TOP
3 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 87.500(MHz) 130.736(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -2.026
Data Arrival Time 25.515
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
20.592 0.232 tC2Q RF 3000 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
21.621 0.555 tINS FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
22.095 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
22.548 0.453 tINS FF 14 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
23.022 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0
23.539 0.517 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F
24.013 0.474 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1
24.583 0.570 tINS FR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT
24.583 0.000 tNET RR 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN
24.618 0.035 tINS RF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT
24.618 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN
24.653 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT
24.653 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN
24.689 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT
24.689 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN
24.724 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT
24.724 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN
24.759 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT
24.759 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN
24.794 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT
24.794 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN
24.829 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT
24.829 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN
24.865 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
24.865 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
24.900 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
24.900 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
24.935 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
24.935 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
24.970 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
24.970 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
25.005 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
25.005 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
25.041 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
25.515 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s/DI[1]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 3728 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_0_7_s
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.553, 49.521%; route: 2.370, 45.978%; tC2Q: 0.232, 4.501%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -1.224
Data Arrival Time 24.712
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
20.592 0.232 tC2Q RF 2 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/I3
21.437 0.371 tINS FF 2 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/F
21.911 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/I2
22.364 0.453 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/F
22.838 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/I3
23.209 0.371 tINS FF 5 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/F
23.683 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1314_s3/I1
24.238 0.555 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1314_s3/F
24.712 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 3728 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.750, 40.211%; route: 2.370, 54.458%; tC2Q: 0.232, 5.331%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -1.186
Data Arrival Time 24.674
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
20.592 0.232 tC2Q RF 2 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/I3
21.437 0.371 tINS FF 2 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/F
21.911 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/I2
22.364 0.453 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/F
22.838 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/I3
23.209 0.371 tINS FF 5 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/F
23.683 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1310_s3/I0
24.200 0.517 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1310_s3/F
24.674 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 3728 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.712, 39.685%; route: 2.370, 54.937%; tC2Q: 0.232, 5.378%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -1.186
Data Arrival Time 24.674
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
20.592 0.232 tC2Q RF 2 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/I3
21.437 0.371 tINS FF 2 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/F
21.911 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/I2
22.364 0.453 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/F
22.838 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/I3
23.209 0.371 tINS FF 5 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/F
23.683 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1313_s3/I0
24.200 0.517 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1313_s3/F
24.674 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 3728 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.712, 39.685%; route: 2.370, 54.937%; tC2Q: 0.232, 5.378%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -1.040
Data Arrival Time 24.528
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_state_1_s10
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
20.592 0.232 tC2Q RF 2 u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/I3
21.437 0.371 tINS FF 2 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s29/F
21.911 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/I2
22.364 0.453 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_0_s28/F
22.838 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/I3
23.209 0.371 tINS FF 5 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s5/F
23.683 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_1_s27/I3
24.054 0.371 tINS FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state_1_s27/F
24.528 0.474 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_state_1_s10/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 3728 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_state_1_s10/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_state_1_s10
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/init_state_1_s10
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.566, 37.572%; route: 2.370, 56.862%; tC2Q: 0.232, 5.566%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%