Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_2\ddr3_1_2code.v D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_2\DDR3_TOP.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Thu Feb 13 15:38:59 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR3_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.618s, Peak memory usage = 140.543MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 140.543MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 140.543MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 140.543MB Optimizing Phase 2: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.248s, Peak memory usage = 140.543MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.169s, Peak memory usage = 140.543MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 140.543MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 140.543MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 140.543MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.189s, Peak memory usage = 140.543MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 140.543MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 140.543MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 163.195MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.282s, Peak memory usage = 163.195MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 163.195MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 163.195MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 234 |
| I/O Buf | 229 |
| IBUF | 111 |
| OBUF | 99 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 1706 |
| DFF | 55 |
| DFFE | 4 |
| DFFR | 1 |
| DFFP | 54 |
| DFFPE | 12 |
| DFFC | 1162 |
| DFFCE | 418 |
| LUT | 1757 |
| LUT2 | 402 |
| LUT3 | 549 |
| LUT4 | 806 |
| ALU | 145 |
| ALU | 145 |
| SSRAM | 62 |
| RAM16S4 | 23 |
| RAM16SDP4 | 39 |
| INV | 22 |
| INV | 22 |
| IOLOGIC | 76 |
| IDES4_MEM | 16 |
| OSER4 | 24 |
| OSER4_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 4 |
| SDPB | 2 |
| SDPX9B | 2 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DHCEN | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2296(1779 LUT, 145 ALU, 62 RAM16) / 20736 | 12% |
| Register | 1706 / 16173 | 11% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 1706 / 16173 | 11% |
| BSRAM | 4 / 46 | 9% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | memory_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| 2 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 3 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.000(MHz) | 1030.929(MHz) | 1 | TOP |
| 2 | clk | 100.000(MHz) | 184.638(MHz) | 6 | TOP |
| 3 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.000(MHz) | 115.457(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.176 |
| Data Arrival Time | 2.436 |
| Data Required Time | 5.612 |
| From | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0 |
| To | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 1799 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.474 | 0.474 | tNET | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 5.660 | 0.186 | tINS | FF | 64 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 6.134 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.099 | -0.035 | tUnc | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.612 | -0.487 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.433 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 3.176 |
| Data Arrival Time | 2.436 |
| Data Required Time | 5.612 |
| From | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0 |
| To | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 1799 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.474 | 0.474 | tNET | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 5.660 | 0.186 | tINS | FF | 64 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 6.134 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.099 | -0.035 | tUnc | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.612 | -0.487 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.433 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 4.187 |
| Data Arrival Time | 1.066 |
| Data Required Time | 5.253 |
| From | u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0 |
| To | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
| Launch Clk | clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 1 | u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.474 | 0.474 | tNET | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 5.439 | -0.035 | tUnc | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen | ||
| 5.253 | -0.186 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
| Clock Skew: | 0.114 |
| Setup Relationship: | 5.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 4.584 |
| Data Arrival Time | 5.741 |
| Data Required Time | 10.325 |
| From | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1 |
| To | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 5 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n53_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n53_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n50_s2/I3 |
| 2.466 | 0.371 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n50_s2/F |
| 2.940 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n48_s2/I2 |
| 3.393 | 0.453 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n48_s2/F |
| 3.867 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n45_s2/I3 |
| 4.238 | 0.371 | tINS | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n45_s2/F |
| 4.712 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n45_s3/I1 |
| 5.267 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n45_s3/F |
| 5.741 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.305, 42.836%; route: 2.844, 52.853%; tC2Q: 0.232, 4.311% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 4.686 |
| Data Arrival Time | 5.639 |
| Data Required Time | 10.325 |
| From | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1 |
| To | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 5 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_1_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n53_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n53_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n50_s2/I3 |
| 2.466 | 0.371 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n50_s2/F |
| 2.940 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n48_s2/I2 |
| 3.393 | 0.453 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n48_s2/F |
| 3.867 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n45_s2/I3 |
| 4.238 | 0.371 | tINS | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n45_s2/F |
| 4.712 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n44_s3/I2 |
| 5.165 | 0.453 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n44_s3/F |
| 5.639 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.203, 41.731%; route: 2.844, 53.874%; tC2Q: 0.232, 4.395% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |