Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gwsynthesis\ddr3_ref_design.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.sdc
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Feb 28 17:19:00 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	11586
Numbers of Endpoints Analyzed	7623
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk_in_osc_50	Base	20.000	50.000	0.000	10.000			clk
2	memory_clk	Base	5.000	200.000	0.000	2.500			pll/rpll_inst/CLKOUT
3	clk_user	Generated	10.000	100.000	0.000	5.000	pll/rpll_inst/CLKOUT	memory_clk	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
4	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_ibuf/I
5	pll/rpll_inst/CLKOUTP.default_gen_clk	Generated	5.000	200.000	0.000	2.500	clk_ibuf/I	clk_in_osc_50	pll/rpll_inst/CLKOUTP
6	pll/rpll_inst/CLKOUTD.default_gen_clk	Generated	10.000	100.000	0.000	5.000	clk_ibuf/I	clk_in_osc_50	pll/rpll_inst/CLKOUTD
7	pll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	15.000	66.667	0.000	7.500	clk_ibuf/I	clk_in_osc_50	pll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk_in_osc_50	50.000(MHz)	222.534(MHz)	6	TOP
2	memory_clk	200.000(MHz)	2016.129(MHz)	1	TOP
3	clk_user	100.000(MHz)	103.769(MHz)	8	TOP
4	tck_pad_i	20.000(MHz)	133.570(MHz)	6	TOP

No timing paths to get frequency of pll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pll/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_in_osc_50	Setup	0.000	0
clk_in_osc_50	Hold	0.000	0
memory_clk	Setup	0.000	0
memory_clk	Hold	0.000	0
clk_user	Setup	0.000	0
clk_user	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
pll/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
pll/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
pll/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
pll/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
pll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
pll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.363	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_48_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.602
2	0.413	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_47_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.552
3	0.437	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_57_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.528
4	0.454	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_46_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.511
5	0.467	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_60_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.498
6	0.480	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_56_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.485
7	0.498	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_5_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.467
8	0.515	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_54_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.450
9	0.515	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_52_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.450
10	0.515	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_45_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.450
11	0.522	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_24_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.443
12	0.591	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_51_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.374
13	0.591	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_55_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.374
14	0.609	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_8_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.356
15	0.612	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_49_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.353
16	0.612	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_50_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.353
17	0.612	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_53_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.353
18	0.612	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_58_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.353
19	0.643	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_38_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.322
20	0.643	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_61_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.322
21	0.688	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_wren_s0/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.277
22	0.689	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_36_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.276
23	0.713	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_59_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.252
24	0.713	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_63_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.252
25	0.715	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q	u_rd/app_wdf_data_26_s1/D	clk_user:[R]	clk_user:[R]	10.000	0.000	9.250

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.074	u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15]	clk_user:[R]	clk_user:[R]	0.000	0.000	0.323
2	0.074	u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]	clk_user:[R]	clk_user:[R]	0.000	0.000	0.323
3	0.213	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[6]	clk_user:[R]	clk_user:[R]	0.000	0.000	0.331
4	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0]	clk_user:[R]	clk_user:[R]	0.000	0.000	0.462
5	0.225	u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]	clk_user:[R]	clk_user:[R]	0.000	0.000	0.474
6	0.307	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_29_s0/Q	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_1_29_s0/D	clk_user:[R]	clk_user:[R]	0.000	0.000	0.318
7	0.307	u_la0_top/rst_ao_syn_s0/Q	u_la0_top/rst_ao_s0/D	clk_user:[R]	clk_user:[R]	0.000	0.000	0.318
8	0.307	u_la0_top/data_register_27_s0/Q	u_la0_top/data_register_26_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
9	0.307	u_la0_top/data_register_28_s0/Q	u_la0_top/data_register_27_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
10	0.307	u_la0_top/data_register_30_s0/Q	u_la0_top/data_register_29_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
11	0.307	u_la0_top/data_register_32_s0/Q	u_la0_top/data_register_31_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
12	0.307	u_la0_top/data_register_34_s0/Q	u_la0_top/data_register_33_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
13	0.307	u_la0_top/data_register_35_s0/Q	u_la0_top/data_register_34_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
14	0.307	u_la0_top/data_register_40_s0/Q	u_la0_top/data_register_39_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
15	0.307	u_la0_top/data_register_42_s0/Q	u_la0_top/data_register_41_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
16	0.307	u_la0_top/data_register_46_s0/Q	u_la0_top/data_register_45_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
17	0.307	u_la0_top/data_register_48_s0/Q	u_la0_top/data_register_47_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.318
18	0.310	u_la0_top/data_register_7_s0/Q	u_la0_top/data_register_6_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.321
19	0.310	u_la0_top/data_register_53_s0/Q	u_la0_top/data_register_52_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.321
20	0.310	u_la0_top/data_register_54_s0/Q	u_la0_top/data_register_53_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.321
21	0.310	u_la0_top/data_register_56_s0/Q	u_la0_top/data_register_55_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.321
22	0.310	u_la0_top/data_register_59_s0/Q	u_la0_top/data_register_58_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.321
23	0.310	u_la0_top/data_register_62_s0/Q	u_la0_top/data_register_61_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.321
24	0.313	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/mux_addr_8_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[16].mem0_cmd_fifo_gen[16].mem0_0_11_s/DI[2]	clk_user:[R]	clk_user:[R]	0.000	0.000	0.323
25	0.313	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[3].Q_data0_1_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_0_s23/DI[3]	clk_user:[R]	clk_user:[R]	0.000	0.000	0.323

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
2	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
3	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
4	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_4_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
5	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
6	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
7	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
8	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_5_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
9	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_4_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
10	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
11	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
12	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
13	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_5_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
14	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
15	7.817	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET	clk_user:[R]	clk_user:[R]	10.000	0.000	2.148
16	7.825	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_5_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.140
17	7.825	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.140
18	7.956	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.009
19	7.956	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.009
20	7.956	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	2.009
21	8.082	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_4_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	1.883
22	8.082	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	1.883
23	8.082	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	1.883
24	8.082	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	1.883
25	8.082	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR	clk_user:[R]	clk_user:[R]	10.000	0.000	1.883

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.487	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.498
2	0.487	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.498
3	0.487	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.498
4	0.593	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.604
5	0.593	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.604
6	0.599	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_4_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.610
7	0.599	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_5_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.610
8	0.599	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_9_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.610
9	0.599	u_la0_top/rst_ao_s0/Q	u_la0_top/start_reg_s0/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.610
10	0.599	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.610
11	0.608	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.619
12	0.611	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.622
13	0.611	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.622
14	0.611	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.622
15	0.611	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.622
16	0.611	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_6_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.622
17	0.611	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_2_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.622
18	0.611	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_3_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.622
19	0.612	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.623
20	0.612	u_la0_top/rst_ao_s0/Q	u_la0_top/trigger_seq_start_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.623
21	0.612	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.623
22	0.612	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_1_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.623
23	0.612	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_3_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.623
24	0.614	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.625
25	0.614	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk_user:[R]	clk_user:[R]	0.000	0.000	0.625

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/wloadn_1_s0
2	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0
3	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0
4	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/recalib_s_1_s0
5	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_2_s0
6	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1
7	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1
8	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0
9	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1
10	0.837	1.837	1.000	High Pulse Width	clk_in_osc_50	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.363
Data Arrival Time	11.873
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_48_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.411	0.906	tNET	FF	1	R16C27[1][B]	u_rd/n691_s0/I0
11.873	0.462	tINS	FR	1	R16C27[1][B]	u_rd/n691_s0/F
11.873	0.000	tNET	RR	1	R16C27[1][B]	u_rd/app_wdf_data_48_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C27[1][B]	u_rd/app_wdf_data_48_s1/CLK
12.236	-0.035	tSu		1	R16C27[1][B]	u_rd/app_wdf_data_48_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.731, 38.858%; route: 5.639, 58.726%; tC2Q: 0.232, 2.416%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path2

Path Summary:

Slack	0.413
Data Arrival Time	11.823
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_47_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.253	0.748	tNET	FF	1	R16C27[2][A]	u_rd/n692_s0/I0
11.823	0.570	tINS	FR	1	R16C27[2][A]	u_rd/n692_s0/F
11.823	0.000	tNET	RR	1	R16C27[2][A]	u_rd/app_wdf_data_47_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C27[2][A]	u_rd/app_wdf_data_47_s1/CLK
12.236	-0.035	tSu		1	R16C27[2][A]	u_rd/app_wdf_data_47_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.839, 40.190%; route: 5.481, 57.381%; tC2Q: 0.232, 2.429%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path3

Path Summary:

Slack	0.437
Data Arrival Time	11.799
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_57_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.229	0.724	tNET	FF	1	R14C27[2][B]	u_rd/n682_s0/I0
11.799	0.570	tINS	FR	1	R14C27[2][B]	u_rd/n682_s0/F
11.799	0.000	tNET	RR	1	R14C27[2][B]	u_rd/app_wdf_data_57_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R14C27[2][B]	u_rd/app_wdf_data_57_s1/CLK
12.236	-0.035	tSu		1	R14C27[2][B]	u_rd/app_wdf_data_57_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.839, 40.292%; route: 5.457, 57.273%; tC2Q: 0.232, 2.435%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path4

Path Summary:

Slack	0.454
Data Arrival Time	11.782
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_46_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.411	0.906	tNET	FF	1	R16C27[2][B]	u_rd/n693_s0/I1
11.782	0.371	tINS	FF	1	R16C27[2][B]	u_rd/n693_s0/F
11.782	0.000	tNET	FF	1	R16C27[2][B]	u_rd/app_wdf_data_46_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C27[2][B]	u_rd/app_wdf_data_46_s1/CLK
12.236	-0.035	tSu		1	R16C27[2][B]	u_rd/app_wdf_data_46_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.640, 38.273%; route: 5.639, 59.288%; tC2Q: 0.232, 2.439%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path5

Path Summary:

Slack	0.467
Data Arrival Time	11.769
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_60_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.220	0.715	tNET	FF	1	R13C29[2][A]	u_rd/n679_s0/I0
11.769	0.549	tINS	FR	1	R13C29[2][A]	u_rd/n679_s0/F
11.769	0.000	tNET	RR	1	R13C29[2][A]	u_rd/app_wdf_data_60_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C29[2][A]	u_rd/app_wdf_data_60_s1/CLK
12.236	-0.035	tSu		1	R13C29[2][A]	u_rd/app_wdf_data_60_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 40.198%; route: 5.448, 57.359%; tC2Q: 0.232, 2.443%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path6

Path Summary:

Slack	0.480
Data Arrival Time	11.756
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_56_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.186	0.681	tNET	FF	1	R14C28[2][B]	u_rd/n683_s0/I0
11.756	0.570	tINS	FR	1	R14C28[2][B]	u_rd/n683_s0/F
11.756	0.000	tNET	RR	1	R14C28[2][B]	u_rd/app_wdf_data_56_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R14C28[2][B]	u_rd/app_wdf_data_56_s1/CLK
12.236	-0.035	tSu		1	R14C28[2][B]	u_rd/app_wdf_data_56_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.839, 40.476%; route: 5.414, 57.078%; tC2Q: 0.232, 2.446%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path7

Path Summary:

Slack	0.498
Data Arrival Time	11.738
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_5_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
10.117	0.625	tNET	FF	1	R13C32[1][B]	u_rd/n608_s1/I1
10.488	0.371	tINS	FF	11	R13C32[1][B]	u_rd/n608_s1/F
11.189	0.702	tNET	FF	1	R16C33[1][B]	u_rd/n734_s0/I1
11.738	0.549	tINS	FR	1	R16C33[1][B]	u_rd/n734_s0/F
11.738	0.000	tNET	RR	1	R16C33[1][B]	u_rd/app_wdf_data_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C33[1][B]	u_rd/app_wdf_data_5_s1/CLK
12.236	-0.035	tSu		1	R16C33[1][B]	u_rd/app_wdf_data_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.634, 38.387%; route: 5.601, 59.163%; tC2Q: 0.232, 2.451%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path8

Path Summary:

Slack	0.515
Data Arrival Time	11.721
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_54_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.259	0.754	tNET	FF	1	R13C27[0][B]	u_rd/n685_s0/I0
11.721	0.462	tINS	FR	1	R13C27[0][B]	u_rd/n685_s0/F
11.721	0.000	tNET	RR	1	R13C27[0][B]	u_rd/app_wdf_data_54_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C27[0][B]	u_rd/app_wdf_data_54_s1/CLK
12.236	-0.035	tSu		1	R13C27[0][B]	u_rd/app_wdf_data_54_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.731, 39.483%; route: 5.487, 58.062%; tC2Q: 0.232, 2.455%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path9

Path Summary:

Slack	0.515
Data Arrival Time	11.721
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_52_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.259	0.754	tNET	FF	1	R13C27[1][B]	u_rd/n687_s0/I0
11.721	0.462	tINS	FR	1	R13C27[1][B]	u_rd/n687_s0/F
11.721	0.000	tNET	RR	1	R13C27[1][B]	u_rd/app_wdf_data_52_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C27[1][B]	u_rd/app_wdf_data_52_s1/CLK
12.236	-0.035	tSu		1	R13C27[1][B]	u_rd/app_wdf_data_52_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.731, 39.483%; route: 5.487, 58.062%; tC2Q: 0.232, 2.455%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path10

Path Summary:

Slack	0.515
Data Arrival Time	11.721
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_45_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.259	0.754	tNET	FF	1	R13C27[1][A]	u_rd/n694_s1/I0
11.721	0.462	tINS	FR	1	R13C27[1][A]	u_rd/n694_s1/F
11.721	0.000	tNET	RR	1	R13C27[1][A]	u_rd/app_wdf_data_45_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C27[1][A]	u_rd/app_wdf_data_45_s1/CLK
12.236	-0.035	tSu		1	R13C27[1][A]	u_rd/app_wdf_data_45_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.731, 39.483%; route: 5.487, 58.062%; tC2Q: 0.232, 2.455%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path11

Path Summary:

Slack	0.522
Data Arrival Time	11.714
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_24_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
10.117	0.625	tNET	FF	1	R13C32[1][B]	u_rd/n608_s1/I1
10.488	0.371	tINS	FF	11	R13C32[1][B]	u_rd/n608_s1/F
11.165	0.678	tNET	FF	1	R16C31[0][B]	u_rd/n715_s0/I0
11.714	0.549	tINS	FR	1	R16C31[0][B]	u_rd/n715_s0/F
11.714	0.000	tNET	RR	1	R16C31[0][B]	u_rd/app_wdf_data_24_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C31[0][B]	u_rd/app_wdf_data_24_s1/CLK
12.236	-0.035	tSu		1	R16C31[0][B]	u_rd/app_wdf_data_24_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.634, 38.483%; route: 5.577, 59.060%; tC2Q: 0.232, 2.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path12

Path Summary:

Slack	0.591
Data Arrival Time	11.645
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_51_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.075	0.569	tNET	FF	1	R16C28[2][B]	u_rd/n688_s0/I0
11.645	0.570	tINS	FR	1	R16C28[2][B]	u_rd/n688_s0/F
11.645	0.000	tNET	RR	1	R16C28[2][B]	u_rd/app_wdf_data_51_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C28[2][B]	u_rd/app_wdf_data_51_s1/CLK
12.236	-0.035	tSu		1	R16C28[2][B]	u_rd/app_wdf_data_51_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.839, 40.955%; route: 5.303, 56.570%; tC2Q: 0.232, 2.475%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path13

Path Summary:

Slack	0.591
Data Arrival Time	11.645
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_55_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.075	0.569	tNET	FF	1	R13C28[2][B]	u_rd/n684_s0/I0
11.645	0.570	tINS	FR	1	R13C28[2][B]	u_rd/n684_s0/F
11.645	0.000	tNET	RR	1	R13C28[2][B]	u_rd/app_wdf_data_55_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C28[2][B]	u_rd/app_wdf_data_55_s1/CLK
12.236	-0.035	tSu		1	R13C28[2][B]	u_rd/app_wdf_data_55_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.839, 40.955%; route: 5.303, 56.570%; tC2Q: 0.232, 2.475%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path14

Path Summary:

Slack	0.609
Data Arrival Time	11.627
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_8_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
10.117	0.625	tNET	FF	1	R13C32[1][B]	u_rd/n608_s1/I1
10.488	0.371	tINS	FF	11	R13C32[1][B]	u_rd/n608_s1/F
11.165	0.678	tNET	FF	1	R16C33[0][A]	u_rd/n731_s0/I0
11.627	0.462	tINS	FR	1	R16C33[0][A]	u_rd/n731_s0/F
11.627	0.000	tNET	RR	1	R16C33[0][A]	u_rd/app_wdf_data_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C33[0][A]	u_rd/app_wdf_data_8_s1/CLK
12.236	-0.035	tSu		1	R16C33[0][A]	u_rd/app_wdf_data_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.547, 37.911%; route: 5.577, 59.609%; tC2Q: 0.232, 2.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path15

Path Summary:

Slack	0.612
Data Arrival Time	11.624
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_49_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.075	0.569	tNET	FF	1	R16C28[0][B]	u_rd/n690_s0/I0
11.624	0.549	tINS	FR	1	R16C28[0][B]	u_rd/n690_s0/F
11.624	0.000	tNET	RR	1	R16C28[0][B]	u_rd/app_wdf_data_49_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C28[0][B]	u_rd/app_wdf_data_49_s1/CLK
12.236	-0.035	tSu		1	R16C28[0][B]	u_rd/app_wdf_data_49_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 40.823%; route: 5.303, 56.697%; tC2Q: 0.232, 2.481%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path16

Path Summary:

Slack	0.612
Data Arrival Time	11.624
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_50_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.075	0.569	tNET	FF	1	R16C28[0][A]	u_rd/n689_s0/I0
11.624	0.549	tINS	FR	1	R16C28[0][A]	u_rd/n689_s0/F
11.624	0.000	tNET	RR	1	R16C28[0][A]	u_rd/app_wdf_data_50_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C28[0][A]	u_rd/app_wdf_data_50_s1/CLK
12.236	-0.035	tSu		1	R16C28[0][A]	u_rd/app_wdf_data_50_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 40.823%; route: 5.303, 56.697%; tC2Q: 0.232, 2.481%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path17

Path Summary:

Slack	0.612
Data Arrival Time	11.624
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_53_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.075	0.569	tNET	FF	1	R13C28[0][A]	u_rd/n686_s0/I0
11.624	0.549	tINS	FR	1	R13C28[0][A]	u_rd/n686_s0/F
11.624	0.000	tNET	RR	1	R13C28[0][A]	u_rd/app_wdf_data_53_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C28[0][A]	u_rd/app_wdf_data_53_s1/CLK
12.236	-0.035	tSu		1	R13C28[0][A]	u_rd/app_wdf_data_53_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 40.823%; route: 5.303, 56.697%; tC2Q: 0.232, 2.481%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path18

Path Summary:

Slack	0.612
Data Arrival Time	11.624
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_58_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.075	0.569	tNET	FF	1	R13C28[1][B]	u_rd/n681_s0/I0
11.624	0.549	tINS	FR	1	R13C28[1][B]	u_rd/n681_s0/F
11.624	0.000	tNET	RR	1	R13C28[1][B]	u_rd/app_wdf_data_58_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C28[1][B]	u_rd/app_wdf_data_58_s1/CLK
12.236	-0.035	tSu		1	R13C28[1][B]	u_rd/app_wdf_data_58_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 40.823%; route: 5.303, 56.697%; tC2Q: 0.232, 2.481%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path19

Path Summary:

Slack	0.643
Data Arrival Time	11.594
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_38_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.223	0.717	tNET	FF	1	R13C29[2][B]	u_rd/n701_s0/I0
11.594	0.371	tINS	FF	1	R13C29[2][B]	u_rd/n701_s0/F
11.594	0.000	tNET	FF	1	R13C29[2][B]	u_rd/app_wdf_data_38_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C29[2][B]	u_rd/app_wdf_data_38_s1/CLK
12.236	-0.035	tSu		1	R13C29[2][B]	u_rd/app_wdf_data_38_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.640, 39.046%; route: 5.450, 58.466%; tC2Q: 0.232, 2.489%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path20

Path Summary:

Slack	0.643
Data Arrival Time	11.594
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_61_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
11.223	0.717	tNET	FF	1	R13C29[1][B]	u_rd/n678_s0/I0
11.594	0.371	tINS	FF	1	R13C29[1][B]	u_rd/n678_s0/F
11.594	0.000	tNET	FF	1	R13C29[1][B]	u_rd/app_wdf_data_61_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C29[1][B]	u_rd/app_wdf_data_61_s1/CLK
12.236	-0.035	tSu		1	R13C29[1][B]	u_rd/app_wdf_data_61_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.640, 39.046%; route: 5.450, 58.466%; tC2Q: 0.232, 2.489%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path21

Path Summary:

Slack	0.688
Data Arrival Time	11.548
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_wren_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
10.117	0.625	tNET	FF	1	R13C32[1][B]	u_rd/n608_s1/I1
10.488	0.371	tINS	FF	11	R13C32[1][B]	u_rd/n608_s1/F
11.548	1.061	tNET	FF	1	R14C36[2][A]	u_rd/app_wdf_wren_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R14C36[2][A]	u_rd/app_wdf_wren_s0/CLK
12.236	-0.035	tSu		1	R14C36[2][A]	u_rd/app_wdf_wren_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.085, 33.254%; route: 5.960, 64.245%; tC2Q: 0.232, 2.501%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path22

Path Summary:

Slack	0.689
Data Arrival Time	11.548
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_36_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
10.978	0.472	tNET	FF	1	R14C29[2][B]	u_rd/n703_s0/I1
11.548	0.570	tINS	FR	1	R14C29[2][B]	u_rd/n703_s0/F
11.548	0.000	tNET	RR	1	R14C29[2][B]	u_rd/app_wdf_data_36_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R14C29[2][B]	u_rd/app_wdf_data_36_s1/CLK
12.236	-0.035	tSu		1	R14C29[2][B]	u_rd/app_wdf_data_36_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.839, 41.385%; route: 5.205, 56.114%; tC2Q: 0.232, 2.501%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path23

Path Summary:

Slack	0.713
Data Arrival Time	11.523
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_59_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
10.974	0.469	tNET	FF	1	R13C30[2][A]	u_rd/n680_s0/I0
11.523	0.549	tINS	FR	1	R13C30[2][A]	u_rd/n680_s0/F
11.523	0.000	tNET	RR	1	R13C30[2][A]	u_rd/app_wdf_data_59_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C30[2][A]	u_rd/app_wdf_data_59_s1/CLK
12.236	-0.035	tSu		1	R13C30[2][A]	u_rd/app_wdf_data_59_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 41.267%; route: 5.202, 56.225%; tC2Q: 0.232, 2.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path24

Path Summary:

Slack	0.713
Data Arrival Time	11.523
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_63_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
10.974	0.469	tNET	FF	1	R13C30[0][B]	u_rd/n676_s0/I0
11.523	0.549	tINS	FR	1	R13C30[0][B]	u_rd/n676_s0/F
11.523	0.000	tNET	RR	1	R13C30[0][B]	u_rd/app_wdf_data_63_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R13C30[0][B]	u_rd/app_wdf_data_63_s1/CLK
12.236	-0.035	tSu		1	R13C30[0][B]	u_rd/app_wdf_data_63_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 41.267%; route: 5.202, 56.225%; tC2Q: 0.232, 2.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path25

Path Summary:

Slack	0.715
Data Arrival Time	11.521
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0
To	u_rd/app_wdf_data_26_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/CLK
2.503	0.232	tC2Q	RF	14	R20C41[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_buf_wptr_1_s0/Q
3.427	0.924	tNET	FF	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/I0
3.997	0.570	tINS	FR	1	R17C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s2/F
4.170	0.172	tNET	RR	1	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I1
4.687	0.517	tINS	RF	4	R18C39[3][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
6.087	1.401	tNET	FF	1	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/I1
6.604	0.517	tINS	FF	5	R21C14[1][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/cmd_ready_d_s/F
7.953	1.349	tNET	FF	1	R13C38[1][B]	u_rd/app_cmd_0_s4/I0
8.508	0.555	tINS	FF	4	R13C38[1][B]	u_rd/app_cmd_0_s4/F
8.936	0.428	tNET	FF	1	R14C39[2][B]	u_rd/n608_s3/I3
9.491	0.555	tINS	FF	10	R14C39[2][B]	u_rd/n608_s3/F
9.950	0.459	tNET	FF	1	R14C32[3][A]	u_rd/n676_s1/I1
10.505	0.555	tINS	FF	39	R14C32[3][A]	u_rd/n676_s1/F
10.972	0.466	tNET	FF	1	R16C31[2][A]	u_rd/n713_s0/I1
11.521	0.549	tINS	FR	1	R16C31[2][A]	u_rd/n713_s0/F
11.521	0.000	tNET	RR	1	R16C31[2][A]	u_rd/app_wdf_data_26_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R16C31[2][A]	u_rd/app_wdf_data_26_s1/CLK
12.236	-0.035	tSu		1	R16C31[2][A]	u_rd/app_wdf_data_26_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.818, 41.278%; route: 5.200, 56.214%; tC2Q: 0.232, 2.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.074
Data Arrival Time	0.323
Data Required Time	0.249
From	u_la0_top/u_ao_mem_ctrl/data_reg_33_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/CLK
0.201	0.201	tC2Q	RF	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q
0.323	0.122	tNET	FF	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.249	0.249	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	0.074
Data Arrival Time	0.323
Data Required Time	0.249
From	u_la0_top/u_ao_mem_ctrl/data_reg_32_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK
0.201	0.201	tC2Q	RF	1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q
0.323	0.122	tNET	FF	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.249	0.249	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	0.213
Data Arrival Time	0.331
Data Required Time	0.118
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.202	0.202	tC2Q	RR	8	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q
0.331	0.129	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.118	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.129, 39.034%; tC2Q: 0.202, 60.966%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	0.213
Data Arrival Time	0.462
Data Required Time	0.249
From	u_la0_top/u_ao_mem_ctrl/data_reg_18_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R11C6[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK
0.202	0.202	tC2Q	RR	1	R11C6[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q
0.462	0.260	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.249	0.249	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	0.225
Data Arrival Time	0.474
Data Required Time	0.249
From	u_la0_top/u_ao_mem_ctrl/data_reg_28_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK
0.202	0.202	tC2Q	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q
0.474	0.272	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.249	0.249	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	0.307
Data Arrival Time	1.829
Data Required Time	1.522
From	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_29_s0
To	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_1_29_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C21[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_29_s0/CLK
1.712	0.201	tC2Q	RF	1	R24C21[0][A]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_29_s0/Q
1.829	0.117	tNET	FF	1	R24C21[1][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_1_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R24C21[1][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_1_29_s0/CLK
1.522	0.011	tHld		1	R24C21[1][B]	u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_wrdata_dly_1_29_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path7

Path Summary:

Slack	0.307
Data Arrival Time	0.318
Data Required Time	0.011
From	u_la0_top/rst_ao_syn_s0
To	u_la0_top/rst_ao_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][A]	u_la0_top/rst_ao_syn_s0/CLK
0.201	0.201	tC2Q	RF	1	R12C6[0][A]	u_la0_top/rst_ao_syn_s0/Q
0.318	0.117	tNET	FF	1	R12C6[0][B]	u_la0_top/rst_ao_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.011	0.011	tHld		1	R12C6[0][B]	u_la0_top/rst_ao_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_27_s0
To	u_la0_top/data_register_26_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_27_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_27_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_26_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_26_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path9

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_28_s0
To	u_la0_top/data_register_27_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_28_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_28_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_27_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_27_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path10

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_30_s0
To	u_la0_top/data_register_29_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_30_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_30_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_29_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_29_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path11

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_32_s0
To	u_la0_top/data_register_31_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_32_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_32_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_31_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_31_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_31_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path12

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_34_s0
To	u_la0_top/data_register_33_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_34_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_34_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_33_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_33_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path13

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_35_s0
To	u_la0_top/data_register_34_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_35_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_35_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_34_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_34_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path14

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_40_s0
To	u_la0_top/data_register_39_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_40_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_40_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_39_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_39_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_39_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path15

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_42_s0
To	u_la0_top/data_register_41_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_42_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_42_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_41_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_41_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_41_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path16

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_46_s0
To	u_la0_top/data_register_45_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_46_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_46_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_45_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_45_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_45_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path17

Path Summary:

Slack	0.307
Data Arrival Time	6.012
Data Required Time	5.705
From	u_la0_top/data_register_48_s0
To	u_la0_top/data_register_47_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_48_s0/CLK
5.895	0.201	tC2Q	RF	1		u_la0_top/data_register_48_s0/Q
6.012	0.117	tNET	FF	1		u_la0_top/data_register_47_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_47_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_47_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path18

Path Summary:

Slack	0.310
Data Arrival Time	6.016
Data Required Time	5.705
From	u_la0_top/data_register_7_s0
To	u_la0_top/data_register_6_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_7_s0/CLK
5.895	0.201	tC2Q	RF	4		u_la0_top/data_register_7_s0/Q
6.016	0.120	tNET	FF	1		u_la0_top/data_register_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_6_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path19

Path Summary:

Slack	0.310
Data Arrival Time	6.016
Data Required Time	5.705
From	u_la0_top/data_register_53_s0
To	u_la0_top/data_register_52_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_53_s0/CLK
5.895	0.201	tC2Q	RF	2		u_la0_top/data_register_53_s0/Q
6.016	0.120	tNET	FF	1		u_la0_top/data_register_52_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_52_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_52_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path20

Path Summary:

Slack	0.310
Data Arrival Time	6.016
Data Required Time	5.705
From	u_la0_top/data_register_54_s0
To	u_la0_top/data_register_53_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_54_s0/CLK
5.895	0.201	tC2Q	RF	2		u_la0_top/data_register_54_s0/Q
6.016	0.120	tNET	FF	1		u_la0_top/data_register_53_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_53_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_53_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path21

Path Summary:

Slack	0.310
Data Arrival Time	6.016
Data Required Time	5.705
From	u_la0_top/data_register_56_s0
To	u_la0_top/data_register_55_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_56_s0/CLK
5.895	0.201	tC2Q	RF	2		u_la0_top/data_register_56_s0/Q
6.016	0.120	tNET	FF	1		u_la0_top/data_register_55_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_55_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_55_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path22

Path Summary:

Slack	0.310
Data Arrival Time	6.016
Data Required Time	5.705
From	u_la0_top/data_register_59_s0
To	u_la0_top/data_register_58_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_59_s0/CLK
5.895	0.201	tC2Q	RF	2		u_la0_top/data_register_59_s0/Q
6.016	0.120	tNET	FF	1		u_la0_top/data_register_58_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_58_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_58_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path23

Path Summary:

Slack	0.310
Data Arrival Time	6.016
Data Required Time	5.705
From	u_la0_top/data_register_62_s0
To	u_la0_top/data_register_61_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_62_s0/CLK
5.895	0.201	tC2Q	RF	2		u_la0_top/data_register_62_s0/Q
6.016	0.120	tNET	FF	1		u_la0_top/data_register_61_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.802	0.675	tINS	RR	321		u_gw_jtag/tck_o
5.694	1.892	tNET	RR	1		u_la0_top/data_register_61_s0/CLK
5.705	0.011	tHld		1		u_la0_top/data_register_61_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 3.802, 66.767%; route: 1.892, 33.233%

Path24

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/mux_addr_8_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[16].mem0_cmd_fifo_gen[16].mem0_0_11_s
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R34C33[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/mux_addr_8_s0/CLK
1.712	0.201	tC2Q	RF	1	R34C33[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/mux_addr_8_s0/Q
1.834	0.122	tNET	FF	1	R33C33	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[16].mem0_cmd_fifo_gen[16].mem0_0_11_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R33C33	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[16].mem0_cmd_fifo_gen[16].mem0_0_11_s/CLK
1.521	0.010	tHld		1	R33C33	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[16].mem0_cmd_fifo_gen[16].mem0_0_11_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path25

Path Summary:

Slack	0.313
Data Arrival Time	1.834
Data Required Time	1.521
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[3].Q_data0_1_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_0_s23
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R32C29[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[3].Q_data0_1_s0/CLK
1.712	0.201	tC2Q	RF	1	R32C29[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/cmd_fifo_gen[3].Q_data0_1_s0/Q
1.834	0.122	tNET	FF	1	R33C29	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_0_s23/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
1.511	1.511	tNET	RR	1	R33C29	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_0_s23/CLK
1.521	0.010	tHld		1	R33C29	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_0_s23

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R38C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R38C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0/CLK
12.236	-0.035	tSu		1	R38C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path2

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R38C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R38C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0/CLK
12.236	-0.035	tSu		1	R38C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path3

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R38C26[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R38C26[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLK
12.236	-0.035	tSu		1	R38C26[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path4

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_4_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C27[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C27[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_4_s0/CLK
12.236	-0.035	tSu		1	R39C27[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path5

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C27[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C27[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLK
12.236	-0.035	tSu		1	R39C27[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path6

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK
12.236	-0.035	tSu		1	R39C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path7

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C26[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C26[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK
12.236	-0.035	tSu		1	R39C26[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path8

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_5_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_5_s0/CLK
12.236	-0.035	tSu		1	R39C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path9

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_4_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C27[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C27[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_4_s0/CLK
12.236	-0.035	tSu		1	R39C27[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path10

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C27[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C27[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLK
12.236	-0.035	tSu		1	R39C27[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path11

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C26[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C26[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK
12.236	-0.035	tSu		1	R39C26[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path12

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C26[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C26[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK
12.236	-0.035	tSu		1	R39C26[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path13

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_5_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C27[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C27[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_5_s0/CLK
12.236	-0.035	tSu		1	R39C27[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path14

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R38C26[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R38C26[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK
12.236	-0.035	tSu		1	R38C26[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path15

Path Summary:

Slack	7.817
Data Arrival Time	4.420
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.420	1.246	tNET	FF	1	R39C26[2][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R39C26[2][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/CLK
12.236	-0.035	tSu		1	R39C26[2][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.067%; route: 1.399, 65.133%; tC2Q: 0.232, 10.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path16

Path Summary:

Slack	7.825
Data Arrival Time	4.412
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_5_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.412	1.238	tNET	FF	1	R40C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R40C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_5_s0/CLK
12.236	-0.035	tSu		1	R40C26[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.155%; route: 1.391, 65.005%; tC2Q: 0.232, 10.839%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path17

Path Summary:

Slack	7.825
Data Arrival Time	4.412
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.412	1.238	tNET	FF	1	R40C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R40C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLK
12.236	-0.035	tSu		1	R40C26[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 24.155%; route: 1.391, 65.005%; tC2Q: 0.232, 10.839%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path18

Path Summary:

Slack	7.956
Data Arrival Time	4.280
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.280	1.107	tNET	FF	1	R36C21[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C21[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLK
12.236	-0.035	tSu		1	R36C21[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 25.738%; route: 1.260, 62.712%; tC2Q: 0.232, 11.550%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path19

Path Summary:

Slack	7.956
Data Arrival Time	4.280
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.280	1.107	tNET	FF	1	R36C21[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C21[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0/CLK
12.236	-0.035	tSu		1	R36C21[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 25.738%; route: 1.260, 62.712%; tC2Q: 0.232, 11.550%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path20

Path Summary:

Slack	7.956
Data Arrival Time	4.280
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.280	1.107	tNET	FF	1	R36C21[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C21[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0/CLK
12.236	-0.035	tSu		1	R36C21[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 25.738%; route: 1.260, 62.712%; tC2Q: 0.232, 11.550%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path21

Path Summary:

Slack	8.082
Data Arrival Time	4.154
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_4_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.154	0.981	tNET	FF	1	R36C24[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C24[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_4_s0/CLK
12.236	-0.035	tSu		1	R36C24[0][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 27.456%; route: 1.134, 60.223%; tC2Q: 0.232, 12.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path22

Path Summary:

Slack	8.082
Data Arrival Time	4.154
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.154	0.981	tNET	FF	1	R36C24[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C24[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK
12.236	-0.035	tSu		1	R36C24[2][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 27.456%; route: 1.134, 60.223%; tC2Q: 0.232, 12.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path23

Path Summary:

Slack	8.082
Data Arrival Time	4.154
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.154	0.981	tNET	FF	1	R36C24[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C24[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLK
12.236	-0.035	tSu		1	R36C24[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 27.456%; route: 1.134, 60.223%; tC2Q: 0.232, 12.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path24

Path Summary:

Slack	8.082
Data Arrival Time	4.154
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.154	0.981	tNET	FF	1	R36C24[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C24[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLK
12.236	-0.035	tSu		1	R36C24[1][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 27.456%; route: 1.134, 60.223%; tC2Q: 0.232, 12.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path25

Path Summary:

Slack	8.082
Data Arrival Time	4.154
Data Required Time	12.236
From	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
2.271	2.271	tNET	RR	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R34C15[1][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.656	0.153	tNET	FF	1	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
3.173	0.517	tINS	FF	60	R34C15[3][A]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
4.154	0.981	tNET	FF	1	R36C24[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_user
10.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
12.271	2.271	tNET	RR	1	R36C24[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLK
12.236	-0.035	tSu		1	R36C24[0][B]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.517, 27.456%; route: 1.134, 60.223%; tC2Q: 0.232, 12.321%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.487
Data Arrival Time	0.498
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.498	0.296	tNET	RR	1	R4C4[2][A]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C4[2][A]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.011	0.011	tHld		1	R4C4[2][A]	u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.296, 59.464%; tC2Q: 0.202, 40.536%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	0.487
Data Arrival Time	0.498
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.498	0.296	tNET	RR	1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.011	0.011	tHld		1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.296, 59.464%; tC2Q: 0.202, 40.536%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	0.487
Data Arrival Time	0.498
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.498	0.296	tNET	RR	1	R4C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.011	0.011	tHld		1	R4C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.296, 59.464%; tC2Q: 0.202, 40.536%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	0.593
Data Arrival Time	0.604
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.604	0.402	tNET	RR	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.011	0.011	tHld		1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.402, 66.546%; tC2Q: 0.202, 33.454%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	0.593
Data Arrival Time	0.604
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.604	0.402	tNET	RR	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.011	0.011	tHld		1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.402, 66.546%; tC2Q: 0.202, 33.454%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	0.599
Data Arrival Time	0.610
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_4_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.610	0.408	tNET	RR	1	R2C4[0][B]	u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R2C4[0][B]	u_la0_top/capture_window_sel_4_s1/CLK
0.011	0.011	tHld		1	R2C4[0][B]	u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.408, 66.875%; tC2Q: 0.202, 33.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	0.599
Data Arrival Time	0.610
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_5_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.610	0.408	tNET	RR	1	R2C4[0][A]	u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R2C4[0][A]	u_la0_top/capture_window_sel_5_s1/CLK
0.011	0.011	tHld		1	R2C4[0][A]	u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.408, 66.875%; tC2Q: 0.202, 33.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	0.599
Data Arrival Time	0.610
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_9_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.610	0.408	tNET	RR	1	R2C4[2][A]	u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R2C4[2][A]	u_la0_top/capture_window_sel_9_s1/CLK
0.011	0.011	tHld		1	R2C4[2][A]	u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.408, 66.875%; tC2Q: 0.202, 33.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	0.599
Data Arrival Time	0.610
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/start_reg_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.610	0.408	tNET	RR	1	R2C4[1][B]	u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R2C4[1][B]	u_la0_top/start_reg_s0/CLK
0.011	0.011	tHld		1	R2C4[1][B]	u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.408, 66.875%; tC2Q: 0.202, 33.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	0.599
Data Arrival Time	0.610
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.610	0.408	tNET	RR	1	R2C4[1][A]	u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R2C4[1][A]	u_la0_top/internal_reg_start_dly_0_s0/CLK
0.011	0.011	tHld		1	R2C4[1][A]	u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.408, 66.875%; tC2Q: 0.202, 33.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	0.608
Data Arrival Time	0.619
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.619	0.417	tNET	RR	1	R12C4[1][A]	u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C4[1][A]	u_la0_top/internal_reg_start_syn_0_s0/CLK
0.011	0.011	tHld		1	R12C4[1][A]	u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.417, 67.365%; tC2Q: 0.202, 32.635%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	0.611
Data Arrival Time	0.622
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.622	0.420	tNET	RR	1	R12C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.011	0.011	tHld		1	R12C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.523%; tC2Q: 0.202, 32.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	0.611
Data Arrival Time	0.622
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.622	0.420	tNET	RR	1	R12C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.011	0.011	tHld		1	R12C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.523%; tC2Q: 0.202, 32.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	0.611
Data Arrival Time	0.622
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.622	0.420	tNET	RR	1	R12C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.011	0.011	tHld		1	R12C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.523%; tC2Q: 0.202, 32.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	0.611
Data Arrival Time	0.622
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.622	0.420	tNET	RR	1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.011	0.011	tHld		1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.523%; tC2Q: 0.202, 32.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	0.611
Data Arrival Time	0.622
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_6_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.622	0.420	tNET	RR	1	R4C3[0][A]	u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C3[0][A]	u_la0_top/capture_window_sel_6_s1/CLK
0.011	0.011	tHld		1	R4C3[0][A]	u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.523%; tC2Q: 0.202, 32.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	0.611
Data Arrival Time	0.622
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.622	0.420	tNET	RR	1	R4C3[1][B]	u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C3[1][B]	u_la0_top/triger_level_cnt_2_s1/CLK
0.011	0.011	tHld		1	R4C3[1][B]	u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.523%; tC2Q: 0.202, 32.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	0.611
Data Arrival Time	0.622
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.622	0.420	tNET	RR	1	R4C3[1][A]	u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C3[1][A]	u_la0_top/triger_level_cnt_3_s1/CLK
0.011	0.011	tHld		1	R4C3[1][A]	u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.523%; tC2Q: 0.202, 32.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack	0.612
Data Arrival Time	0.623
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.623	0.421	tNET	RR	1	R5C4[2][A]	u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R5C4[2][A]	u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.011	0.011	tHld		1	R5C4[2][A]	u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 67.584%; tC2Q: 0.202, 32.416%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack	0.612
Data Arrival Time	0.623
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/trigger_seq_start_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.623	0.421	tNET	RR	1	R5C4[0][A]	u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R5C4[0][A]	u_la0_top/trigger_seq_start_s1/CLK
0.011	0.011	tHld		1	R5C4[0][A]	u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 67.584%; tC2Q: 0.202, 32.416%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack	0.612
Data Arrival Time	0.623
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.623	0.421	tNET	RR	1	R4C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
0.011	0.011	tHld		1	R4C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 67.593%; tC2Q: 0.202, 32.407%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack	0.612
Data Arrival Time	0.623
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_1_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.623	0.421	tNET	RR	1	R4C2[2][A]	u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C2[2][A]	u_la0_top/capture_window_sel_1_s1/CLK
0.011	0.011	tHld		1	R4C2[2][A]	u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 67.593%; tC2Q: 0.202, 32.407%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack	0.612
Data Arrival Time	0.623
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_3_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.623	0.421	tNET	RR	1	R4C2[2][B]	u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R4C2[2][B]	u_la0_top/capture_window_sel_3_s1/CLK
0.011	0.011	tHld		1	R4C2[2][B]	u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 67.593%; tC2Q: 0.202, 32.407%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack	0.614
Data Arrival Time	0.625
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.625	0.423	tNET	RR	1	R13C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R13C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.011	0.011	tHld		1	R13C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.423, 67.701%; tC2Q: 0.202, 32.299%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack	0.614
Data Arrival Time	0.625
Data Required Time	0.011
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk_user:[R]
Latch Clk	clk_user:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R12C6[0][B]	u_la0_top/rst_ao_s0/CLK
0.202	0.202	tC2Q	RR	57	R12C6[0][B]	u_la0_top/rst_ao_s0/Q
0.625	0.423	tNET	RR	1	R13C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_user
0.000	0.000	tCL	RR	2467	BOTTOMSIDE[0]	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT
0.000	0.000	tNET	RR	1	R13C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.011	0.011	tHld		1	R13C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.423, 67.701%; tC2Q: 0.202, 32.299%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/wloadn_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/wloadn_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/wloadn_1_s0/CLK

MPW2

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/CLK

MPW3

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0/CLK

MPW4

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/recalib_s_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/recalib_s_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/recalib_s_1_s0/CLK

MPW5

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_2_s0/CLK

MPW6

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_6_s1/CLK

MPW7

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLK

MPW8

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0/CLK

MPW9

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLK

MPW10

MPW Summary:

Slack:	0.837
Actual Width:	1.837
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_in_osc_50
Objects:	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_in_osc_50
0.000	0.000	tCL	RR	clk_ibuf/I
9.781	9.781	tINS	RR	clk_ibuf/O
12.052	2.271	tNET	RR	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_in_osc_50
10.000	0.000	tCL	FF	clk_ibuf/I
12.376	2.376	tINS	FF	clk_ibuf/O
13.889	1.514	tNET	FF	u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2467	clk_x1	0.363	2.274
128	eye_calib_start_rr[0]	3.671	1.848
96	eye_calib_start_rr	6.480	1.779
92	ddr_init_internal_rr	6.415	1.761
85	init_calib_complete	4.980	2.528
84	mem4_15	7.803	0.984
75	n28_3	0.995	1.473
73	send_wr_d2	7.310	1.325
66	phy_rddata_valid_d1	7.644	1.540
64	clk_x2i	4.504	0.386

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R28C23	75.00%
R28C24	69.44%
R46C26	66.67%
R29C21	62.50%
R46C27	62.50%
R21C22	59.72%
R30C34	58.33%
R21C39	58.33%
R29C24	56.94%
R28C25	55.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_in_osc_50 -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name memory_clk -period 5 -waveform {0 2.5} [get_pins {pll/rpll_inst/CLKOUT}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name clk_user -source [get_pins {pll/rpll_inst/CLKOUT}] -master_clock memory_clk -divide_by 2 [get_pins {u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk_in_osc_50}] -group [get_clocks {memory_clk clk_user}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {memory_clk}] -group [get_clocks {clk_user}]