PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gwsynthesis\ddr3_ref_design.vg
Gao Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gao\gao.v
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.cst
Timing Constraints File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.sdc
Tool Version V1.9.11.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Fri Feb 28 17:19:00 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.809s, Elapsed time = 0h 0m 0.809s Placement Phase 1: CPU time = 0h 0m 0.297s, Elapsed time = 0h 0m 0.297s Placement Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Placement Phase GAO : CPU time = 0h 0m 0.088s, Elapsed time = 0h 0m 0.088s Total Placement: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Running routing: Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s Routing Phase 1: CPU time = 0h 0m 0.396s, Elapsed time = 0h 0m 0.396s Routing Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Routing Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Routing: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s Generate output files: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Total Time and Memory Usage CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 549MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 2981/20736 15%
    --LUT,ALU,ROM16 2609(2382 LUT, 227 ALU, 0 ROM16) -
    --SSRAM(RAM16) 62 -
Register 2171/16173 14%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 2170/15552 14%
    --I/O Register as Latch 0/621 0%
    --I/O Register as FF 1/621 <1%
CLS 2093/10368 21%
I/O Port 54/207 27%
I/O Buf 51 -
    --Input Buf 2 -
    --Output Buf 31 -
    --Inout Buf 18 -
IOLOGIC 16 IDES4_MEM
24 OSER4
20 OSER4_MEM
16 IODELAY
 29%
BSRAM 2 SDPB
2 SDPX9B
 9%

GAO Resource Usage Summary:

Resource Usage
Logic 496
    --LUT,ALU,ROM16 496(483 LUT, 13 ALU, 0 ROM16)
    --SSRAM(RAM16) 0
Register 517
I/O Port 73
I/O Buf 4
    --Input Buf 3
    --Output Buf 1
    --Inout Buf 0
BSRAM 4

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 5/2918%
bank 1 0/200%
bank 2 0/200%
bank 3 0/320%
bank 4 20/3656%
bank 5 20/3656%
bank 6 9/1850%
bank 7 0/160%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 2/8 25%
LW 3/8 38%
GCLK_PIN 4/8 50%
CLKDIV 1/8 13%
DHCEN 1/16 7%
DLL 1/4 25%
DQS 2/9 23%
rPLL 1/4 25%

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY TR TL BL
clk_x1 PRIMARY TR TL BR BL
n7_6 LW -
init_calib_complete LW -
u_ddr3/u_gw3_phy_mc/ddr_rst LW -
memory_clk HCLK BOTTOM[0] LEFT[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - H11/0 Y in IOT27[A] GCLKT_0 LVCMOS15 NA UP ON NONE NA NA NA NA 1.5
rst_nn - T2/4 Y in IOB48[B] - LVCMOS15 NA UP ON NONE NA NA NA NA 1.5
ddr_addr[0] - F7/6 Y out IOL45[A] LPLL2_T_in SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_addr[1] - A4/5 Y out IOB2[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_addr[2] - D6/5 Y out IOB3[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_addr[3] - F8/6 Y out IOL35[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_addr[4] - C4/6 Y out IOL47[A] LPLL2_T_fb SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_addr[5] - E6/6 Y out IOL53[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_addr[6] - B1/5 Y out IOB8[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_addr[7] - D8/6 Y out IOL38[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_addr[8] - A5/5 Y out IOB7[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_addr[9] - F9/6 Y out IOL31[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_addr[10] - K3/4 Y out IOB36[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_addr[11] - B7/6 Y out IOL40[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_addr[12] - A3/5 Y out IOB4[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_addr[13] - C8/6 Y out IOL29[A] GCLKT_6 SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_bank[0] - H4/5 Y out IOB26[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_bank[1] - D3/5 Y out IOB9[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_bank[2] - H5/4 Y out IOB35[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_cs - P5/4 Y out IOB50[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_ras - R4/4 Y out IOB52[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_cas - R6/4 Y out IOB54[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_we - L2/4 Y out IOB30[A] GCLKT_4 SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_ck ddr_ck_n J1,J3/5 Y out IOB27 GCLKT_5 SSTL15D 8 NA NA NA NA NA NA NA 1.5
ddr_cke - J2/4 Y out IOB34[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_odt - R3/4 Y out IOB48[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_reset_n - B9/6 Y out IOL33[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
ddr_dm[0] - G1/5 Y out IOB24[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
ddr_dm[1] - K5/4 Y out IOB40[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
led[0] - F16/0 Y out IOT9[B] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
led[1] - G12/0 Y out IOT8[B] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
led[2] - F13/0 Y out IOT8[A] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
led[3] - F14/0 Y out IOT9[A] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
ddr_dq[0] - G5/5 Y io IOB20[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[1] - F5/5 Y io IOB22[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[2] - F4/5 Y io IOB18[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[3] - F3/5 Y io IOB19[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[4] - E2/5 Y io IOB12[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[5] - C1/5 Y io IOB14[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[6] - E1/5 Y io IOB16[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[7] - B3/5 Y io IOB13[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[8] - M3/4 Y io IOB42[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[9] - K4/4 Y io IOB39[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[10] - N2/4 Y io IOB41[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[11] - L1/4 Y io IOB38[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[12] - P4/4 Y io IOB45[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[13] - H3/4 Y io IOB32[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[14] - R1/4 Y io IOB44[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[15] - M2/4 Y io IOB43[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dqs[0] ddr_dqs_n[0] G2,G3/5 Y io IOB21 - SSTL15D 8 NONE NA NA NA NA NA NA 1.5
ddr_dqs[1] ddr_dqs_n[1] J5,K6/4 Y io IOB37 - SSTL15D 8 NONE NA NA NA NA NA NA 1.5

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
L15/0 - in IOT2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D16/0 - in IOT4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E14/0 - in IOT4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C16/0 - in IOT5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D15/0 - in IOT5[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E16/0 - in IOT6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F15/0 - in IOT6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F13/0 led[2] out IOT8[A] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
G12/0 led[1] out IOT8[B] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
F14/0 led[3] out IOT9[A] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
F16/0 led[0] out IOT9[B] - LVCMOS15 8 UP NA NA OFF NA NA NA 1.5
F12/0 - in IOT12[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G13/0 - in IOT12[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G15/0 - in IOT13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G14/0 - in IOT13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G11/0 - in IOT14[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H12/0 - in IOT14[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G16/0 - in IOT16[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H15/0 - in IOT16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H13/0 - in IOT18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J12/0 - in IOT18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H14/0 - in IOT20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H16/0 - in IOT20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J16/0 - in IOT22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J14/0 - in IOT22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J15/0 - in IOT24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K16/0 - in IOT24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H11/0 clk in IOT27[A] GCLKT_0 LVCMOS15 NA UP ON NONE NA NA NA NA 1.5
J13/0 - in IOT27[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K14/1 - in IOT30[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K15/1 - in IOT30[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J11/1 - in IOT32[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L12/1 - in IOT32[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L16/1 - in IOT34[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L14/1 - in IOT34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K13/1 - in IOT36[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K12/1 - in IOT36[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K11/1 - in IOT38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L13/1 - in IOT38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M14/1 - in IOT40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M15/1 - in IOT40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D14/1 - in IOT44[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E15/1 - in IOT44[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N15/1 - in IOT48[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P16/1 - in IOT48[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N16/1 - in IOT52[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N14/1 - in IOT52[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P15/1 - in IOT54[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R16/1 - in IOT54[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A4/5 ddr_addr[1] out IOB2[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
C5/5 - in IOB2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D6/5 ddr_addr[2] out IOB3[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
E7/5 - in IOB3[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
A3/5 ddr_addr[12] out IOB4[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
B4/5 - in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
A5/5 ddr_addr[8] out IOB7[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
B6/5 - in IOB7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B1/5 ddr_addr[6] out IOB8[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
C2/5 - in IOB8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D3/5 ddr_bank[1] out IOB9[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
D1/5 - in IOB9[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E2/5 ddr_dq[4] io IOB12[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
E3/5 - in IOB12[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B3/5 ddr_dq[7] io IOB13[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
A2/5 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C1/5 ddr_dq[5] io IOB14[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
D2/5 - in IOB14[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E1/5 ddr_dq[6] io IOB16[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
F2/5 - in IOB16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F4/5 ddr_dq[2] io IOB18[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
G6/5 - in IOB18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F3/5 ddr_dq[3] io IOB19[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
F1/5 - in IOB19[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G5/5 ddr_dq[0] io IOB20[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
G4/5 - in IOB20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G2/5 ddr_dqs[0] io IOB21[A] - SSTL15D 8 NONE NA NA NA NA NA NA 1.5
G3/5 ddr_dqs_n[0] io IOB21[B] - SSTL15D 8 NONE NA NA NA NA NA NA 1.5
F5/5 ddr_dq[1] io IOB22[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
H6/5 - in IOB22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G1/5 ddr_dm[0] out IOB24[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
H2/5 - in IOB24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H4/5 ddr_bank[0] out IOB26[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
J6/5 - in IOB26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J1/5 ddr_ck out IOB27[A] GCLKT_5 SSTL15D 8 NA NA NA NA NA NA NA 1.5
J3/5 ddr_ck_n out IOB27[B] GCLKC_5 SSTL15D 8 NA NA NA NA NA NA NA 1.5
L2/4 ddr_we out IOB30[A] GCLKT_4 SSTL15 8 NA NA NA NA NA NA NA 1.5
M1/4 - in IOB30[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H3/4 ddr_dq[13] io IOB32[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
H1/4 - in IOB32[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J2/4 ddr_cke out IOB34[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
K1/4 - in IOB34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H5/4 ddr_bank[2] out IOB35[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
J4/4 - in IOB35[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K3/4 ddr_addr[10] out IOB36[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
K2/4 - in IOB36[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J5/4 ddr_dqs[1] io IOB37[A] - SSTL15D 8 NONE NA NA NA NA NA NA 1.5
K6/4 ddr_dqs_n[1] io IOB37[B] - SSTL15D 8 NONE NA NA NA NA NA NA 1.5
L1/4 ddr_dq[11] io IOB38[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
L3/4 - in IOB38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K4/4 ddr_dq[9] io IOB39[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
L5/4 - in IOB39[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K5/4 ddr_dm[1] out IOB40[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
L4/4 - in IOB40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
N2/4 ddr_dq[10] io IOB41[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
P1/4 - in IOB41[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M3/4 ddr_dq[8] io IOB42[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
N1/4 - in IOB42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M2/4 ddr_dq[15] io IOB43[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
N3/4 - in IOB43[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R1/4 ddr_dq[14] io IOB44[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
P2/4 - in IOB44[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P4/4 ddr_dq[12] io IOB45[A] - SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
T4/4 - in IOB45[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R3/4 ddr_odt out IOB48[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
T2/4 rst_nn in IOB48[B] - LVCMOS15 NA UP ON NONE NA NA NA NA 1.5
P5/4 ddr_cs out IOB50[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
R5/4 - in IOB50[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R4/4 ddr_ras out IOB52[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
T3/4 - in IOB52[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R6/4 ddr_cas out IOB54[A] - SSTL15 8 NA NA NA NA NA NA NA 1.5
T5/4 - in IOB54[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B14/7 - in IOL2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A15/7 - in IOL2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C12/7 - in IOL7[A] LPLL1_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B12/7 - in IOL7[B] LPLL1_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B13/7 - in IOL8[A] LPLL1_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A14/7 - in IOL8[B] LPLL1_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F10/7 - in IOL11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B11/7 - in IOL13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A12/7 - in IOL13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A11/7 - in IOL15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C11/7 - in IOL15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D10/7 - in IOL17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E10/7 - in IOL17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D11/7 - in IOL22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A9/7 - in IOL27[A] GCLKT_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C9/7 - in IOL27[B] GCLKC_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C8/6 ddr_addr[13] out IOL29[A] GCLKT_6 SSTL15 8 NA NA NA NA NA OFF NA 1.5
A8/6 - in IOL29[B] GCLKC_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F9/6 ddr_addr[9] out IOL31[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
E11/6 - in IOL31[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B9/6 ddr_reset_n out IOL33[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
A10/6 - in IOL33[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F8/6 ddr_addr[3] out IOL35[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
D9/6 - in IOL35[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D8/6 ddr_addr[7] out IOL38[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
E9/6 - in IOL38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B7/6 ddr_addr[11] out IOL40[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
C7/6 - in IOL40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F7/6 ddr_addr[0] out IOL45[A] LPLL2_T_in SSTL15 8 NA NA NA NA NA OFF NA 1.5
E8/6 - in IOL45[B] LPLL2_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C4/6 ddr_addr[4] out IOL47[A] LPLL2_T_fb SSTL15 8 NA NA NA NA NA OFF NA 1.5
B5/6 - in IOL47[B] LPLL2_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E6/6 ddr_addr[5] out IOL53[A] - SSTL15 8 NA NA NA NA NA OFF NA 1.5
D7/6 - in IOL53[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
T15/2 - in IOR7[A] RPLL1_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R14/2 - in IOR7[B] RPLL1_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P12/2 - in IOR8[A] RPLL1_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T13/2 - in IOR8[B] RPLL1_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R12/2 - in IOR11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P13/2 - in IOR11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R11/2 - in IOR17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T12/2 - in IOR17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R13/2 - in IOR20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T14/2 - in IOR20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M10/2 - in IOR22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N11/2 - in IOR22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T11/2 - in IOR24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P11/2 - in IOR24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C6/2 tdo_pad_o out IOR25[A] TDO LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
B8/2 tms_pad_i in IOR25[B] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A7/2 tck_pad_i in IOR26[A] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A6/2 tdi_pad_i in IOR26[B] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N10/2 - in IOR27[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M11/2 - in IOR27[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T7/3 - in IOR29[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R8/3 - in IOR29[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M16/3 - in IOR30[A] MODE0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B16/3 - in IOR30[B] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C15/3 - in IOR31[A] MODE2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B10/3 - in IOR31[B] RECONFIG_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A13/3 - in IOR32[A] READY LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C13/3 - in IOR32[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P10/3 - in IOR33[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R10/3 - in IOR33[B] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M9/3 - in IOR34[A] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L10/3 - in IOR34[B] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R9/3 - in IOR35[A] FASTRD_N/D3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T10/3 - in IOR35[B] SI/D2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M8/3 - in IOR36[A] SO/D1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N9/3 - in IOR36[B] SSPI_CS_N/D0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T9/3 - in IOR38[A] DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P9/3 - in IOR38[B] DOUT/WE_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C10/3 - in IOR39[A] SCLK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N8/3 - in IOR40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L9/3 - in IOR40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P8/3 - in IOR42[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T8/3 - in IOR42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M6/3 - in IOR44[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L8/3 - in IOR44[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M7/3 - in IOR47[A] RPLL2_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N7/3 - in IOR47[B] RPLL2_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R7/3 - in IOR49[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P7/3 - in IOR49[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N6/3 - in IOR51[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P6/3 - in IOR53[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T6/3 - in IOR53[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8