Power Messages

Report Title	Power Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gwsynthesis\ddr3_ref_design.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.cst
Timing Constraints File	E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.sdc
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Feb 28 17:19:00 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	292.542
Quiescent Power (mW)	120.847
Dynamic Power (mW)	171.695

Thermal Information:

Junction Temperature	34.367
Theta JA	32.020
Max Allowed Ambient Temperature	75.633

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	1.000	143.114	69.929	213.044
VCCX	3.300	5.948	15.000	69.130
VCCIO15	1.500	5.967	0.945	10.368

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	4.584	NA	12.329
IO	45.682	10.256	29.348
BSRAM	64.620	NA	NA
PLL	20.920	NA	NA
DLL	46.080	NA	NA
DQS	135.900	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
ddr3_syn_top	272.105	272.105(272.028)
ddr3_syn_top/pll/	20.920	20.920(0.000)
ddr3_syn_top/u_ddr3/	250.223	250.223(250.223)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/	250.223	250.223(250.120)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/	248.991	248.991(202.712)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/	0.041	0.041(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/	0.825	0.825(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/	200.983	200.983(200.969)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/	116.685	116.685(116.666)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/	67.975	67.975(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/	15.930	15.930(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/	32.761	32.761(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/	83.919	83.919(83.900)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/	67.970	67.970(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/	15.930	15.930(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/	0.062	0.062(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[1].fifo_ctrl/	0.062	0.062(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/of_fifo_ctrl_inst/	0.040	0.040(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/	0.200	0.200(0.129)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/	0.083	0.083(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/	0.045	0.045(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/	0.000	0.000(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib/	0.219	0.219(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_eye_calib_rmove_mod/	0.128	0.128(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_init_rmove_mod/	0.515	0.515(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/	1.129	1.129(0.970)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/	0.261	0.261(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_rd_data0/	0.101	0.101(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/	0.262	0.262(0.188)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/	0.188	0.188(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/	0.230	0.230(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/	0.083	0.083(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_timing_ctrl0/	0.034	0.034(0.000)
ddr3_syn_top/u_rd/	0.884	0.884(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
clk_user	100.000	69.185
NO CLOCK DOMAIN	0.000	0.000
clk_in_osc_50	50.000	20.977
memory_clk	200.000	182.007