Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\DDR3_test.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3_memory_interface\ddr3_memory_interface.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3_syn_top.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\gowin_rpll\gowin_rpll.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Fri Feb 28 17:18:44 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | ddr3_syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.564s, Peak memory usage = 513.160MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 513.160MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 513.160MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 513.160MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 513.160MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 513.160MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 513.160MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 513.160MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 513.160MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 513.160MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 513.160MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 513.160MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.286s, Peak memory usage = 513.160MB Generate output files: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.251s, Peak memory usage = 513.160MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 513.160MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 54 |
| I/O Buf | 51 |
| IBUF | 2 |
| OBUF | 30 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 2005 |
| DFF | 55 |
| DFFE | 4 |
| DFFR | 1 |
| DFFP | 74 |
| DFFPE | 28 |
| DFFC | 1327 |
| DFFCE | 516 |
| LUT | 2192 |
| LUT2 | 462 |
| LUT3 | 614 |
| LUT4 | 1116 |
| ALU | 193 |
| ALU | 193 |
| SSRAM | 62 |
| RAM16S4 | 23 |
| RAM16SDP4 | 39 |
| INV | 26 |
| INV | 26 |
| IOLOGIC | 76 |
| IDES4_MEM | 16 |
| OSER4 | 24 |
| OSER4_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 4 |
| SDPB | 2 |
| SDPX9B | 2 |
| CLOCK | 5 |
| CLKDIV | 1 |
| DQS | 2 |
| DHCEN | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2783(2218 LUT, 193 ALU, 62 RAM16) / 20736 | 14% |
| Register | 2005 / 16173 | 13% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 2005 / 16173 | 13% |
| BSRAM | 4 / 46 | 9% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUT |
| 3 | pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTP |
| 4 | pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTD |
| 5 | pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 15.000 | 66.667 | 0.000 | 7.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTD3 |
| 6 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | pll/rpll_inst/CLKOUT | pll/rpll_inst/CLKOUT.default_gen_clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 184.638(MHz) | 6 | TOP |
| 2 | pll/rpll_inst/CLKOUT.default_gen_clk | 200.000(MHz) | 1030.927(MHz) | 1 | TOP |
| 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 115.457(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.176 |
| Data Arrival Time | 2.436 |
| Data Required Time | 3.612 |
| From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | pll/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 2097 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | pll/rpll_inst/CLKOUT.default_gen_clk | |||
| 3.000 | 0.500 | tCL | FF | 1 | pll/rpll_inst/CLKOUT |
| 3.474 | 0.474 | tNET | FF | 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 3.660 | 0.186 | tINS | FF | 64 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 4.134 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 4.099 | -0.035 | tUnc | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 3.612 | -0.487 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.933 |
| Setup Relationship: | 2.500 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 1.176 |
| Data Arrival Time | 2.436 |
| Data Required Time | 3.612 |
| From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | pll/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 2097 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | pll/rpll_inst/CLKOUT.default_gen_clk | |||
| 3.000 | 0.500 | tCL | FF | 1 | pll/rpll_inst/CLKOUT |
| 3.474 | 0.474 | tNET | FF | 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 3.660 | 0.186 | tINS | FF | 64 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 4.134 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 4.099 | -0.035 | tUnc | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 3.612 | -0.487 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.933 |
| Setup Relationship: | 2.500 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 1.339 |
| Data Arrival Time | 9.327 |
| Data Required Time | 10.666 |
| From | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_28_s9 |
| To | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 2097 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_28_s9/CLK |
| 0.933 | 0.232 | tC2Q | RF | 7 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_28_s9/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_31_s63/I1 |
| 1.962 | 0.555 | tINS | FF | 8 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_31_s63/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s0/I1 |
| 2.991 | 0.555 | tINS | FF | 4 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s0/F |
| 3.465 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_5_s65/I0 |
| 3.982 | 0.517 | tINS | FF | 28 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_5_s65/F |
| 4.456 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/I1 |
| 5.011 | 0.555 | tINS | FF | 75 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/F |
| 5.485 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_2_s5/I0 |
| 6.002 | 0.517 | tINS | FF | 3 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_2_s5/F |
| 6.476 | 0.474 | tNET | FF | 2 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_2_s/I1 |
| 7.046 | 0.570 | tINS | FR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_2_s/COUT |
| 7.046 | 0.000 | tNET | RR | 2 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/CIN |
| 7.081 | 0.035 | tINS | RF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/COUT |
| 7.555 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s18/I3 |
| 7.926 | 0.371 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s18/F |
| 8.400 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/I2 |
| 8.853 | 0.453 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/F |
| 9.327 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.341 | 0.341 | tCL | RR | 2097 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/CLK |
| 10.666 | -0.035 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 4.128, 47.857%; route: 4.266, 49.454%; tC2Q: 0.232, 2.689% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 2.141 |
| Data Arrival Time | 8.525 |
| Data Required Time | 10.666 |
| From | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_28_s9 |
| To | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0 |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 2097 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_28_s9/CLK |
| 0.933 | 0.232 | tC2Q | RF | 7 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_28_s9/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_31_s63/I1 |
| 1.962 | 0.555 | tINS | FF | 8 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_31_s63/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s0/I1 |
| 2.991 | 0.555 | tINS | FF | 4 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s0/F |
| 3.465 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_5_s65/I0 |
| 3.982 | 0.517 | tINS | FF | 28 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate_5_s65/F |
| 4.456 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/I1 |
| 5.011 | 0.555 | tINS | FF | 75 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/F |
| 5.485 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_2_s5/I0 |
| 6.002 | 0.517 | tINS | FF | 3 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_2_s5/F |
| 6.476 | 0.474 | tNET | FF | 2 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n654_s0/I0 |
| 7.025 | 0.549 | tINS | FR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n654_s0/COUT |
| 7.025 | 0.000 | tNET | RR | 2 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n655_s0/CIN |
| 7.060 | 0.035 | tINS | RF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n655_s0/COUT |
| 7.534 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rempty_val_s1/I0 |
| 8.051 | 0.517 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rempty_val_s1/F |
| 8.525 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.341 | 0.341 | tCL | RR | 2097 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0/CLK |
| 10.666 | -0.035 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.800, 48.570%; route: 3.792, 48.465%; tC2Q: 0.232, 2.965% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 2.187 |
| Data Arrival Time | 1.066 |
| Data Required Time | 3.253 |
| From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
| Launch Clk | clk[F] |
| Latch Clk | pll/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 41 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | pll/rpll_inst/CLKOUT.default_gen_clk | |||
| 3.000 | 0.500 | tCL | FF | 1 | pll/rpll_inst/CLKOUT |
| 3.474 | 0.474 | tNET | FF | 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 3.439 | -0.035 | tUnc | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen | ||
| 3.253 | -0.186 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
| Clock Skew: | 0.614 |
| Setup Relationship: | 2.500 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |