Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gao\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Fri Feb 28 17:18:47 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | gw_gao |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.289s, Peak memory usage = 102.082MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 102.082MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 102.082MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 102.082MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 102.082MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 102.082MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 102.082MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 102.082MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 102.082MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 102.082MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 102.082MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 102.082MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 131.824MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 131.824MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 131.824MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 131.824MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 73 |
| I/O Buf | 73 |
| IBUF | 72 |
| OBUF | 1 |
| Register | 517 |
| DFF | 143 |
| DFFR | 1 |
| DFFP | 3 |
| DFFPE | 33 |
| DFFC | 29 |
| DFFCE | 308 |
| LUT | 474 |
| LUT2 | 61 |
| LUT3 | 121 |
| LUT4 | 292 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 13 |
| ALU | 13 |
| INV | 4 |
| INV | 4 |
| BSRAM | 4 |
| SDPX9B | 4 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 499(486 LUT, 13 ALU) / 20736 | 3% |
| Register | 517 / 16173 | 4% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 517 / 16173 | 4% |
| BSRAM | 4 / 46 | 9% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_x1 | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_x1_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_x1 | 100.000(MHz) | 177.179(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.356 |
| Data Arrival Time | 5.969 |
| Data Required Time | 10.325 |
| From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Launch Clk | clk_x1[R] |
| Latch Clk | clk_x1[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_x1 | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 9 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n550_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 3 | u_la0_top/u_ao_mem_ctrl/n550_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n548_s2/I2 |
| 2.548 | 0.453 | tINS | FF | 3 | u_la0_top/u_ao_mem_ctrl/n548_s2/F |
| 3.022 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n546_s2/I2 |
| 3.475 | 0.453 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n546_s2/F |
| 3.949 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s3/I1 |
| 4.504 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s3/F |
| 4.978 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s2/I0 |
| 5.495 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s2/F |
| 5.969 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_x1 | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.533, 45.160%; route: 2.844, 50.704%; tC2Q: 0.232, 4.136% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 5.219 |
| Data Arrival Time | 5.106 |
| Data Required Time | 10.325 |
| From | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
| Launch Clk | clk_x1[R] |
| Latch Clk | clk_x1[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_x1 | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 3 | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n455_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 4 | u_la0_top/u_ao_mem_ctrl/n455_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n452_s3/I0 |
| 2.612 | 0.517 | tINS | FF | 3 | u_la0_top/u_ao_mem_ctrl/n452_s3/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n451_s1/I1 |
| 3.641 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n451_s1/F |
| 4.115 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n451_s2/I0 |
| 4.632 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n451_s2/F |
| 5.106 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_x1 | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.144, 45.175%; route: 2.370, 49.937%; tC2Q: 0.232, 4.888% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 5.257 |
| Data Arrival Time | 5.068 |
| Data Required Time | 10.325 |
| From | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
| Launch Clk | clk_x1[R] |
| Latch Clk | clk_x1[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_x1 | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 3 | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n455_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 4 | u_la0_top/u_ao_mem_ctrl/n455_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n452_s3/I0 |
| 2.612 | 0.517 | tINS | FF | 3 | u_la0_top/u_ao_mem_ctrl/n452_s3/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n450_s4/I0 |
| 3.603 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n450_s4/F |
| 4.077 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n450_s5/I0 |
| 4.594 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n450_s5/F |
| 5.068 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_x1 | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.106, 44.732%; route: 2.370, 50.340%; tC2Q: 0.232, 4.928% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 5.283 |
| Data Arrival Time | 5.042 |
| Data Required Time | 10.325 |
| From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
| Launch Clk | clk_x1[R] |
| Latch Clk | clk_x1[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_x1 | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 9 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n550_s2/I1 |
| 1.621 | 0.555 | tINS | FF | 3 | u_la0_top/u_ao_mem_ctrl/n550_s2/F |
| 2.095 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n548_s2/I2 |
| 2.548 | 0.453 | tINS | FF | 3 | u_la0_top/u_ao_mem_ctrl/n548_s2/F |
| 3.022 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n547_s2/I1 |
| 3.577 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n547_s2/F |
| 4.051 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n547_s1/I0 |
| 4.568 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n547_s1/F |
| 5.042 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_x1 | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.080, 44.425%; route: 2.370, 50.620%; tC2Q: 0.232, 4.955% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 5.321 |
| Data Arrival Time | 5.004 |
| Data Required Time | 10.325 |
| From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
| Launch Clk | clk_x1[R] |
| Latch Clk | clk_x1[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_x1 | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
| 0.592 | 0.232 | tC2Q | RF | 8 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s8/I0 |
| 1.583 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s8/F |
| 2.057 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s5/I1 |
| 2.612 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n545_s5/F |
| 3.086 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n545_s4/I0 |
| 3.603 | 0.517 | tINS | FF | 10 | u_la0_top/u_ao_mem_ctrl/n545_s4/F |
| 4.077 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n551_s1/I2 |
| 4.530 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n551_s1/F |
| 5.004 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_x1 | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 204 | clk_x1_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.042, 43.971%; route: 2.370, 51.033%; tC2Q: 0.232, 4.996% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |