Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR2\data\ddr2_5a\ddr2_memory_interface.v
C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR2\data\ddr2_5a\DDR2_TOP.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.02
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Thu Mar 21 17:18:53 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DDR2_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.121MB
Running netlist conversion:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.147s, Peak memory usage = 181.121MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.539s, Peak memory usage = 181.121MB
    Optimizing Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.297s, Peak memory usage = 181.121MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.121MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.121MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 181.121MB
    Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 181.121MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 181.121MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.706s, Peak memory usage = 181.121MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.466s, Peak memory usage = 181.121MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 181.121MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 189.379MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.66s, Peak memory usage = 189.379MB
Generate output files:
    CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.828s, Peak memory usage = 196.309MB
Total Time and Memory Usage CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 196.309MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 661
I/O Buf 653
    IBUF 324
    OBUF 288
    TBUF 4
    IOBUF 32
    ELVDS_OBUF 1
    ELVDS_IOBUF 4
Register 4942
    DFFRE 1015
    DFFPE 61
    DFFCE 3866
LUT 3675
    LUT2 915
    LUT3 1633
    LUT4 1127
ALU 145
    ALU 145
INV 25
    INV 25
IOLOGIC 126
    IDES8_MEM 32
    OSER8 22
    OSER8_MEM 40
    IODELAY 32
BSRAM 24
    SDPB 8
    SDPX9B 16
CLOCK 6
    CLKDIV 1
    DQS 4
    DDRDLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3845(3700 LUT, 145 ALU) / 23040 17%
Register 4942 / 23685 21%
  --Register as Latch 0 / 23685 0%
  --Register as FF 4942 / 23685 21%
BSRAM 24 / 56 43%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 memory_clk_ibuf/I memory_clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 memory_clk 100.000(MHz) 1164.144(MHz) 1 TOP
2 clk 100.000(MHz) 220.933(MHz) 6 TOP
3 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 25.000(MHz) 173.160(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.167
Data Arrival Time 2.351
Data Required Time 5.518
From gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0
To gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.317 0.317 tCL RR 5050 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.692 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK
1.075 0.382 tC2Q RR 8 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q
1.450 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0
1.976 0.526 tINS RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F
2.351 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 100 memory_clk_ibuf/O
6.037 0.350 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.003 -0.035 tUnc gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.518 -0.484 tSu 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.345
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.167
Data Arrival Time 2.351
Data Required Time 5.518
From gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0
To gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.317 0.317 tCL RR 5050 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.692 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK
1.075 0.382 tC2Q RR 8 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q
1.450 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0
1.976 0.526 tINS RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F
2.351 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 100 memory_clk_ibuf/O
6.037 0.350 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.003 -0.035 tUnc gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.518 -0.484 tSu 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.345
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 3.167
Data Arrival Time 2.351
Data Required Time 5.518
From gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.317 0.317 tCL RR 5050 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.692 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
1.075 0.382 tC2Q RR 8 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
1.450 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
1.976 0.526 tINS RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
2.351 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 100 memory_clk_ibuf/O
6.037 0.350 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.003 -0.035 tUnc gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.518 -0.484 tSu 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.345
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 3.167
Data Arrival Time 2.351
Data Required Time 5.518
From gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.317 0.317 tCL RR 5050 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.692 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
1.075 0.382 tC2Q RR 8 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
1.450 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
1.976 0.526 tINS RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
2.351 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 100 memory_clk_ibuf/O
6.037 0.350 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.003 -0.035 tUnc gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.518 -0.484 tSu 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.345
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.249
Data Arrival Time 35.345
Data Required Time 40.594
From gw2mc_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To gw2mc_top/u_ddr_phy_top/u_ddr_init/init_state.PRE_ALL_CMD_WAIT_s0
Launch Clk clk[R]
Latch Clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
30.000 0.000 clk
30.000 0.000 tCL RR 1 clk_ibuf/I
30.683 0.683 tINS RR 39 clk_ibuf/O
31.058 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
31.440 0.382 tC2Q RR 3 gw2mc_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
31.815 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s23/I0
32.341 0.526 tINS RR 3 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s23/F
32.716 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.RELEASE_DLL_RST_s25/I2
33.178 0.461 tINS RR 12 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.RELEASE_DLL_RST_s25/F
33.553 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s24/I1
34.069 0.516 tINS RR 5 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s24/F
34.444 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.PRE_ALL_CMD_WAIT_s22/I0
34.970 0.526 tINS RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.PRE_ALL_CMD_WAIT_s22/F
35.345 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_state.PRE_ALL_CMD_WAIT_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
40.318 0.317 tCL RR 5050 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
40.693 0.375 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_state.PRE_ALL_CMD_WAIT_s0/CLK
40.658 -0.035 tUnc gw2mc_top/u_ddr_phy_top/u_ddr_init/init_state.PRE_ALL_CMD_WAIT_s0
40.594 -0.064 tSu 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/init_state.PRE_ALL_CMD_WAIT_s0
Path Statistics:
Clock Skew: -0.365
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.030, 47.347%; route: 1.875, 43.732%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%