Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\impl\gwsynthesis\ddr2_state.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\src\ddr2_phy.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\src\ddr2_tim.sdc
Tool Version	V1.9.9.02
Part Number	GW5A-EV25UG324SES
Device	GW5A-25
Device Version	A
Created Time	Thu Mar 21 17:21:09 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 0C ES
Hold Delay Model	Fast 1.26V 85C ES
Numbers of Paths Analyzed	18512
Numbers of Endpoints Analyzed	27919
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Objects
tck_pad_i	Base	50.000	20.000	25.000	tck_pad_i
clk100	Base	10.000	100.000	5.000	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
clkin	Base	40.000	25.000	20.000	clk
mem_clk	Base	2.500	400.000	1.250	Gowin_PLL_inst/PLLA_inst/CLKOUT2

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	tck_pad_i	20.000(MHz)	78.652(MHz)	4	TOP
2	clk100	100.000(MHz)	100.905(MHz)	6	TOP
3	mem_clk	400.000(MHz)	2016.129(MHz)	1	TOP

No timing paths to get frequency of clkin!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
clk100	Setup	0.000	0
clk100	Hold	0.000	0
clkin	Setup	0.000	0
clkin	Hold	0.000	0
mem_clk	Setup	0.000	0
mem_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.090	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DO[28]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1/CE	clk100:[R]	clk100:[R]	10.000	0.000	9.599
2	0.338	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DO[13]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1/CE	clk100:[R]	clk100:[R]	10.000	-0.002	9.352
3	0.627	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DO[28]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1/D	clk100:[R]	clk100:[R]	10.000	0.000	9.309
4	1.227	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2SRE_s0/D	clk100:[R]	clk100:[R]	10.000	-0.006	8.715
5	1.327	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_SREE_s0/D	clk100:[R]	clk100:[R]	10.000	0.012	8.597
6	1.396	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DO[13]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1/D	clk100:[R]	clk100:[R]	10.000	-0.002	8.542
7	1.424	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2AR_s0/D	clk100:[R]	clk100:[R]	10.000	-0.017	8.535
8	1.467	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2REF_s0/D	clk100:[R]	clk100:[R]	10.000	-0.006	8.475
9	1.472	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2SRE_s0/D	clk100:[R]	clk100:[R]	10.000	-0.006	8.470
10	1.534	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_UPDATA_DQS_WAITE_s0/D	clk100:[R]	clk100:[R]	10.000	0.016	8.386
11	1.542	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2WR_s0/D	clk100:[R]	clk100:[R]	10.000	0.027	8.367
12	1.581	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/rburst_cnt_10_s1/CE	clk100:[F]	clk100:[R]	5.000	-0.024	3.131
13	1.606	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_POWERON_s0/D	clk100:[R]	clk100:[R]	10.000	0.027	8.304
14	1.627	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DO[30]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_1_s1/CE	clk100:[R]	clk100:[R]	10.000	-0.002	8.064
15	1.638	u_rd/c_s.WR_ROW_CH_s4/Q	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_181_s0/D	clk100:[R]	clk100:[R]	10.000	0.022	8.277
16	1.661	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2RD_s0/D	clk100:[R]	clk100:[R]	10.000	0.027	8.249
17	1.679	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2REF_s0/D	clk100:[R]	clk100:[R]	10.000	-0.004	8.261
18	1.680	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2AR_s0/D	clk100:[R]	clk100:[R]	10.000	-0.002	8.259
19	1.746	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_IDLE_s0/D	clk100:[R]	clk100:[R]	10.000	0.007	8.184
20	1.790	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_R2W_s0/D	clk100:[R]	clk100:[R]	10.000	0.033	8.114
21	1.792	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_rdata_valid_r_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s1/CE	clk100:[R]	clk100:[R]	10.000	-0.003	7.900
22	1.802	u_rd/repeatt_s2/Q	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_26_s0/D	clk100:[R]	clk100:[R]	10.000	0.061	8.074
23	1.802	u_rd/repeatt_s2/Q	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_146_s0/D	clk100:[R]	clk100:[R]	10.000	0.061	8.074
24	1.805	u_rd/repeatt_s2/Q	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_18_s0/D	clk100:[R]	clk100:[R]	10.000	0.045	8.086
25	1.805	u_rd/repeatt_s2/Q	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_22_s0/D	clk100:[R]	clk100:[R]	10.000	0.045	8.086

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.067	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[1]	clk100:[R]	clk100:[R]	0.013	0.304
2	0.072	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_125_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[17]	clk100:[R]	clk100:[R]	0.018	0.304
3	0.083	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_115_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[7]	clk100:[R]	clk100:[R]	0.026	0.306
4	0.161	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]	clk100:[R]	clk100:[R]	0.013	0.397
5	0.166	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_118_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[10]	clk100:[R]	clk100:[R]	0.018	0.397
6	0.175	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_112_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[4]	clk100:[R]	clk100:[R]	0.008	0.416
7	0.177	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[8]	clk100:[R]	clk100:[R]	0.026	0.400
8	0.180	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_120_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[12]	clk100:[R]	clk100:[R]	0.013	0.416
9	0.186	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2]	clk100:[R]	clk100:[R]	0.019	0.416
10	0.187	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_119_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[11]	clk100:[R]	clk100:[R]	0.013	0.424
11	0.191	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[16]	clk100:[R]	clk100:[R]	0.024	0.416
12	0.198	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[13]	clk100:[R]	clk100:[R]	0.028	0.419
13	0.202	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen/D2	clk100:[R]	clk100:[R]	-0.002	0.299
14	0.202	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen/D2	clk100:[R]	clk100:[R]	-0.002	0.299
15	0.203	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen/D0	clk100:[R]	clk100:[R]	-0.002	0.300
16	0.205	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_184_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[4]	clk100:[R]	clk100:[R]	0.023	0.431
17	0.208	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D6	clk100:[R]	clk100:[R]	-0.002	0.305
18	0.208	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D4	clk100:[R]	clk100:[R]	-0.002	0.305
19	0.214	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen/D3	clk100:[R]	clk100:[R]	-0.002	0.299
20	0.214	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen/D3	clk100:[R]	clk100:[R]	-0.002	0.299
21	0.215	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen/D1	clk100:[R]	clk100:[R]	-0.002	0.300
22	0.220	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D7	clk100:[R]	clk100:[R]	-0.002	0.305
23	0.220	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D5	clk100:[R]	clk100:[R]	-0.002	0.305
24	0.248	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_122_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[14]	clk100:[R]	clk100:[R]	0.024	0.474
25	0.254	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_260_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/DI[8]	clk100:[R]	clk100:[R]	-0.018	0.520

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.135	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.038	3.480
2	1.146	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.027	3.480
3	1.289	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.050	3.314
4	1.289	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.050	3.314
5	1.289	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.050	3.314
6	1.332	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.025	3.296
7	1.333	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.023	3.296
8	1.497	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.043	3.113
9	1.498	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.042	3.113
10	1.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.036	3.113
11	1.698	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.034	2.920
12	1.700	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.032	2.920
13	2.158	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk100:[F]	clk100:[R]	5.000	-0.002	2.496
14	2.158	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk100:[F]	clk100:[R]	5.000	-0.002	2.496
15	2.168	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	clk100:[F]	clk100:[R]	5.000	-0.012	2.496
16	2.168	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	clk100:[F]	clk100:[R]	5.000	-0.012	2.496
17	2.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk100:[F]	clk100:[R]	5.000	0.043	2.432
18	2.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.043	2.432
19	2.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.043	2.432
20	2.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.043	2.432
21	2.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.043	2.432
22	2.181	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.040	2.431
23	2.192	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.045	2.415
24	2.192	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk100:[F]	clk100:[R]	5.000	0.045	2.415
25	4.617	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/PRESET	clk100:[R]	clk100:[R]	10.000	-0.025	5.060

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.610	rstni_s0/Q	u_pll_mDRP_intf/c_s.OP_WR1_s4/CLEAR	clkin:[R]	clkin:[R]	-0.010	0.431
2	0.610	rstni_s0/Q	u_pll_mDRP_intf/c_s.OP_RD_s1/CLEAR	clkin:[R]	clkin:[R]	-0.010	0.431
3	0.610	rstni_s0/Q	u_pll_mDRP_intf/cnt_0_s0/CLEAR	clkin:[R]	clkin:[R]	-0.010	0.431
4	0.610	rstni_s0/Q	u_pll_mDRP_intf/cnt_1_s0/CLEAR	clkin:[R]	clkin:[R]	-0.010	0.431
5	0.610	rstni_s0/Q	u_pll_mDRP_intf/cnt_2_s0/CLEAR	clkin:[R]	clkin:[R]	-0.010	0.431
6	0.615	rstni_s0/Q	u_pll_mDRP_intf/c_s.OP_WR_s5/CLEAR	clkin:[R]	clkin:[R]	-0.005	0.431
7	0.615	rstni_s0/Q	u_pll_mDRP_intf/c_s.IDLE_s0/PRESET	clkin:[R]	clkin:[R]	-0.005	0.431
8	0.615	rstni_s0/Q	u_pll_mDRP_intf/pll_lock_r_s0/CLEAR	clkin:[R]	clkin:[R]	-0.005	0.431
9	0.615	rstni_s0/Q	u_pll_mDRP_intf/c_s.WAIT_R_s0/CLEAR	clkin:[R]	clkin:[R]	-0.005	0.431
10	0.734	pll_lock_rr_s0/Q	wr_s0/CLEAR	clkin:[R]	clkin:[R]	-0.003	0.549
11	0.832	rstni_s0/Q	u_pll_mDRP_intf/mdrp_wdata_7_s4/CLEAR	clkin:[R]	clkin:[R]	-0.008	0.651
12	0.832	rstni_s0/Q	u_pll_mDRP_intf/mdrp_inc_s0/CLEAR	clkin:[R]	clkin:[R]	-0.008	0.651
13	0.832	rstni_s0/Q	u_pll_mDRP_intf/mdrp_op_0_s0/CLEAR	clkin:[R]	clkin:[R]	-0.008	0.651
14	0.832	rstni_s0/Q	u_pll_mDRP_intf/mdrp_op_1_s0/CLEAR	clkin:[R]	clkin:[R]	-0.008	0.651
15	2.279	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR	clk100:[R]	clk100:[R]	-0.005	2.095
16	2.279	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR	clk100:[R]	clk100:[R]	-0.005	2.095
17	2.279	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR	clk100:[R]	clk100:[R]	-0.005	2.095
18	2.279	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR	clk100:[R]	clk100:[R]	-0.005	2.095
19	2.284	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR	clk100:[R]	clk100:[R]	0.000	2.095
20	2.284	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR	clk100:[R]	clk100:[R]	0.000	2.095
21	2.284	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR	clk100:[R]	clk100:[R]	0.000	2.095
22	2.284	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR	clk100:[R]	clk100:[R]	0.000	2.095
23	2.284	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR	clk100:[R]	clk100:[R]	0.000	2.095
24	2.284	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR	clk100:[R]	clk100:[R]	0.000	2.095
25	2.504	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0/CLEAR	clk100:[R]	clk100:[R]	-0.015	2.330

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.499	4.499	1.000	Low Pulse Width	clk100	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
2	3.499	4.499	1.000	Low Pulse Width	clk100	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
3	3.499	4.499	1.000	Low Pulse Width	clk100	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s
4	3.499	4.499	1.000	Low Pulse Width	clk100	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
5	3.499	4.499	1.000	Low Pulse Width	clk100	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
6	3.499	4.499	1.000	Low Pulse Width	clk100	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s
7	3.499	4.499	1.000	Low Pulse Width	clk100	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
8	3.499	4.499	1.000	Low Pulse Width	clk100	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s
9	3.499	4.499	1.000	Low Pulse Width	clk100	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s
10	3.499	4.499	1.000	Low Pulse Width	clk100	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.090
Data Arrival Time	10.458
Data Required Time	10.548
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.860	0.860	tNET	RR	32	BSRAM_R10[25]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB
3.120	2.260	tC2Q	RF	2	BSRAM_R10[25]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DO[28]
4.670	1.550	tNET	FF	1	R8C60[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s14/I3
5.186	0.516	tINS	FR	1	R8C60[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s14/F
5.343	0.157	tNET	RR	1	R9C60[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s5/I2
5.865	0.521	tINS	RR	1	R9C60[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s5/F
6.598	0.734	tNET	RR	1	R12C60[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s3/I1
7.125	0.526	tINS	RR	1	R12C60[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s3/F
8.711	1.586	tNET	RR	1	R30C60[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s2/I1
8.973	0.262	tINS	RR	2	R30C60[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s2/F
9.906	0.933	tNET	RR	1	R36C65[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s3/I1
10.321	0.415	tINS	RR	1	R36C65[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s3/F
10.458	0.137	tNET	RR	1	R36C65[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.859	0.859	tNET	RR	1	R36C65[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1/CLK
10.548	-0.311	tSu		1	R36C65[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.860, 100.000%
Arrival Data Path Delay	cell: 2.241, 23.349%; route: 5.097, 53.106%; tC2Q: 2.260, 23.545%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.859, 100.000%

Path2

Path Summary:

Slack	0.338
Data Arrival Time	10.212
Data Required Time	10.551
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.860	0.860	tNET	RR	32	BSRAM_R10[21]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB
3.120	2.260	tC2Q	RR	2	BSRAM_R10[21]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DO[13]
4.070	0.950	tNET	RR	1	R8C63[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s13/I3
4.591	0.521	tINS	RR	1	R8C63[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s13/F
4.918	0.327	tNET	RR	1	R8C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s5/I1
5.435	0.516	tINS	RR	1	R8C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s5/F
6.168	0.734	tNET	RR	1	R12C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s3/I1
6.630	0.461	tINS	RR	1	R12C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s3/F
7.740	1.110	tNET	RR	1	R23C60[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s2/I1
8.201	0.461	tINS	RR	2	R23C60[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s2/F
9.140	0.939	tNET	RR	1	R29C62[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s3/I1
9.402	0.262	tINS	RR	1	R29C62[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s3/F
10.212	0.810	tNET	RR	1	R29C62[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.862	0.862	tNET	RR	1	R29C62[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1/CLK
10.551	-0.311	tSu		1	R29C62[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.860, 100.000%
Arrival Data Path Delay	cell: 2.222, 23.764%; route: 4.870, 52.072%; tC2Q: 2.260, 24.165%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.862, 100.000%

Path3

Path Summary:

Slack	0.627
Data Arrival Time	10.168
Data Required Time	10.796
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.860	0.860	tNET	RR	32	BSRAM_R10[25]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB
3.120	2.260	tC2Q	RF	2	BSRAM_R10[25]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[3].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DO[28]
4.670	1.550	tNET	FF	1	R8C60[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s14/I3
5.186	0.516	tINS	FR	1	R8C60[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s14/F
5.343	0.157	tNET	RR	1	R9C60[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s5/I2
5.865	0.521	tINS	RR	1	R9C60[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s5/F
6.598	0.734	tNET	RR	1	R12C60[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s3/I1
7.125	0.526	tINS	RR	1	R12C60[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s3/F
8.711	1.586	tNET	RR	1	R30C60[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s2/I1
8.973	0.262	tINS	RR	2	R30C60[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n3775_s2/F
10.168	1.195	tNET	RR	1	R36C65[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.859	0.859	tNET	RR	1	R36C65[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1/CLK
10.796	-0.064	tSu		1	R36C65[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_3_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.860, 100.000%
Arrival Data Path Delay	cell: 1.826, 19.619%; route: 5.223, 56.103%; tC2Q: 2.260, 24.278%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.859, 100.000%

Path4

Path Summary:

Slack	1.227
Data Arrival Time	9.584
Data Required Time	10.811
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2SRE_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
8.151	0.910	tNET	RR	1	R31C47[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AW_s40/I2
8.667	0.516	tINS	RR	4	R31C47[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AW_s40/F
9.057	0.390	tNET	RR	1	R34C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2SRE_s37/I0
9.584	0.526	tINS	RR	1	R34C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2SRE_s37/F
9.584	0.000	tNET	RR	1	R34C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2SRE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.874	0.874	tNET	RR	1	R34C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2SRE_s0/CLK
10.811	-0.064	tSu		1	R34C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2SRE_s0

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.631, 30.192%; route: 5.701, 65.419%; tC2Q: 0.382, 4.389%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%

Path5

Path Summary:

Slack	1.327
Data Arrival Time	9.466
Data Required Time	10.793
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_SREE_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
7.681	0.440	tNET	RR	1	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/I2
8.096	0.415	tINS	RR	7	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/F
9.005	0.909	tNET	RR	1	R32C46[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREE_s37/I0
9.466	0.461	tINS	RR	1	R32C46[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREE_s37/F
9.466	0.000	tNET	RR	1	R32C46[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_SREE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.857	0.857	tNET	RR	1	R32C46[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_SREE_s0/CLK
10.793	-0.064	tSu		1	R32C46[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_SREE_s0

Path Statistics:

Clock Skew	-0.012
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.465, 28.671%; route: 5.750, 66.880%; tC2Q: 0.382, 4.449%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path6

Path Summary:

Slack	1.396
Data Arrival Time	9.402
Data Required Time	10.798
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.860	0.860	tNET	RR	32	BSRAM_R10[21]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB
3.120	2.260	tC2Q	RR	2	BSRAM_R10[21]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DO[13]
4.070	0.950	tNET	RR	1	R8C63[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s13/I3
4.591	0.521	tINS	RR	1	R8C63[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s13/F
4.918	0.327	tNET	RR	1	R8C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s5/I1
5.435	0.516	tINS	RR	1	R8C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s5/F
6.168	0.734	tNET	RR	1	R12C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s3/I1
6.630	0.461	tINS	RR	1	R12C61[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s3/F
7.740	1.110	tNET	RR	1	R23C60[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s2/I1
8.201	0.461	tINS	RR	2	R23C60[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2548_s2/F
9.402	1.201	tNET	RR	1	R29C62[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.862	0.862	tNET	RR	1	R29C62[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1/CLK
10.798	-0.064	tSu		1	R29C62[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_0_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.860, 100.000%
Arrival Data Path Delay	cell: 1.960, 22.944%; route: 4.323, 50.600%; tC2Q: 2.260, 26.456%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.862, 100.000%

Path7

Path Summary:

Slack	1.424
Data Arrival Time	9.404
Data Required Time	10.828
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2AR_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
7.171	0.740	tNET	RR	1	R29C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s42/I0
7.434	0.262	tINS	RR	1	R29C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s42/F
7.816	0.382	tNET	RR	1	R31C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s41/I3
8.277	0.461	tINS	RR	4	R31C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s41/F
9.114	0.836	tNET	RR	1	R27C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AR_s38/I0
9.404	0.290	tINS	RF	1	R27C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AR_s38/F
9.404	0.000	tNET	FF	1	R27C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2AR_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.886	0.886	tNET	RR	1	R27C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2AR_s0/CLK
10.828	-0.058	tSu		1	R27C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2AR_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.340, 27.417%; route: 5.813, 68.102%; tC2Q: 0.382, 4.482%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path8

Path Summary:

Slack	1.467
Data Arrival Time	9.344
Data Required Time	10.811
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2REF_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
7.171	0.740	tNET	RR	1	R29C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s42/I0
7.434	0.262	tINS	RR	1	R29C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s42/F
7.816	0.382	tNET	RR	1	R31C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s41/I3
8.277	0.461	tINS	RR	4	R31C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s41/F
8.822	0.545	tNET	RR	1	R34C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2REF_s37/I0
9.344	0.521	tINS	RR	1	R34C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2REF_s37/F
9.344	0.000	tNET	RR	1	R34C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2REF_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.874	0.874	tNET	RR	1	R34C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2REF_s0/CLK
10.811	-0.064	tSu		1	R34C47[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2REF_s0

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.571, 30.339%; route: 5.521, 65.147%; tC2Q: 0.382, 4.513%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%

Path9

Path Summary:

Slack	1.472
Data Arrival Time	9.339
Data Required Time	10.811
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2SRE_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
7.171	0.740	tNET	RR	1	R29C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s42/I0
7.434	0.262	tINS	RR	1	R29C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s42/F
7.816	0.382	tNET	RR	1	R31C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s41/I3
8.277	0.461	tINS	RR	4	R31C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2AW_s41/F
8.822	0.545	tNET	RR	1	R34C47[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2SRE_s37/I0
9.339	0.516	tINS	RR	1	R34C47[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_RP2SRE_s37/F
9.339	0.000	tNET	RR	1	R34C47[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2SRE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.874	0.874	tNET	RR	1	R34C47[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2SRE_s0/CLK
10.811	-0.064	tSu		1	R34C47[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_RP2SRE_s0

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.566, 30.298%; route: 5.521, 65.186%; tC2Q: 0.382, 4.516%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%

Path10

Path Summary:

Slack	1.534
Data Arrival Time	9.255
Data Required Time	10.789
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_UPDATA_DQS_WAITE_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
7.681	0.440	tNET	RR	1	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/I2
8.096	0.415	tINS	RR	7	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/F
8.729	0.632	tNET	RR	1	R29C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s49/I3
9.255	0.526	tINS	RR	1	R29C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s49/F
9.255	0.000	tNET	RR	1	R29C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_UPDATA_DQS_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.852	0.852	tNET	RR	1	R29C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_UPDATA_DQS_WAITE_s0/CLK
10.789	-0.064	tSu		1	R29C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_UPDATA_DQS_WAITE_s0

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.530, 30.168%; route: 5.474, 65.271%; tC2Q: 0.382, 4.561%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%

Path11

Path Summary:

Slack	1.542
Data Arrival Time	9.236
Data Required Time	10.778
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2WR_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
8.009	0.767	tNET	RR	1	R31C47[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2WR_s39/I1
8.525	0.516	tINS	RR	2	R31C47[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2WR_s39/F
8.720	0.195	tNET	RR	1	R31C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2WR_s38/I0
9.236	0.516	tINS	RR	1	R31C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2WR_s38/F
9.236	0.000	tNET	RR	1	R31C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2WR_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.842	0.842	tNET	RR	1	R31C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2WR_s0/CLK
10.778	-0.064	tSu		1	R31C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2WR_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.621, 31.327%; route: 5.364, 64.102%; tC2Q: 0.382, 4.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path12

Path Summary:

Slack	1.581
Data Arrival Time	8.986
Data Required Time	10.567
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/rburst_cnt_10_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.854	0.854	tNET	FF	1	R18C65[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/CLK
6.288	0.434	tC2Q	FR	1	R18C65[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/Q
6.426	0.137	tNET	RR	1	R18C65[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_t_s0/I1
6.952	0.526	tINS	RR	2	R18C65[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_t_s0/F
7.687	0.735	tNET	RR	1	R20C66[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/rburst_cnt_19_s3/I0
7.952	0.265	tINS	RR	10	R20C66[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/rburst_cnt_19_s3/F
8.986	1.034	tNET	RR	1	R18C67[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/rburst_cnt_10_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.878	0.878	tNET	RR	1	R18C67[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/rburst_cnt_10_s1/CLK
10.567	-0.311	tSu		1	R18C67[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/rburst_cnt_10_s1

Path Statistics:

Clock Skew	0.024
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.854, 100.000%
Arrival Data Path Delay	cell: 0.791, 25.269%; route: 1.906, 60.878%; tC2Q: 0.434, 13.852%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.878, 100.000%

Path13

Path Summary:

Slack	1.606
Data Arrival Time	9.172
Data Required Time	10.778
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_POWERON_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
7.681	0.440	tNET	RR	1	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/I2
8.096	0.415	tINS	RR	7	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/F
8.646	0.550	tNET	RR	1	R31C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_POWERON_s36/I0
9.172	0.526	tINS	RR	1	R31C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_POWERON_s36/F
9.172	0.000	tNET	RR	1	R31C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_POWERON_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.842	0.842	tNET	RR	1	R31C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_POWERON_s0/CLK
10.778	-0.064	tSu		1	R31C49[2][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_POWERON_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.530, 30.468%; route: 5.391, 64.925%; tC2Q: 0.382, 4.606%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path14

Path Summary:

Slack	1.627
Data Arrival Time	8.923
Data Required Time	10.551
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_1_s1
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.860	0.860	tNET	RR	32	BSRAM_R28[25]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB
3.120	2.260	tC2Q	RR	2	BSRAM_R28[25]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DO[30]
5.456	2.336	tNET	RR	1	R27C59[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s10/I3
5.917	0.461	tINS	RR	1	R27C59[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s10/F
6.075	0.157	tNET	RR	1	R27C60[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s4/I2
6.596	0.521	tINS	RR	1	R27C60[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s4/F
6.598	0.003	tNET	RR	1	R27C60[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s3/I0
7.125	0.526	tINS	RR	1	R27C60[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s3/F
7.668	0.544	tNET	RR	1	R29C60[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s2/I1
8.130	0.461	tINS	RR	2	R29C60[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/n2957_s2/F
8.325	0.195	tNET	RR	1	R29C62[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_1_s3/I1
8.786	0.461	tINS	RR	1	R29C62[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_1_s3/F
8.923	0.137	tNET	RR	1	R29C62[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.862	0.862	tNET	RR	1	R29C62[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_1_s1/CLK
10.551	-0.311	tSu		1	R29C62[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_init/readback_check_1_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.860, 100.000%
Arrival Data Path Delay	cell: 2.431, 30.150%; route: 3.373, 41.823%; tC2Q: 2.260, 28.027%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.862, 100.000%

Path15

Path Summary:

Slack	1.638
Data Arrival Time	9.170
Data Required Time	10.807
From	u_rd/c_s.WR_ROW_CH_s4
To	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_181_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.893	0.893	tNET	RR	1	R6C36[1][A]	u_rd/c_s.WR_ROW_CH_s4/CLK
1.261	0.368	tC2Q	RF	37	R6C36[1][A]	u_rd/c_s.WR_ROW_CH_s4/Q
2.371	1.110	tNET	FF	1	R6C31[3][B]	u_rd/u_DDR2_TOP_39_s1/I0
2.892	0.521	tINS	FR	9	R6C31[3][B]	u_rd/u_DDR2_TOP_39_s1/F
3.836	0.944	tNET	RR	1	R3C33[3][A]	u_rd/u_DDR2_TOP_11_s2/I3
4.126	0.290	tINS	RF	1	R3C33[3][A]	u_rd/u_DDR2_TOP_11_s2/F
4.452	0.326	tNET	FF	1	R2C33[3][A]	u_rd/u_DDR2_TOP_11_s0/I3
4.867	0.415	tINS	FR	1	R2C33[3][A]	u_rd/u_DDR2_TOP_11_s0/F
5.025	0.157	tNET	RR	1	R3C33[0][A]	u_rd/u_DDR2_TOP_11_s/I0
5.287	0.262	tINS	RR	8	R3C33[0][A]	u_rd/u_DDR2_TOP_11_s/F
8.755	3.468	tNET	RR	1	R11C47[3][A]	u_DDR2_TOP/gw2mc_top/n113_s1/I0
9.170	0.415	tINS	RR	1	R11C47[3][A]	u_DDR2_TOP/gw2mc_top/n113_s1/F
9.170	0.000	tNET	RR	1	R11C47[3][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_181_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.871	0.871	tNET	RR	1	R11C47[3][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_181_s0/CLK
10.807	-0.064	tSu		1	R11C47[3][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_181_s0

Path Statistics:

Clock Skew	-0.022
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.893, 100.000%
Arrival Data Path Delay	cell: 1.904, 23.002%; route: 6.005, 72.558%; tC2Q: 0.368, 4.440%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.871, 100.000%

Path16

Path Summary:

Slack	1.661
Data Arrival Time	9.117
Data Required Time	10.778
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2RD_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
8.009	0.767	tNET	RR	1	R31C47[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2WR_s39/I1
8.525	0.516	tINS	RR	2	R31C47[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2WR_s39/F
8.855	0.330	tNET	RR	1	R31C49[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2RD_s38/I0
9.117	0.262	tINS	RR	1	R31C49[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_ACT2RD_s38/F
9.117	0.000	tNET	RR	1	R31C49[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2RD_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.842	0.842	tNET	RR	1	R31C49[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2RD_s0/CLK
10.778	-0.064	tSu		1	R31C49[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_ACT2RD_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.368, 28.701%; route: 5.499, 66.662%; tC2Q: 0.382, 4.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path17

Path Summary:

Slack	1.679
Data Arrival Time	9.130
Data Required Time	10.809
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2REF_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
8.151	0.910	tNET	RR	1	R31C47[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AW_s40/I2
8.667	0.516	tINS	RR	4	R31C47[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AW_s40/F
8.867	0.200	tNET	RR	1	R33C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2REF_s37/I0
9.130	0.262	tINS	RR	1	R33C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2REF_s37/F
9.130	0.000	tNET	RR	1	R33C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2REF_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.873	0.873	tNET	RR	1	R33C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2REF_s0/CLK
10.809	-0.064	tSu		1	R33C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2REF_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.368, 28.658%; route: 5.511, 66.712%; tC2Q: 0.382, 4.630%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.873, 100.000%

Path18

Path Summary:

Slack	1.680
Data Arrival Time	9.127
Data Required Time	10.807
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2AR_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
8.151	0.910	tNET	RR	1	R31C47[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AW_s40/I2
8.667	0.516	tINS	RR	4	R31C47[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AW_s40/F
8.865	0.197	tNET	RR	1	R29C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AR_s38/I2
9.127	0.262	tINS	RR	1	R29C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_WP2AR_s38/F
9.127	0.000	tNET	RR	1	R29C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2AR_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.871	0.871	tNET	RR	1	R29C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2AR_s0/CLK
10.807	-0.064	tSu		1	R29C47[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_WP2AR_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.368, 28.667%; route: 5.509, 66.702%; tC2Q: 0.382, 4.631%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.871, 100.000%

Path19

Path Summary:

Slack	1.746
Data Arrival Time	9.052
Data Required Time	10.798
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_IDLE_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
7.681	0.440	tNET	RR	1	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/I2
8.096	0.415	tINS	RR	7	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/F
8.536	0.440	tNET	RR	1	R29C48[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_IDLE_s37/I2
9.052	0.516	tINS	RR	1	R29C48[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_IDLE_s37/F
9.052	0.000	tNET	RR	1	R29C48[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_IDLE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.862	0.862	tNET	RR	1	R29C48[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_IDLE_s0/CLK
10.798	-0.064	tSu		1	R29C48[1][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_IDLE_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.520, 30.793%; route: 5.281, 64.533%; tC2Q: 0.382, 4.674%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.862, 100.000%

Path20

Path Summary:

Slack	1.790
Data Arrival Time	8.982
Data Required Time	10.772
From	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_R2W_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869	0.869	tNET	RR	1	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.251	0.382	tC2Q	RR	61	R36C42[1][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
3.961	2.710	tNET	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/S0
4.214	0.252	tINS	RR	1	R23C44[3][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s1/O
4.214	0.000	tNET	RR	1	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/I0
4.300	0.086	tINS	RR	7	R23C44[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_182_G[0]_s0/O
5.284	0.984	tNET	RR	1	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/I0
5.745	0.461	tINS	RR	5	R27C47[2][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s42/F
5.905	0.160	tNET	RR	1	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/I2
6.431	0.526	tINS	RR	4	R27C48[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_SREI_s41/F
6.979	0.548	tNET	RR	1	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/I1
7.241	0.262	tINS	RR	4	R29C48[0][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s44/F
7.681	0.440	tNET	RR	1	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/I2
8.096	0.415	tINS	RR	7	R30C47[3][B]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_UPDATA_DQS_WAITE_s40/F
8.456	0.360	tNET	RR	1	R30C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_R2W_s37/I0
8.982	0.526	tINS	RR	1	R30C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_nstate.GWMCST_R2W_s37/F
8.982	0.000	tNET	RR	1	R30C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_R2W_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.836	0.836	tNET	RR	1	R30C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_R2W_s0/CLK
10.772	-0.064	tSu		1	R30C49[0][A]	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate.GWMCST_R2W_s0

Path Statistics:

Clock Skew	-0.033
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay	cell: 2.530, 31.182%; route: 5.201, 64.104%; tC2Q: 0.382, 4.714%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.836, 100.000%

Path21

Path Summary:

Slack	1.792
Data Arrival Time	8.757
Data Required Time	10.549
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_rdata_valid_r_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s1
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.857	0.857	tNET	RR	1	R35C81[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_rdata_valid_r_s0/CLK
1.240	0.382	tC2Q	RR	10	R35C81[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_rdata_valid_r_s0/Q
5.715	4.475	tNET	RR	1	R4C58[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error1_1_s6/I1
6.098	0.382	tINS	RF	13	R4C58[3][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error1_1_s6/F
6.735	0.637	tNET	FF	1	R9C58[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s6/I3
7.150	0.415	tINS	FR	1	R9C58[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s6/F
7.884	0.734	tNET	RR	1	R12C58[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s3/I2
8.410	0.526	tINS	RR	1	R12C58[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s3/F
8.757	0.347	tNET	RR	1	R13C59[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.861	0.861	tNET	RR	1	R13C59[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s1/CLK
10.549	-0.311	tSu		1	R13C59[2][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib/eye_calib_error3_3_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%
Arrival Data Path Delay	cell: 1.324, 16.756%; route: 6.194, 78.402%; tC2Q: 0.382, 4.842%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.861, 100.000%

Path22

Path Summary:

Slack	1.802
Data Arrival Time	8.976
Data Required Time	10.778
From	u_rd/repeatt_s2
To	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_26_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.902	0.902	tNET	RR	1	R6C35[1][A]	u_rd/repeatt_s2/CLK
1.285	0.382	tC2Q	RR	17	R6C35[1][A]	u_rd/repeatt_s2/Q
2.904	1.619	tNET	RR	1	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/I1
3.430	0.526	tINS	RR	3	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/F
3.952	0.522	tNET	RR	1	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/I2
4.215	0.262	tINS	RR	17	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/F
4.567	0.352	tNET	RR	1	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/I3
5.089	0.521	tINS	RR	40	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/F
8.460	3.371	tNET	RR	1	R13C49[0][A]	u_DDR2_TOP/gw2mc_top/n268_s1/I0
8.976	0.516	tINS	RR	1	R13C49[0][A]	u_DDR2_TOP/gw2mc_top/n268_s1/F
8.976	0.000	tNET	RR	1	R13C49[0][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.842	0.842	tNET	RR	1	R13C49[0][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_26_s0/CLK
10.778	-0.064	tSu		1	R13C49[0][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_26_s0

Path Statistics:

Clock Skew	-0.061
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay	cell: 1.826, 22.620%; route: 5.865, 72.643%; tC2Q: 0.382, 4.738%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path23

Path Summary:

Slack	1.802
Data Arrival Time	8.976
Data Required Time	10.778
From	u_rd/repeatt_s2
To	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_146_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.902	0.902	tNET	RR	1	R6C35[1][A]	u_rd/repeatt_s2/CLK
1.285	0.382	tC2Q	RR	17	R6C35[1][A]	u_rd/repeatt_s2/Q
2.904	1.619	tNET	RR	1	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/I1
3.430	0.526	tINS	RR	3	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/F
3.952	0.522	tNET	RR	1	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/I2
4.215	0.262	tINS	RR	17	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/F
4.567	0.352	tNET	RR	1	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/I3
5.089	0.521	tINS	RR	40	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/F
8.460	3.371	tNET	RR	1	R13C49[1][A]	u_DDR2_TOP/gw2mc_top/n148_s1/I0
8.976	0.516	tINS	RR	1	R13C49[1][A]	u_DDR2_TOP/gw2mc_top/n148_s1/F
8.976	0.000	tNET	RR	1	R13C49[1][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_146_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.842	0.842	tNET	RR	1	R13C49[1][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_146_s0/CLK
10.778	-0.064	tSu		1	R13C49[1][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_146_s0

Path Statistics:

Clock Skew	-0.061
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay	cell: 1.826, 22.620%; route: 5.865, 72.643%; tC2Q: 0.382, 4.738%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path24

Path Summary:

Slack	1.805
Data Arrival Time	8.989
Data Required Time	10.793
From	u_rd/repeatt_s2
To	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_18_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.902	0.902	tNET	RR	1	R6C35[1][A]	u_rd/repeatt_s2/CLK
1.285	0.382	tC2Q	RR	17	R6C35[1][A]	u_rd/repeatt_s2/Q
2.904	1.619	tNET	RR	1	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/I1
3.430	0.526	tINS	RR	3	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/F
3.952	0.522	tNET	RR	1	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/I2
4.215	0.262	tINS	RR	17	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/F
4.567	0.352	tNET	RR	1	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/I3
5.089	0.521	tINS	RR	40	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/F
8.462	3.374	tNET	RR	1	R14C48[0][A]	u_DDR2_TOP/gw2mc_top/n276_s1/I0
8.989	0.526	tINS	RR	1	R14C48[0][A]	u_DDR2_TOP/gw2mc_top/n276_s1/F
8.989	0.000	tNET	RR	1	R14C48[0][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.857	0.857	tNET	RR	1	R14C48[0][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_18_s0/CLK
10.793	-0.064	tSu		1	R14C48[0][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_18_s0

Path Statistics:

Clock Skew	-0.045
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay	cell: 1.836, 22.708%; route: 5.868, 72.561%; tC2Q: 0.382, 4.730%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path25

Path Summary:

Slack	1.805
Data Arrival Time	8.989
Data Required Time	10.793
From	u_rd/repeatt_s2
To	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_22_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.902	0.902	tNET	RR	1	R6C35[1][A]	u_rd/repeatt_s2/CLK
1.285	0.382	tC2Q	RR	17	R6C35[1][A]	u_rd/repeatt_s2/Q
2.904	1.619	tNET	RR	1	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/I1
3.430	0.526	tINS	RR	3	R3C31[1][A]	u_rd/u_DDR2_TOP_49_s0/F
3.952	0.522	tNET	RR	1	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/I2
4.215	0.262	tINS	RR	17	R7C31[2][B]	u_rd/u_DDR2_TOP_60_s/F
4.567	0.352	tNET	RR	1	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/I3
5.089	0.521	tINS	RR	40	R6C30[3][A]	u_rd/u_DDR2_TOP_46_s0/F
8.462	3.374	tNET	RR	1	R14C48[1][A]	u_DDR2_TOP/gw2mc_top/n272_s1/I0
8.989	0.526	tINS	RR	1	R14C48[1][A]	u_DDR2_TOP/gw2mc_top/n272_s1/F
8.989	0.000	tNET	RR	1	R14C48[1][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.857	0.857	tNET	RR	1	R14C48[1][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_22_s0/CLK
10.793	-0.064	tSu		1	R14C48[1][A]	u_DDR2_TOP/gw2mc_top/gwmc_app_wdf_wdata_22_s0

Path Statistics:

Clock Skew	-0.045
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay	cell: 1.836, 22.708%; route: 5.868, 72.561%; tC2Q: 0.382, 4.730%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.067
Data Arrival Time	0.680
Data Required Time	0.613
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.376	0.376	tNET	RR	1	R8C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0/CLK
0.556	0.180	tC2Q	RR	1	R8C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0/Q
0.680	0.124	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364	0.364	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA
0.613	0.249	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.376, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path2

Path Summary:

Slack	0.072
Data Arrival Time	0.690
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_125_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.386	0.386	tNET	RR	1	R8C15[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_125_s0/CLK
0.566	0.180	tC2Q	RR	1	R8C15[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_125_s0/Q
0.690	0.124	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path3

Path Summary:

Slack	0.083
Data Arrival Time	0.701
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_115_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.395	0.395	tNET	RR	1	R6C15[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_115_s0/CLK
0.575	0.180	tC2Q	RR	1	R6C15[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_115_s0/Q
0.701	0.126	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path4

Path Summary:

Slack	0.161
Data Arrival Time	0.779
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381	0.381	tNET	RR	1	R8C8[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/CLK
0.561	0.180	tC2Q	RR	1	R8C8[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q
0.779	0.217	tNET	RR	1	BSRAM_R10[1]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[1]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[1]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path5

Path Summary:

Slack	0.166
Data Arrival Time	0.784
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_118_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.386	0.386	tNET	RR	1	R8C15[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_118_s0/CLK
0.566	0.180	tC2Q	RR	1	R8C15[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_118_s0/Q
0.784	0.217	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path6

Path Summary:

Slack	0.175
Data Arrival Time	0.793
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_112_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.376	0.376	tNET	RR	1	R8C13[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_112_s0/CLK
0.556	0.180	tC2Q	RR	1	R8C13[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_112_s0/Q
0.793	0.236	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.376, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path7

Path Summary:

Slack	0.177
Data Arrival Time	0.795
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.395	0.395	tNET	RR	1	R6C15[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/CLK
0.575	0.180	tC2Q	RR	1	R6C15[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/Q
0.795	0.220	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.220, 55.000%; tC2Q: 0.180, 45.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path8

Path Summary:

Slack	0.180
Data Arrival Time	0.798
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_120_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381	0.381	tNET	RR	1	R8C14[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_120_s0/CLK
0.561	0.180	tC2Q	RR	1	R8C14[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_120_s0/Q
0.798	0.236	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path9

Path Summary:

Slack	0.186
Data Arrival Time	0.804
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.387	0.387	tNET	RR	1	R7C14[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/CLK
0.567	0.180	tC2Q	RR	1	R7C14[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/Q
0.804	0.236	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.387, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path10

Path Summary:

Slack	0.187
Data Arrival Time	0.805
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_119_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381	0.381	tNET	RR	1	R8C14[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_119_s0/CLK
0.561	0.180	tC2Q	RR	1	R8C14[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_119_s0/Q
0.805	0.244	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path11

Path Summary:

Slack	0.191
Data Arrival Time	0.809
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.392	0.392	tNET	RR	1	R7C15[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/CLK
0.572	0.180	tC2Q	RR	1	R7C15[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_124_s0/Q
0.809	0.236	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path12

Path Summary:

Slack	0.198
Data Arrival Time	0.811
Data Required Time	0.613
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.392	0.392	tNET	RR	1	R5C16[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0/CLK
0.572	0.180	tC2Q	RR	1	R5C16[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_157_s0/Q
0.811	0.239	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364	0.364	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA
0.613	0.249	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Path Statistics:

Clock Skew	-0.028
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 57.015%; tC2Q: 0.180, 42.985%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path13

Path Summary:

Slack	0.202
Data Arrival Time	0.697
Data Required Time	0.496
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398	0.398	tNET	RR	1	R2C68[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0/CLK
0.578	0.180	tC2Q	RR	2	R2C68[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0/Q
0.697	0.119	tNET	RR	1	IOT68[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen/D2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.401	0.401	tNET	RR	1	IOT68[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen/PCLK
0.496	0.095	tHld		1	IOT68[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.398, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.119, 39.749%; tC2Q: 0.180, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.401, 100.000%

Path14

Path Summary:

Slack	0.202
Data Arrival Time	0.692
Data Required Time	0.491
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.393	0.393	tNET	RR	1	R2C61[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0/CLK
0.573	0.180	tC2Q	RR	2	R2C61[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0/Q
0.692	0.119	tNET	RR	1	IOT61[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen/D2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.396	0.396	tNET	RR	1	IOT61[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen/PCLK
0.491	0.095	tHld		1	IOT61[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.393, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.119, 39.749%; tC2Q: 0.180, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.396, 100.000%

Path15

Path Summary:

Slack	0.203
Data Arrival Time	0.693
Data Required Time	0.491
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.393	0.393	tNET	RR	1	R2C77[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0/CLK
0.573	0.180	tC2Q	RR	2	R2C77[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0/Q
0.693	0.120	tNET	RR	1	IOT76[B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.396	0.396	tNET	RR	1	IOT76[B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen/PCLK
0.491	0.095	tHld		1	IOT76[B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.393, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 40.000%; tC2Q: 0.180, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.396, 100.000%

Path16

Path Summary:

Slack	0.205
Data Arrival Time	0.823
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_184_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.392	0.392	tNET	RR	1	R5C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_184_s0/CLK
0.572	0.180	tC2Q	RR	1	R5C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_184_s0/Q
0.823	0.251	tNET	RR	1	BSRAM_R10[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path17

Path Summary:

Slack	0.208
Data Arrival Time	0.708
Data Required Time	0.501
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.403	0.403	tNET	RR	1	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/CLK
0.583	0.180	tC2Q	RR	60	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q
0.708	0.125	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.406	0.406	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/PCLK
0.501	0.095	tHld		1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.403, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 40.984%; tC2Q: 0.180, 59.016%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.406, 100.000%

Path18

Path Summary:

Slack	0.208
Data Arrival Time	0.708
Data Required Time	0.501
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.403	0.403	tNET	RR	1	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/CLK
0.583	0.180	tC2Q	RR	60	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q
0.708	0.125	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.406	0.406	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/PCLK
0.501	0.095	tHld		1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.403, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 40.984%; tC2Q: 0.180, 59.016%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.406, 100.000%

Path19

Path Summary:

Slack	0.214
Data Arrival Time	0.697
Data Required Time	0.484
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398	0.398	tNET	RR	1	R2C68[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0/CLK
0.578	0.180	tC2Q	RR	2	R2C68[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_41_s0/Q
0.697	0.119	tNET	RR	1	IOT68[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen/D3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.401	0.401	tNET	RR	1	IOT68[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen/PCLK
0.484	0.083	tHld		1	IOT68[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[10].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.398, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.119, 39.749%; tC2Q: 0.180, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.401, 100.000%

Path20

Path Summary:

Slack	0.214
Data Arrival Time	0.692
Data Required Time	0.479
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.393	0.393	tNET	RR	1	R2C61[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0/CLK
0.573	0.180	tC2Q	RR	2	R2C61[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_1_s0/Q
0.692	0.119	tNET	RR	1	IOT61[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen/D3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.396	0.396	tNET	RR	1	IOT61[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen/PCLK
0.479	0.083	tHld		1	IOT61[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[0].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.393, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.119, 39.749%; tC2Q: 0.180, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.396, 100.000%

Path21

Path Summary:

Slack	0.215
Data Arrival Time	0.693
Data Required Time	0.479
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.393	0.393	tNET	RR	1	R2C77[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0/CLK
0.573	0.180	tC2Q	RR	2	R2C77[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_32_s0/Q
0.693	0.120	tNET	RR	1	IOT76[B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.396	0.396	tNET	RR	1	IOT76[B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen/PCLK
0.479	0.083	tHld		1	IOT76[B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[8].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.393, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 40.000%; tC2Q: 0.180, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.396, 100.000%

Path22

Path Summary:

Slack	0.220
Data Arrival Time	0.708
Data Required Time	0.489
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.403	0.403	tNET	RR	1	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/CLK
0.583	0.180	tC2Q	RR	60	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q
0.708	0.125	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.406	0.406	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/PCLK
0.489	0.083	tHld		1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.403, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 40.984%; tC2Q: 0.180, 59.016%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.406, 100.000%

Path23

Path Summary:

Slack	0.220
Data Arrival Time	0.708
Data Required Time	0.489
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.403	0.403	tNET	RR	1	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/CLK
0.583	0.180	tC2Q	RR	60	R2C83[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rrr_27_s0/Q
0.708	0.125	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/D5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.406	0.406	tNET	RR	1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen/PCLK
0.489	0.083	tHld		1	IOT83[A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[15].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.403, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 40.984%; tC2Q: 0.180, 59.016%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.406, 100.000%

Path24

Path Summary:

Slack	0.248
Data Arrival Time	0.866
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_122_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.392	0.392	tNET	RR	1	R7C15[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_122_s0/CLK
0.572	0.180	tC2Q	RR	1	R7C15[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_122_s0/Q
0.866	0.294	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[3]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.294, 62.005%; tC2Q: 0.180, 37.995%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path25

Path Summary:

Slack	0.254
Data Arrival Time	0.871
Data Required Time	0.618
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_260_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R12C26[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_260_s0/CLK
0.531	0.180	tC2Q	RR	1	R12C26[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_260_s0/Q
0.871	0.340	tNET	RR	1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369	0.369	tNET	RR	1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/CLKA
0.618	0.249	tHld		1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s

Path Statistics:

Clock Skew	0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.340, 65.385%; tC2Q: 0.180, 34.615%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.135
Data Arrival Time	9.381
Data Required Time	10.516
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.381	3.038	tNET	FF	1	R15C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.863	0.863	tNET	RR	1	R15C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.516	-0.347	tSu		1	R15C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.038
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.038, 87.284%; tC2Q: 0.442, 12.716%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.863, 100.000%

Path2

Path Summary:

Slack	1.146
Data Arrival Time	9.381
Data Required Time	10.527
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.381	3.038	tNET	FF	1	R16C15[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.874	0.874	tNET	RR	1	R16C15[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.527	-0.347	tSu		1	R16C15[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.027
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.038, 87.284%; tC2Q: 0.442, 12.716%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%

Path3

Path Summary:

Slack	1.289
Data Arrival Time	9.215
Data Required Time	10.504
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.215	2.871	tNET	FF	1	R13C20[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.851	0.851	tNET	RR	1	R13C20[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.504	-0.347	tSu		1	R13C20[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.050
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.871, 86.647%; tC2Q: 0.442, 13.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.851, 100.000%

Path4

Path Summary:

Slack	1.289
Data Arrival Time	9.215
Data Required Time	10.504
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.215	2.871	tNET	FF	1	R13C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.851	0.851	tNET	RR	1	R13C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
10.504	-0.347	tSu		1	R13C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.050
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.871, 86.647%; tC2Q: 0.442, 13.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.851, 100.000%

Path5

Path Summary:

Slack	1.289
Data Arrival Time	9.215
Data Required Time	10.504
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.215	2.871	tNET	FF	1	R13C20[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.851	0.851	tNET	RR	1	R13C20[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.504	-0.347	tSu		1	R13C20[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.050
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.871, 86.647%; tC2Q: 0.442, 13.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.851, 100.000%

Path6

Path Summary:

Slack	1.332
Data Arrival Time	9.197
Data Required Time	10.529
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.197	2.854	tNET	FF	1	R17C15[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876	0.876	tNET	RR	1	R17C15[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.529	-0.347	tSu		1	R17C15[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.025
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.854, 86.576%; tC2Q: 0.442, 13.424%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%

Path7

Path Summary:

Slack	1.333
Data Arrival Time	9.197
Data Required Time	10.531
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.197	2.854	tNET	FF	1	R18C15[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.878	0.878	tNET	RR	1	R18C15[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.531	-0.347	tSu		1	R18C15[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.854, 86.576%; tC2Q: 0.442, 13.424%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.878, 100.000%

Path8

Path Summary:

Slack	1.497
Data Arrival Time	9.013
Data Required Time	10.510
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.013	2.670	tNET	FF	1	R17C17[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858	0.857	tNET	RR	1	R17C17[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.510	-0.347	tSu		1	R17C17[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.670, 85.783%; tC2Q: 0.442, 14.217%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path9

Path Summary:

Slack	1.498
Data Arrival Time	9.013
Data Required Time	10.512
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.013	2.670	tNET	FF	1	R18C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.859	0.859	tNET	RR	1	R18C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.512	-0.347	tSu		1	R18C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.042
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.670, 85.783%; tC2Q: 0.442, 14.217%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.859, 100.000%

Path10

Path Summary:

Slack	1.504
Data Arrival Time	9.013
Data Required Time	10.517
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.013	2.670	tNET	FF	1	R16C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.865	0.865	tNET	RR	1	R16C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.517	-0.347	tSu		1	R16C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.036
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.670, 85.783%; tC2Q: 0.442, 14.217%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.865, 100.000%

Path11

Path Summary:

Slack	1.698
Data Arrival Time	8.821
Data Required Time	10.519
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.821	2.478	tNET	FF	1	R17C20[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867	0.867	tNET	RR	1	R17C20[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.519	-0.347	tSu		1	R17C20[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.034
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.478, 84.846%; tC2Q: 0.442, 15.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.867, 100.000%

Path12

Path Summary:

Slack	1.700
Data Arrival Time	8.821
Data Required Time	10.521
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.821	2.478	tNET	FF	1	R18C20[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.869	0.869	tNET	RR	1	R18C20[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.521	-0.347	tSu		1	R18C20[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.032
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.478, 84.846%; tC2Q: 0.442, 15.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.869, 100.000%

Path13

Path Summary:

Slack	2.158
Data Arrival Time	8.397
Data Required Time	10.556
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.397	2.054	tNET	FF	1	R20C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.903	0.903	tNET	RR	1	R20C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
10.556	-0.347	tSu		1	R20C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.054, 82.273%; tC2Q: 0.442, 17.727%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.903, 100.000%

Path14

Path Summary:

Slack	2.158
Data Arrival Time	8.397
Data Required Time	10.556
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.397	2.054	tNET	FF	1	R20C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.903	0.903	tNET	RR	1	R20C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.556	-0.347	tSu		1	R20C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.054, 82.273%; tC2Q: 0.442, 17.727%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.903, 100.000%

Path15

Path Summary:

Slack	2.168
Data Arrival Time	8.397
Data Required Time	10.565
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.397	2.054	tNET	FF	1	R20C19[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.913	0.913	tNET	RR	1	R20C19[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
10.565	-0.347	tSu		1	R20C19[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.054, 82.273%; tC2Q: 0.442, 17.727%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.913, 100.000%

Path16

Path Summary:

Slack	2.168
Data Arrival Time	8.397
Data Required Time	10.565
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.397	2.054	tNET	FF	1	R20C19[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.913	0.913	tNET	RR	1	R20C19[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
10.565	-0.347	tSu		1	R20C19[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.054, 82.273%; tC2Q: 0.442, 17.727%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.913, 100.000%

Path17

Path Summary:

Slack	2.177
Data Arrival Time	8.333
Data Required Time	10.510
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.333	1.990	tNET	FF	1	R17C21[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858	0.857	tNET	RR	1	R17C21[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.510	-0.347	tSu		1	R17C21[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.990, 81.809%; tC2Q: 0.442, 18.191%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path18

Path Summary:

Slack	2.177
Data Arrival Time	8.333
Data Required Time	10.510
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.333	1.990	tNET	FF	1	R17C21[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858	0.857	tNET	RR	1	R17C21[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
10.510	-0.347	tSu		1	R17C21[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.990, 81.809%; tC2Q: 0.442, 18.191%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path19

Path Summary:

Slack	2.177
Data Arrival Time	8.333
Data Required Time	10.510
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.333	1.990	tNET	FF	1	R17C21[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858	0.857	tNET	RR	1	R17C21[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
10.510	-0.347	tSu		1	R17C21[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.990, 81.809%; tC2Q: 0.442, 18.191%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path20

Path Summary:

Slack	2.177
Data Arrival Time	8.333
Data Required Time	10.510
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.333	1.990	tNET	FF	1	R17C21[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858	0.857	tNET	RR	1	R17C21[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
10.510	-0.347	tSu		1	R17C21[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.990, 81.809%; tC2Q: 0.442, 18.191%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path21

Path Summary:

Slack	2.177
Data Arrival Time	8.333
Data Required Time	10.510
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.333	1.990	tNET	FF	1	R17C21[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858	0.857	tNET	RR	1	R17C21[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
10.510	-0.347	tSu		1	R17C21[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.990, 81.809%; tC2Q: 0.442, 18.191%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.857, 100.000%

Path22

Path Summary:

Slack	2.181
Data Arrival Time	8.332
Data Required Time	10.513
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.332	1.989	tNET	FF	1	R13C19[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.861	0.861	tNET	RR	1	R13C19[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.513	-0.347	tSu		1	R13C19[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.040
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.989, 81.799%; tC2Q: 0.442, 18.201%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.861, 100.000%

Path23

Path Summary:

Slack	2.192
Data Arrival Time	8.316
Data Required Time	10.508
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.316	1.972	tNET	FF	1	R16C21[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.856	0.856	tNET	RR	1	R16C21[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
10.508	-0.347	tSu		1	R16C21[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.972, 81.677%; tC2Q: 0.442, 18.323%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.856, 100.000%

Path24

Path Summary:

Slack	2.192
Data Arrival Time	8.316
Data Required Time	10.508
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk100:[F]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk100
5.000	0.000	tCL	FF	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.901	0.901	tNET	FF	1	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.343	0.442	tC2Q	FF	55	R20C28[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.316	1.972	tNET	FF	1	R16C21[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.856	0.856	tNET	RR	1	R16C21[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
10.508	-0.347	tSu		1	R16C21[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.972, 81.677%; tC2Q: 0.442, 18.323%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.856, 100.000%

Path25

Path Summary:

Slack	4.617
Data Arrival Time	5.902
Data Required Time	10.519
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.842	0.842	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.224	0.382	tC2Q	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.362	0.137	tNET	RR	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.744	0.382	tINS	RF	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.902	4.158	tNET	FF	1	R35C82[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk100
10.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867	0.867	tNET	RR	1	R35C82[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/CLK
10.519	-0.347	tSu		1	R35C82[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew	0.025
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%
Arrival Data Path Delay	cell: 0.382, 7.559%; route: 4.295, 84.881%; tC2Q: 0.382, 7.559%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.867, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.610
Data Arrival Time	1.476
Data Required Time	0.866
From	rstni_s0
To	u_pll_mDRP_intf/c_s.OP_WR1_s4
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C60[0][B]	u_pll_mDRP_intf/c_s.OP_WR1_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.055	0.380	tNET	RR	1	R36C60[0][B]	u_pll_mDRP_intf/c_s.OP_WR1_s4/CLK
0.866	-0.189	tHld		1	R36C60[0][B]	u_pll_mDRP_intf/c_s.OP_WR1_s4

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.017%; route: 0.380, 35.983%

Path2

Path Summary:

Slack	0.610
Data Arrival Time	1.476
Data Required Time	0.866
From	rstni_s0
To	u_pll_mDRP_intf/c_s.OP_RD_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C60[2][A]	u_pll_mDRP_intf/c_s.OP_RD_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.055	0.380	tNET	RR	1	R36C60[2][A]	u_pll_mDRP_intf/c_s.OP_RD_s1/CLK
0.866	-0.189	tHld		1	R36C60[2][A]	u_pll_mDRP_intf/c_s.OP_RD_s1

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.017%; route: 0.380, 35.983%

Path3

Path Summary:

Slack	0.610
Data Arrival Time	1.476
Data Required Time	0.866
From	rstni_s0
To	u_pll_mDRP_intf/cnt_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C60[1][A]	u_pll_mDRP_intf/cnt_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.055	0.380	tNET	RR	1	R36C60[1][A]	u_pll_mDRP_intf/cnt_0_s0/CLK
0.866	-0.189	tHld		1	R36C60[1][A]	u_pll_mDRP_intf/cnt_0_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.017%; route: 0.380, 35.983%

Path4

Path Summary:

Slack	0.610
Data Arrival Time	1.476
Data Required Time	0.866
From	rstni_s0
To	u_pll_mDRP_intf/cnt_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C60[1][B]	u_pll_mDRP_intf/cnt_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.055	0.380	tNET	RR	1	R36C60[1][B]	u_pll_mDRP_intf/cnt_1_s0/CLK
0.866	-0.189	tHld		1	R36C60[1][B]	u_pll_mDRP_intf/cnt_1_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.017%; route: 0.380, 35.983%

Path5

Path Summary:

Slack	0.610
Data Arrival Time	1.476
Data Required Time	0.866
From	rstni_s0
To	u_pll_mDRP_intf/cnt_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C60[0][A]	u_pll_mDRP_intf/cnt_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.055	0.380	tNET	RR	1	R36C60[0][A]	u_pll_mDRP_intf/cnt_2_s0/CLK
0.866	-0.189	tHld		1	R36C60[0][A]	u_pll_mDRP_intf/cnt_2_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.017%; route: 0.380, 35.983%

Path6

Path Summary:

Slack	0.615
Data Arrival Time	1.476
Data Required Time	0.861
From	rstni_s0
To	u_pll_mDRP_intf/c_s.OP_WR_s5
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C59[0][B]	u_pll_mDRP_intf/c_s.OP_WR_s5/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.050	0.375	tNET	RR	1	R36C59[0][B]	u_pll_mDRP_intf/c_s.OP_WR_s5/CLK
0.861	-0.189	tHld		1	R36C59[0][B]	u_pll_mDRP_intf/c_s.OP_WR_s5

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path7

Path Summary:

Slack	0.615
Data Arrival Time	1.476
Data Required Time	0.861
From	rstni_s0
To	u_pll_mDRP_intf/c_s.IDLE_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C59[1][A]	u_pll_mDRP_intf/c_s.IDLE_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.050	0.375	tNET	RR	1	R36C59[1][A]	u_pll_mDRP_intf/c_s.IDLE_s0/CLK
0.861	-0.189	tHld		1	R36C59[1][A]	u_pll_mDRP_intf/c_s.IDLE_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path8

Path Summary:

Slack	0.615
Data Arrival Time	1.476
Data Required Time	0.861
From	rstni_s0
To	u_pll_mDRP_intf/pll_lock_r_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C59[2][A]	u_pll_mDRP_intf/pll_lock_r_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.050	0.375	tNET	RR	1	R36C59[2][A]	u_pll_mDRP_intf/pll_lock_r_s0/CLK
0.861	-0.189	tHld		1	R36C59[2][A]	u_pll_mDRP_intf/pll_lock_r_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path9

Path Summary:

Slack	0.615
Data Arrival Time	1.476
Data Required Time	0.861
From	rstni_s0
To	u_pll_mDRP_intf/c_s.WAIT_R_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.476	0.251	tNET	RR	1	R36C59[0][A]	u_pll_mDRP_intf/c_s.WAIT_R_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.050	0.375	tNET	RR	1	R36C59[0][A]	u_pll_mDRP_intf/c_s.WAIT_R_s0/CLK
0.861	-0.189	tHld		1	R36C59[0][A]	u_pll_mDRP_intf/c_s.WAIT_R_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path10

Path Summary:

Slack	0.734
Data Arrival Time	1.594
Data Required Time	0.860
From	pll_lock_rr_s0
To	wr_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C62[0][A]	pll_lock_rr_s0/CLK
1.225	0.180	tC2Q	RR	9	R36C62[0][A]	pll_lock_rr_s0/Q
1.594	0.369	tNET	RR	1	R35C59[0][A]	wr_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.049	0.373	tNET	RR	1	R35C59[0][A]	wr_s0/CLK
0.860	-0.189	tHld		1	R35C59[0][A]	wr_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.369, 67.198%; tC2Q: 0.180, 32.802%
Required Clock Path Delay	cell: 0.675, 64.418%; route: 0.373, 35.582%

Path11

Path Summary:

Slack	0.832
Data Arrival Time	1.696
Data Required Time	0.865
From	rstni_s0
To	u_pll_mDRP_intf/mdrp_wdata_7_s4
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.696	0.471	tNET	RR	1	R35C60[1][B]	u_pll_mDRP_intf/mdrp_wdata_7_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.054	0.378	tNET	RR	1	R35C60[1][B]	u_pll_mDRP_intf/mdrp_wdata_7_s4/CLK
0.865	-0.189	tHld		1	R35C60[1][B]	u_pll_mDRP_intf/mdrp_wdata_7_s4

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.471, 72.361%; tC2Q: 0.180, 27.639%
Required Clock Path Delay	cell: 0.675, 64.112%; route: 0.378, 35.888%

Path12

Path Summary:

Slack	0.832
Data Arrival Time	1.696
Data Required Time	0.865
From	rstni_s0
To	u_pll_mDRP_intf/mdrp_inc_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.696	0.471	tNET	RR	1	R35C60[0][A]	u_pll_mDRP_intf/mdrp_inc_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.054	0.378	tNET	RR	1	R35C60[0][A]	u_pll_mDRP_intf/mdrp_inc_s0/CLK
0.865	-0.189	tHld		1	R35C60[0][A]	u_pll_mDRP_intf/mdrp_inc_s0

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.471, 72.361%; tC2Q: 0.180, 27.639%
Required Clock Path Delay	cell: 0.675, 64.112%; route: 0.378, 35.888%

Path13

Path Summary:

Slack	0.832
Data Arrival Time	1.696
Data Required Time	0.865
From	rstni_s0
To	u_pll_mDRP_intf/mdrp_op_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.696	0.471	tNET	RR	1	R35C60[0][B]	u_pll_mDRP_intf/mdrp_op_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.054	0.378	tNET	RR	1	R35C60[0][B]	u_pll_mDRP_intf/mdrp_op_0_s0/CLK
0.865	-0.189	tHld		1	R35C60[0][B]	u_pll_mDRP_intf/mdrp_op_0_s0

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.471, 72.361%; tC2Q: 0.180, 27.639%
Required Clock Path Delay	cell: 0.675, 64.112%; route: 0.378, 35.888%

Path14

Path Summary:

Slack	0.832
Data Arrival Time	1.696
Data Required Time	0.865
From	rstni_s0
To	u_pll_mDRP_intf/mdrp_op_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.045	0.370	tNET	RR	1	R36C58[2][A]	rstni_s0/CLK
1.225	0.180	tC2Q	RR	21	R36C58[2][A]	rstni_s0/Q
1.696	0.471	tNET	RR	1	R35C60[1][A]	u_pll_mDRP_intf/mdrp_op_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	76	IOB29[A]	clk_ibuf/O
1.054	0.378	tNET	RR	1	R35C60[1][A]	u_pll_mDRP_intf/mdrp_op_1_s0/CLK
0.865	-0.189	tHld		1	R35C60[1][A]	u_pll_mDRP_intf/mdrp_op_1_s0

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.471, 72.361%; tC2Q: 0.180, 27.639%
Required Clock Path Delay	cell: 0.675, 64.112%; route: 0.378, 35.888%

Path15

Path Summary:

Slack	2.279
Data Arrival Time	2.446
Data Required Time	0.167
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C78[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356	0.356	tNET	RR	1	R13C78[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLK
0.167	-0.189	tHld		1	R13C78[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.356, 100.000%

Path16

Path Summary:

Slack	2.279
Data Arrival Time	2.446
Data Required Time	0.167
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C78[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356	0.356	tNET	RR	1	R13C78[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLK
0.167	-0.189	tHld		1	R13C78[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.356, 100.000%

Path17

Path Summary:

Slack	2.279
Data Arrival Time	2.446
Data Required Time	0.167
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C78[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356	0.356	tNET	RR	1	R13C78[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLK
0.167	-0.189	tHld		1	R13C78[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.356, 100.000%

Path18

Path Summary:

Slack	2.279
Data Arrival Time	2.446
Data Required Time	0.167
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C78[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356	0.356	tNET	RR	1	R13C78[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLK
0.167	-0.189	tHld		1	R13C78[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.356, 100.000%

Path19

Path Summary:

Slack	2.284
Data Arrival Time	2.446
Data Required Time	0.162
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C77[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C77[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK
0.162	-0.189	tHld		1	R13C77[1][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%

Path20

Path Summary:

Slack	2.284
Data Arrival Time	2.446
Data Required Time	0.162
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C77[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C77[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK
0.162	-0.189	tHld		1	R13C77[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%

Path21

Path Summary:

Slack	2.284
Data Arrival Time	2.446
Data Required Time	0.162
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C77[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C77[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLK
0.162	-0.189	tHld		1	R13C77[0][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%

Path22

Path Summary:

Slack	2.284
Data Arrival Time	2.446
Data Required Time	0.162
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C77[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C77[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLK
0.162	-0.189	tHld		1	R13C77[2][B]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%

Path23

Path Summary:

Slack	2.284
Data Arrival Time	2.446
Data Required Time	0.162
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C77[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C77[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLK
0.162	-0.189	tHld		1	R13C77[1][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%

Path24

Path Summary:

Slack	2.284
Data Arrival Time	2.446
Data Required Time	0.162
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.446	1.589	tNET	RR	1	R13C77[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C77[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLK
0.162	-0.189	tHld		1	R13C77[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 11.814%; route: 1.671, 79.773%; tC2Q: 0.176, 8.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%

Path25

Path Summary:

Slack	2.504
Data Arrival Time	2.681
Data Required Time	0.178
From	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0
Launch Clk	clk100:[R]
Latch Clk	clk100:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351	0.351	tNET	RR	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.528	0.176	tC2Q	RF	1	R13C45[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.610	0.082	tNET	FF	1	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.858	0.248	tINS	FR	80	R13C45[3][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.681	1.824	tNET	RR	1	R32C79[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk100
0.000	0.000	tCL	RR	6773	RIGHTSIDE[0]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.366	0.366	tNET	RR	1	R32C79[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0/CLK
0.178	-0.189	tHld		1	R32C79[0][A]	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew	0.015
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay	cell: 0.248, 10.622%; route: 1.906, 81.813%; tC2Q: 0.176, 7.564%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.366, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

MPW2

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA

MPW3

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s/CLKA

MPW4

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA

MPW5

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKB

MPW6

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA

MPW7

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	u_DDR2_TOP/gw2mc_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKB

MPW8

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA

MPW9

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s/CLKA

MPW10

MPW Summary:

Slack:	3.499
Actual Width:	4.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk100
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk100
5.000	0.000	tCL	FF	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875	0.875	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk100
10.000	0.000	tCL	RR	u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374	0.374	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
6773	u_DDR2_TOP_514	0.090	0.924
1243	control0[0]	2.215	2.315
538	n20_3	45.385	2.083
518	n3118_4	41.510	2.461
518	n3118_8	41.603	2.325
517	data_out_shift_reg_515_7	41.065	3.175
331	eye_calib_start_r	2.876	4.311
331	ddr_init_internal_rr	5.136	3.244
331	eye_calib_start_rr	6.155	3.087
300	n295_4	3.908	2.864

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R28C65	70.83%
R10C62	69.44%
R28C66	69.44%
R10C57	66.67%
R12C56	65.28%
R28C74	65.28%
R10C63	61.11%
R28C64	61.11%
R28C68	61.11%
R28C73	61.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK	Actived	create_clock -name clk100 -period 10 -waveform {0 5} [get_pins {u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT}]
TC_CLOCK	Actived	create_clock -name clkin -period 40 -waveform {0 20} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name mem_clk -period 2.5 -waveform {0 1.25} [get_pins {Gowin_PLL_inst/PLLA_inst/CLKOUT2}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk100}] -to [get_clocks {tck_pad_i}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {mem_clk}] -group [get_clocks {clk100}]