Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\src\ddr2_memory_interface\ddr2_memory_interface.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\src\ddr2_test.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\src\pll_mDRP_intf.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\src\top.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DDR2_Memory_Interface_RefDesign\DDR2_MC_PHY_1vs4_5a25k_new\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.02 |
| Part Number | GW5A-EV25UG324SES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Thu Mar 21 17:20:19 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 332.500MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 332.500MB Optimizing Phase 1: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.289s, Peak memory usage = 332.500MB Optimizing Phase 2: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.581s, Peak memory usage = 332.500MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 332.500MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 332.500MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 332.500MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 332.500MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.675s, Peak memory usage = 332.500MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.173s, Peak memory usage = 332.500MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 332.500MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 332.500MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 332.500MB Generate output files: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.802s, Peak memory usage = 353.563MB |
| Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 353.563MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 74 |
| I/O Buf | 68 |
| IBUF | 5 |
| OBUF | 22 |
| TBUF | 4 |
| IOBUF | 32 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 4 |
| Register | 7886 |
| DFFRE | 1017 |
| DFFPE | 99 |
| DFFCE | 6770 |
| LUT | 4820 |
| LUT2 | 1006 |
| LUT3 | 1796 |
| LUT4 | 2018 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 407 |
| ALU | 407 |
| INV | 31 |
| INV | 31 |
| IOLOGIC | 126 |
| IDES8_MEM | 32 |
| OSER8 | 22 |
| OSER8_MEM | 40 |
| IODELAY | 32 |
| BSRAM | 53 |
| SDPB | 8 |
| SDPX9B | 45 |
| CLOCK | 7 |
| CLKDIV | 1 |
| DQS | 4 |
| DDRDLL | 1 |
| PLLA | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5266(4859 LUT, 407 ALU) / 23040 | 23% |
| Register | 7886 / 23736 | 34% |
| --Register as Latch | 0 / 23736 | 0% |
| --Register as FF | 7886 / 23736 | 34% |
| BSRAM | 53 / 56 | 95% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.0 | 0.000 | 1.250 | clk_ibuf/I | clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 220.934(MHz) | 6 | TOP |
| 2 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1164.144(MHz) | 1 | TOP |
| 3 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 173.160(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -2.011 |
| Data Arrival Time | 12.605 |
| Data Required Time | 10.594 |
| From | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll |
| To | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 |
| Launch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.484 | 0.984 | tCL | RR | 100 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 8.859 | 0.375 | tNET | RR | 8 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/CLKIN |
| 9.265 | 0.406 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.640 | 0.375 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/I1 |
| 10.202 | 0.563 | tINS | RF | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/COUT |
| 10.202 | 0.000 | tNET | FF | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/CIN |
| 10.252 | 0.050 | tINS | FR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/COUT |
| 10.252 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/CIN |
| 10.302 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/COUT |
| 10.302 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/CIN |
| 10.352 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/COUT |
| 10.352 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/CIN |
| 10.403 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/COUT |
| 10.403 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/CIN |
| 10.453 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/COUT |
| 10.452 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/CIN |
| 10.502 | 0.050 | tINS | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/COUT |
| 10.877 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/I1 |
| 11.394 | 0.516 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/F |
| 11.769 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n226_s0/I2 |
| 12.230 | 0.461 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n226_s0/F |
| 12.605 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.318 | 0.317 | tCL | RR | 6773 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.693 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK |
| 10.658 | -0.035 | tUnc | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 | ||
| 10.594 | -0.064 | tSu | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 |
| Clock Skew: | -0.291 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 2.246, 54.501%; route: 1.500, 36.399%; tC2Q: 0.375, 9.100% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 2
Path Summary:| Slack | -2.011 |
| Data Arrival Time | 12.605 |
| Data Required Time | 10.594 |
| From | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll |
| To | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 |
| Launch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.484 | 0.984 | tCL | RR | 100 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 8.859 | 0.375 | tNET | RR | 8 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/CLKIN |
| 9.265 | 0.406 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.640 | 0.375 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/I1 |
| 10.202 | 0.563 | tINS | RF | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/COUT |
| 10.202 | 0.000 | tNET | FF | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/CIN |
| 10.252 | 0.050 | tINS | FR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/COUT |
| 10.252 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/CIN |
| 10.302 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/COUT |
| 10.302 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/CIN |
| 10.352 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/COUT |
| 10.352 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/CIN |
| 10.403 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/COUT |
| 10.403 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/CIN |
| 10.453 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/COUT |
| 10.452 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/CIN |
| 10.502 | 0.050 | tINS | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/COUT |
| 10.877 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/I1 |
| 11.394 | 0.516 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/F |
| 11.769 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n225_s0/I2 |
| 12.230 | 0.461 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n225_s0/F |
| 12.605 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.318 | 0.317 | tCL | RR | 6773 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.693 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK |
| 10.658 | -0.035 | tUnc | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 | ||
| 10.594 | -0.064 | tSu | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 |
| Clock Skew: | -0.291 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 2.246, 54.501%; route: 1.500, 36.399%; tC2Q: 0.375, 9.100% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 3
Path Summary:| Slack | -2.011 |
| Data Arrival Time | 12.605 |
| Data Required Time | 10.594 |
| From | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll |
| To | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0 |
| Launch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.484 | 0.984 | tCL | RR | 100 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 8.859 | 0.375 | tNET | RR | 8 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/CLKIN |
| 9.265 | 0.406 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.640 | 0.375 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/I1 |
| 10.202 | 0.563 | tINS | RF | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/COUT |
| 10.202 | 0.000 | tNET | FF | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/CIN |
| 10.252 | 0.050 | tINS | FR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/COUT |
| 10.252 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/CIN |
| 10.302 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/COUT |
| 10.302 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/CIN |
| 10.352 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/COUT |
| 10.352 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/CIN |
| 10.403 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/COUT |
| 10.403 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/CIN |
| 10.453 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/COUT |
| 10.452 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/CIN |
| 10.502 | 0.050 | tINS | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/COUT |
| 10.877 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/I1 |
| 11.394 | 0.516 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/F |
| 11.769 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n224_s0/I2 |
| 12.230 | 0.461 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n224_s0/F |
| 12.605 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.318 | 0.317 | tCL | RR | 6773 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.693 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK |
| 10.658 | -0.035 | tUnc | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0 | ||
| 10.594 | -0.064 | tSu | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0 |
| Clock Skew: | -0.291 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 2.246, 54.501%; route: 1.500, 36.399%; tC2Q: 0.375, 9.100% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 4
Path Summary:| Slack | -2.011 |
| Data Arrival Time | 12.605 |
| Data Required Time | 10.594 |
| From | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll |
| To | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0 |
| Launch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.484 | 0.984 | tCL | RR | 100 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 8.859 | 0.375 | tNET | RR | 8 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/CLKIN |
| 9.265 | 0.406 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.640 | 0.375 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/I1 |
| 10.202 | 0.563 | tINS | RF | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/COUT |
| 10.202 | 0.000 | tNET | FF | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/CIN |
| 10.252 | 0.050 | tINS | FR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/COUT |
| 10.252 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/CIN |
| 10.302 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/COUT |
| 10.302 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/CIN |
| 10.352 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/COUT |
| 10.352 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/CIN |
| 10.403 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/COUT |
| 10.403 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/CIN |
| 10.453 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/COUT |
| 10.452 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/CIN |
| 10.502 | 0.050 | tINS | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/COUT |
| 10.877 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/I1 |
| 11.394 | 0.516 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/F |
| 11.769 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n223_s0/I2 |
| 12.230 | 0.461 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n223_s0/F |
| 12.605 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.318 | 0.317 | tCL | RR | 6773 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.693 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK |
| 10.658 | -0.035 | tUnc | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0 | ||
| 10.594 | -0.064 | tSu | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0 |
| Clock Skew: | -0.291 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 2.246, 54.501%; route: 1.500, 36.399%; tC2Q: 0.375, 9.100% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 5
Path Summary:| Slack | -2.011 |
| Data Arrival Time | 12.605 |
| Data Required Time | 10.594 |
| From | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll |
| To | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0 |
| Launch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.484 | 0.984 | tCL | RR | 100 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
| 8.859 | 0.375 | tNET | RR | 8 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/CLKIN |
| 9.265 | 0.406 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.640 | 0.375 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/I1 |
| 10.202 | 0.563 | tINS | RF | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s16/COUT |
| 10.202 | 0.000 | tNET | FF | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/CIN |
| 10.252 | 0.050 | tINS | FR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s17/COUT |
| 10.252 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/CIN |
| 10.302 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s18/COUT |
| 10.302 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/CIN |
| 10.352 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s19/COUT |
| 10.352 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/CIN |
| 10.403 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s20/COUT |
| 10.403 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/CIN |
| 10.453 | 0.050 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s21/COUT |
| 10.452 | 0.000 | tNET | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/CIN |
| 10.502 | 0.050 | tINS | RR | 2 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n184_s22/COUT |
| 10.877 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/I1 |
| 11.394 | 0.516 | tINS | RR | 9 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n256_s1/F |
| 11.769 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n222_s0/I2 |
| 12.230 | 0.461 | tINS | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/n222_s0/F |
| 12.605 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.318 | 0.317 | tCL | RR | 6773 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.693 | 0.375 | tNET | RR | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK |
| 10.658 | -0.035 | tUnc | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0 | ||
| 10.594 | -0.064 | tSu | 1 | u_DDR2_TOP/gw2mc_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0 |
| Clock Skew: | -0.291 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 2.246, 54.501%; route: 1.500, 36.399%; tC2Q: 0.375, 9.100% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |