Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDR2\data\ddr_code.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDR2\data\DDR2_TOP.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55C
Created Time Wed Jun 29 11:54:53 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DDR2_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.998s, Elapsed time = 0h 0m 1s, Peak memory usage = 56.945MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 56.945MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 56.945MB
    Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.137s, Peak memory usage = 56.945MB
    Optimizing Phase 2: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.412s, Peak memory usage = 56.945MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.202s, Elapsed time = 0h 0m 0.215s, Peak memory usage = 56.945MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 56.945MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 56.945MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 56.945MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.249s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 56.945MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.343s, Peak memory usage = 56.945MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 56.945MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 72.887MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.374s, Elapsed time = 0h 0m 0.388s, Peak memory usage = 72.887MB
Generate output files:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.175s, Peak memory usage = 72.887MB
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 72.887MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 234
I/O Buf 229
    IBUF 111
    OBUF 97
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 1367
    DFF 163
    DFFE 146
    DFFSE 26
    DFFR 2
    DFFRE 46
    DFFP 54
    DFFPE 4
    DFFC 647
    DFFCE 279
LUT 1223
    LUT2 311
    LUT3 334
    LUT4 578
ALU 94
    ALU 94
SSRAM 80
    RAM16S4 7
    RAM16SDP4 73
INV 20
    INV 20
IOLOGIC 100
    ODDR 23
    IDES4_MEM 16
    OSER4 1
    OSER4_MEM 20
    IODELAY 40
CLOCK 4
    CLKDIV 1
    DQS 2
    DQCE 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1817(1243 LUTs, 94 ALUs, 80 SSRAMs) / 54720 3%
Register 1367 / 41997 3%
  --Register as Latch 0 / 41997 0%
  --Register as FF 1367 / 41997 3%
BSRAM 0 / 140 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 memory_clk 100.0(MHz) 1364.3(MHz) 1 TOP
2 clk 100.0(MHz) 241.5(MHz) 6 TOP
3 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 50.0(MHz) 149.3(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.186
Data Arrival Time 4.639
Data Required Time 5.826
From gw2mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_0_s0
To gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.170 0.170 tCL RR 1472 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.350 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_0_s0/CLK
0.582 0.232 tC2Q RF 11 gw2mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_0_s0/Q
0.819 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s19/I1
1.375 0.555 tINS FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s19/F
1.612 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/I1
2.167 0.555 tINS FF 4 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/F
2.404 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/I0
2.921 0.517 tINS FF 7 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/F
3.158 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/I2
3.611 0.453 tINS FF 3 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/F
3.848 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s0/I1
4.403 0.555 tINS FF 2 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s0/F
4.640 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 1 memory_clk_ibuf/O
5.924 0.237 tNET FF 3 gw2mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKIN
6.110 0.186 tINS FF 41 gw2mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT
6.347 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.313 -0.035 tUnc gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.826 -0.487 tSu 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.997
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 2.635, 61.436%; route: 1.422, 33.155%; tC2Q: 0.232, 5.409%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack 1.186
Data Arrival Time 4.639
Data Required Time 5.826
From gw2mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_0_s0
To gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.170 0.170 tCL RR 1472 gw2mc_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.350 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_0_s0/CLK
0.582 0.232 tC2Q RF 11 gw2mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_0_s0/Q
0.819 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s19/I1
1.375 0.555 tINS FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s19/F
1.612 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/I1
2.167 0.555 tINS FF 4 gw2mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/F
2.404 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/I0
2.921 0.517 tINS FF 7 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_SEND_DQS_s15/F
3.158 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/I2
3.611 0.453 tINS FF 3 gw2mc_top/u_ddr_phy_top/u_ddr_init/wrlvl_next_state.WRLVL_ADJ_DQS_s20/F
3.848 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s0/I1
4.403 0.555 tINS FF 2 gw2mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s0/F
4.640 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 1 memory_clk_ibuf/O
5.924 0.237 tNET FF 3 gw2mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKIN
6.110 0.186 tINS FF 41 gw2mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT
6.347 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.313 -0.035 tUnc gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.826 -0.487 tSu 1 gw2mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.997
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 2.635, 61.436%; route: 1.422, 33.155%; tC2Q: 0.232, 5.409%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 3

Path Summary:
Slack 5.860
Data Arrival Time 4.968
Data Required Time 10.828
From gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0
To gw2mc_top/u_ddr_phy_top/ddr_sync/flag_1_s2
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 38 clk_ibuf/O
0.863 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0/CLK
1.095 0.232 tC2Q RF 11 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0/Q
1.332 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s13/I1
1.887 0.555 tINS FF 2 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s13/F
2.124 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/I3
2.495 0.371 tINS FF 4 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/F
2.732 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s12/I1
3.287 0.555 tINS FF 3 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s12/F
3.524 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/I2
3.977 0.453 tINS FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/F
4.214 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s11/I0
4.731 0.517 tINS FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s11/F
4.968 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_1_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 38 clk_ibuf/O
10.863 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_1_s2/CLK
10.828 -0.035 tSu 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_1_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.451, 59.707%; route: 1.422, 34.641%; tC2Q: 0.232, 5.652%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.904
Data Arrival Time 4.924
Data Required Time 10.828
From gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0
To gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 38 clk_ibuf/O
0.863 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0/CLK
1.095 0.232 tC2Q RF 11 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0/Q
1.332 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s13/I1
1.887 0.555 tINS FF 2 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s13/F
2.124 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/I3
2.495 0.371 tINS FF 4 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/F
2.732 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/I1
3.287 0.555 tINS FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/F
3.524 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s13/I1
4.079 0.555 tINS FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s13/F
4.316 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s12/I3
4.687 0.371 tINS FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s12/F
4.924 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 38 clk_ibuf/O
10.863 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/CLK
10.828 -0.035 tSu 1 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.407, 59.271%; route: 1.422, 35.016%; tC2Q: 0.232, 5.713%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.550
Data Arrival Time 4.278
Data Required Time 10.828
From gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0
To gw2mc_top/u_ddr_phy_top/ddr_sync/flag_0_s4
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 38 clk_ibuf/O
0.863 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0/CLK
1.095 0.232 tC2Q RF 11 gw2mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_1_s0/Q
1.332 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s13/I1
1.887 0.555 tINS FF 2 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_1_s13/F
2.124 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/I3
2.495 0.371 tINS FF 4 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/F
2.732 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s12/I1
3.287 0.555 tINS FF 3 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s12/F
3.524 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s11/I0
4.041 0.517 tINS FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s11/F
4.278 0.237 tNET FF 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_0_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 38 clk_ibuf/O
10.863 0.180 tNET RR 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLK
10.828 -0.035 tSu 1 gw2mc_top/u_ddr_phy_top/ddr_sync/flag_0_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.998, 58.506%; route: 1.185, 34.700%; tC2Q: 0.232, 6.794%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%