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	  Example DDR2 Design Read Me
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Object device:GW2A-55-PBGA484
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File List:
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.
|-- doc
|   `-- Readme.txt                              -->  Read Me file (this file)
|-- tb 
|   `-- tb.v                                    -->  TestBench for Example DDR2 design
|   `-- prim_sim.v                              -->  TestBench for Example DDR2 design
|   |-- sim_model                               -->  DDR2 model for simulation(please contact to FAE to get)
|-- project
|   `-- DDR2_MC_PHY_1vs2_Basic_Option.gprj      -->  Gowin Project File for Example Design
|   `-- DDR2_MC_PHY_1vs2_Basic_Option.gprj.user -->  Gowin Project File for Example Design
|   |-- impl
|   |   `-- project_process_config.json
|   |-- temp  
|   |-- src                          
|       `-- ddr2_syn_top.v                      -->  File for Gowin Project
|       `-- ddr2.cst                            -->  File for Gowin Project
|       `-- ddr2.sdc                            -->  File for Gowin Project
|       `-- DDR2_MC_PHY_1vs2_Basic_Option.rao   -->  File for Gowin Project
|       `-- DDR2_test.v                         -->  File for Gowin Project
|       |-- ddr2_memory_interface          
|       |   `-- ddr2_memory_interface.v         -->  File for Gowin Project(Encrypted)
|       |   `-- ddr2_memory_interface.vo        -->  File for Gowin Project
|       |   `-- ddr2_memory_interface.ipc       -->  File for Gowin Project
|       |   `-- ddr2_memory_interface_tmp.v     -->  File for Gowin Project
|       |   |-- temp   
|       |-- gowin_rpll          
|           `-- gowin_rpll.v                    -->  File for Gowin Project(Encrypted)
|           `-- gowin_rpll.mod                  -->  File for Gowin Project
|           `-- gowin_rpll.ipc                  -->  File for Gowin Project
|           `-- gowin_rpll_tmp.v                -->  File for Gowin Project                         
|-- simulation                                  -->  Simulation File
|   |-- modelsim_sim
|   |   `-- readme.txt                          -->  Read Me file for modelsim simulation
|   |   `-- tb.do                               -->  File for Simulation run command
|   |-- vcs_sim
|       `-- readme.txt                          -->  Read Me file for modelsim simulation
|       `-- makefile                            -->  File for Simulation run command

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HOW TO OPEN A PROJECT IN GOWIN FPGA Designer:
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1. Unzip the respective design files.
2. Launch GOWIN FPGA Designer and select "File -> Open -> Project"
3. In the Open Project dialog, enter the Project location -- "project",select the project"DDR2_MC_PHY_1vs2_Basic_Option.gprj".
4. Click Finish. Now the project is successfully loaded. 

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HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATION, AND TIMING ANALYSIS IN GOWIN FPGA Designer:
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1. Click the Process tab in the process panel of the GOWIN FPGA Designer dashboard. 
   Double click on Synthsize(Synplify Pro). This will bring the design through synthesis.
2. Click the Process tab in the process panel of the GOWIN FPGA Designer dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.
4. Click on "Project -> Configuration -> Place & Route" to configurate the Post-Place File 
   and SDF File of the design.
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HOW TO RUN SIMULATION
1. User can run functional simulation by software VCS. 
2. User can check waveform by software Verdi.
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HOW TO  GENERATE IP CORE
1. Click the IP Core Generator tab in the Window panel of the GOWIN FPGA Designer dashboard.
   Double click on "DDR2 Memory Interface". This will generate the IP Core for the design.
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