The GW3A family introduces a hybrid LUT4/LUT6 compute fabric designed for efficient logic packing, higher utilisation, and improved critical path performance. Its architecture integrates application‑specific hard blocks, including high‑precision DSP slices, multi‑tier SRAM (BSRAM/SSRAM), multi‑channel ADC options, MIPI D‑PHY/DSC engines, eDP interfaces, and high‑speed LVDS connectivity—giving designers deterministic acceleration for signal processing, control loops, imaging pipelines, and video transport.

Spanning 6K to 90K logic elements, GW3A devices deliver predictable timing closure with tightly coupled PLLs, streamlined I/O banks, and protocol‑aware subsystems. The result is a compact, mid‑range FPGA platform engineered for real‑time industrial control, machine vision, embedded display processing, and low‑latency bridging, where architectural efficiency, subsystem integration, and reliable throughput are mission‑critical.

Arora 3 FPGA Product Features

Lower Power Architecture

• LV versions support 0.9 V / 1.0 V core voltage.
• Integrated dynamic clock gating enables fine‑grain power reduction.

Flexible Multi‑LUT Fabric

• The compiler auto‑optimises LUT4/LUT5/LUT6 usage for area and performance.
• Real 5-input look-up tables
• Real 6-input look-up tables
• Includes shadow SRAMs for advanced logic mapping.

Advanced Memory Architecture

• Multi‑mode Block SRAM:
• Dual‑Port, Single‑Port, Semi‑Dual, and ROM configurations
• Byte‑write enable support
• Suited for packet buffers, frame data, and DSP coefficient storage.

High‑Performance DSP System (Latest Architecture)

• Optimised for wide‑word multiplication and accumulation
• Supported multiplier sizes:
• 12×12, 18×18, 25×13, 27×18, 27×36
• 48‑bit accumulator
• Multiplier cascading for wide‑precision filters
• Supports:
• Multiply‑add
• Two‑ and three‑input accumulation
• 48+48‑bit addition

Ideal for motor control, digital filters, predictive control loops, and edge analytics.

Flexible Oversampling ADC System

• New multi‑channel oversampling ADC with high‑accuracy—no external reference required
• Integrated 13‑bit SAR ADC for high‑speed sampling
• Enables mixed‑signal processing directly on‑chip

Hardened System‑Level Accelerators (Device/Package dependant)

Integrated hardware modules:

• UBM (Universal Bit Mapping)
• GMT (Matrix Transpose)
• RNG (Random Number Generator)

Supports imaging, AI, crypto, and matrix operations.

High‑Speed External Memory Interfaces

• Multi‑mode SDRAM support
• SSTL15 up to 1333 Mbps
• DDR/DDR2/DDR3

I/O Features & Electrical Options

• Wide I/O standard support
• Hysteresis option for inputs
• Drive strengths from 2 mA to 16 mA
• Per‑pin:
• Bus keeper
• Pull‑up / Pull‑down
• Open‑drain
• Hot Socket support for live‑insertion systems

Clocking

• 16 global clocks
• 16 high‑speed clock nets
• 4 high‑performance PLLs
• Plus, external 24–50 MHz crystal support

mDRP (Mini Dynamic Re‑Program Port)

Enables runtime reconfiguration of:

• HCLK
• PLL
• ADC
• OSC

Perfect for adaptive systems or multi‑mode protocols.

Configuration & Security (Package Dependant)

• JTAG, AutoBoot, SSPI, MSPI, Master/Slave CPU, Master/Slave Serial
• SPI Flash programming via JTAG, SSPI, or soft‑IP in other modes
• Background upgrade supported
• Bitstream encryption, security bits, and CMSER
• Multi‑boot for safe firmware rollbacks