GW1N Series Table

Package Options, Available User I/O, (and LVDS Pairs):

GW1N-1GW1N-1S

GW1N-1S

注記：

• JTAGSEL_NとJTAGピンは、相互に排他的なピンで、JTAGSEL_NピンとJTAG機能の4ピン(TCK、TDI、TDO、TMS)を同時にI/Oとして使用することはできません。ただし、mode[2:0]=001の場合、JTAGSEL_Nピンが常にGPIOであり、JTAGSEL_NピンとJTAGの4ピン(TCK、TMS、TDI、TDO)を同時にGPIOとして使用できます。詳細については、『GW1NシリーズFPGA製品パッケージ及びピンアウト ユーザーガイド(UG103)』を参照してください。
• GW1N-1 CS30はSSPIモードのみをサポートします。
• GW1N-2デバイスの場合、MODE[2]の値が1に固定されている場合、その読み込み周波数は2.5MHzのみになります。
• GW1N-4/GW1N-9 UVバージョンのデバイスでは、VccとVccxがパッケージのピンを共有している場合、GW1N-4/GW1N-9のVccx範囲 (2.5V~3.3V)によってVcc範囲が2.5 V~ 3.3Vに制限されます。この場合、Vccは1.8Vをサポートしていません。
   

   

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

製品情報一覧

各パッケージの最大ユーザーI/O数(True LVDSのペア数):

注記：

JTAGSEL_NとJTAGピンは、相互に排他的なピンで、JTAGSEL_NピンとJTAG機能の4ピン(TCK、TDI、TDO、TMS)を同時にGPIOとして使用することはできません。ただし、mode[2:0]=001の場合、JTAGSEL_Nピンが常にGPIOであり、JTAGSEL_NピンとJTAGの4ピン(TCK、TMS、TDI、TDO)を同時にGPIOとして使用できます。

メモリの容量と幅の一覧

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

The GW1NR embedded pSRAM memory products allow for more efficiency with onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

Features:

• Embedded 64 Mb pSRAM
• Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
• Small package sizes
• Low power consumption
• Dual Boot FPGA
• Remote upgradeable bitstream

GW1NS Series Table

Package Options, Availible User I/O, (and LVDS Pairs):

The GW1NS FPGA SoC device inherits the innovation of LittleBee™ family with embedded ARM Cortex-M3 hardcore processor, user flash, SRAM read/write controller providing customers all-in-one embedded solution with programable logic features in one chip. With Gowin integrated development environment, engineers can develop their hardware and software in a single platform, which is another innovation of FPGA design platform and reduces engineering design cycle.

Embedded 32-bit RISC Microprocessor

• Arm Cortex-M3 (80 MHz)
• 32KB User Flash

Flash Configuration

• Supports 2 image files
• Supports Dual Boot
• Online Upgradeable
• Remote Upgrade

Integrated Development Flow for both M3 Core and FPGA Programming

• Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

Fixed MIPI D-PHY I/O

• I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution

GW1NSR Version includes:

• 32M-bits of embedded pSRAM memory
• 8-bit wide, 332Mbps data rates (166 MHz clock)

Real-Time Operating Systems Supported

• uCOSIII
• FreeRTOS

GW1NS Video Training

Click Here

GW1NSE Secure FPGA Table

Package Options, Availible User I/O, (and LVDS Pairs):

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

GW1NSE SecureFPGA products provide a Root of Trust based on SRAM PUF technology. Each device is factory provisioned with a unique key pair that is never exposed outside of the device.  This widely applicable feature can be used for a variety of consumer and industrial IoT, edge and server management applications.

GW1NRF Series Table

Package Options, Availible User I/O, (and LVDS Pairs):

The GW1NRF Bluetooth FPGA product features FPGA fabric, a power optimized 32-bit microprocessor, a power management unit capable of power as low as 5nA and a Bluetooth 5.0 Low Energy radio.  This extends the capabilities of Bluetooth devices by adding the flexible IO and heterogenous computing capabilities of the FPGA.

The GW1NRF BLE Module contains the GW1NRF-4 µSoC FPGA, radio antenna and appropriate passives.

Features

• Integrated Bluetooth 5.0 Low Energy Radio
• 4k LUT FPGA
• 32-bit Power Optimized ARC Processor 

- 136kB ROM

- 128kB OTP for power efficiency

- 48kB IRAM and 28kB DRAM

• Power Management Unit

-    5nA Chip Disable¹ 

-  < 1uA Sleep and Deep Disable1

-  < 5mA Processor + FPGA Active

• Built-in DCDC Step Up/Down Regulator for Battery Operation
• Hardened Security

- TRNG

- AES-128 Encryption Engine

• ECC-P256 Key Generator
• Module - International RF certifications available

Note!

• [1]Does not include any leakage from external regulators when placed in standby

GW1NZ製品情報リスト

各パッケージの最大ユーザーI/O数、True LVDSのペア数:

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

注記：

• パッケージタイプを表すために略語が使用されています。
• JTAGSEL_NとJTAGピンは、相互に排他的なピンで、JTAGSEL_NピンとJTAG機能の4ピン(TCK、TDI、TDO、TMS)を同時にI/Oとして使用することはできません。ただし、mode[2:0]=001の場合、JTAGSEL_Nピンが常にGPIOであり、JTAGSEL_NピンとJTAGの4ピン(TCK、TMS、TDI、TDO)を同時にGPIOとして使用できます。

Product Resources

Package Options, Availible User I/O, (and LVDS Pairs):

注記：

• JTAGSEL_NとJTAGピンは、相互に排他的なピンで、JTAGSEL_NピンとJTAG機能の4ピン(TCK、TDI、TDO、TMS)を同時にI/Oとして使用することはできません。この表の数字は、JTAG機能の4ピンをI/Oとして使用した場合のものです。ただし、mode[2:0]=001の場合、JTAGSEL_NピンとJTAGの4ピン(TCK、TMS、TDI、TDO)を同時にGPIOとして設定できます。この場合、最大ユーザーI/O数が1増加します。詳細については、GW1NシリーズFPGA製品パッケージ及びピンアウト ユーザーガイド(UG103)を参照して下さい。

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

GOWIN Semiconductor has been manufacturing automotive grade FPGA since early 2018. Providing fully certified AEC-Q100 Level-2 non-volatile Flash-based and SRAM FPGA devices that support a wide range of interface standards including MIPI-DPHY and LVDS.

GW1NSR Series Table

Package Options, Availible User I/O, (and LVDS Pairs):

Package Identifier Definition Table

Feature identifier table denotes additional device capabilities outside of the traditional FPGA options

The GW1NSR series of FPGA products are the first generation products in the LittleBee® family and represent one form of SIP chip.The main difference between the GW1NS series and the GW1NSR series is that the GW1NSR series integrates abundant PSRAM.