更新中

GOWINは、2018年初頭からオートモーティブグレードのFPGAを製造し始め、MIPI-DPHYやLVDSなどの幅広いインターフェース規格をサポートする完全に認定されたAEC-Q100グレード2対応不揮発性FlashベースのFPGAおよびSRAM FPGAデバイスを提供します。

デバイス
GOWINのAEC-Q100オートモーティブ認定済みデバイスは、ADAS、360度のサラウンド ビュー、インフォテインメントシステム、LCDダッシュボードアプリケーション、およびシステム制御, 監視, 管理アプリケーション用のカメラセンサーとディスプレイのインターフェースとブリッジングに最適です。

IP

GOWINは、無料のFPGA EDAソフトウェアで提供されるIP Core Generatorを使用して簡単に入手できる、ライセンス無料の幅広いリファレンスデザインとIPコアを提供します。

ソリューション

10を超える完全なソリューションが開発されており、その多くは多くの大手自動車会社での車両搭載テストに合格しています。

GW2Aシリーズ

パッケージオプションと最大I / O（*詳細は最新のデータシートを参照してください）

GW2AN Family
The GW2AN series of FPGA products are the first generation non-volatile FPGA products of the Arora family. They offer a range of comprehensive features and rich internal resources, a high-speed LVDS interface, abundant BSRAM memory resources, and NOR Flash resources.

These embedded resources combine a streamlined FPGA architecture with a 55nm process to make the GW2AN series of FPGA products suitable for high-speed, low-cost applications. GOWIN continually invests the development of next-generation FPGA hardware environment through the market-oriented independent research and developments that supports the GW2AN series of FPGA products, which can be used for FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.

2.1    Features

• Lower power consumption
  • 55nm technology
  • EV version: Supports 1.0V core voltage;
  • LV version: Supports 1.2 V core voltage;
  • UV version: Supports5V and 3.3 V core voltage;
  • Clock dynamically turns on and off
• Multiple I/O standards
  • LVCMOS33/25/18/15/12;LVTTL33,SSTL33/25/18 I, II, SSTL15; HSTL18 I, II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE MLVDSE, LVPECLE, RSDSE
  • Input hysteresis option
  • Supports 4mA,8mA,16mA,24mA,etc. drive options
  • Slew rate option
  • Output drive strength option
  • Individual bus keeper, weak pull-up, weak pull-down, and open drain option

• • Hot socket

• Abundant slices
  • Four input LUT (LUT4)
  • Double-edge flip-flops
  • Supports shift register and distributed register
• Integrate NOR Flash
• Block SRAM with multiple modes
  • Supports dual port, single port, and semi-dual port
  • Supports byte write enable
• Flexible PLLs
  • Frequency adjustment (multiply and division) and phase adjustment
  • Supports global clock
• Configuration
  • Supoprts JTAG configuration
  • Five GowinCONFIG configuration modes: SSPI, Autoboot, CPU, I²C, SERIAL
  • Supoprts I²C and SSPI background programing
  • Supports JTAG and SSPI programming SPI Flash directly and other modes programming SPI Flash via IP
  • Data stream file encryption and security bit settings

GW2AN Family Table

Package Options and Max I/O (* Refer to the latest datasheet for details)

Note!

• The package types in this data sheet are written with abbreviations. See 1Part Name for further information.
• JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. For further detailed information, pelase refer toUG973, GW2AN series of FPGA Products Package and Pinout .

GW2AN-55 is the first generation products of the Arora family. They offer a range of comprehensive features and rich internal resources like high-performance DSP resources, a high-speed LVDS interface, and abundant BSRAM memory resources. These embedded resources combine a streamlined FPGA architecture with a 55nm process to make GW2AN-55 suitable for high-speed, low-cost applications.

GOWINSEMI continually invests the development of next-generation FPGA hardware environment through the market-oriented independent research and developments that supports GW2AN-55, which can be used for FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.

Features

• Lower power consumption
  • 55nm SRAM technology
  • Core voltage: 0V
  • Clock dynamically turns on and off
• Multiple I/O standards
  • LVCMOS33/25/18/15/12;LVTTL33,SSTL33/25/18 I, II, SSTL15;
  • HSTL18 I, II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
  • MLVDSE, LVPECLE, RSDSE
  • Input hysteresis option
  • Supports 4mA,8mA,16mA,24mA,etc. drive options
  • Slew rate option
  • Output drive strength option
  • Individual bus keeper, weak pull-up, weak pull-down, and open drain option
  • Hot socket

• Integrates NOR FLASH
• High performance DSP
  • High performance digital signal processing ability
  • Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator;
  • Multipliers cascading
  • Registers pipeline and bypass

• • Adaptive filtering through signal feedback
  • Supports barrel shifter

• Abundant slices
  • Four input LUT (LUT4)
  • Double-edge flip-flops
  • Supports shift register and distributed register
• Block SRAM with multiple modes
  • Supports dual port, single port, and semi-dual port
  • Supports bytes write enable
• Flexible PLLs
  • Frequency adjustment (multiply and division) and phase adjustment
  • Supports global clock
• Configuration
  • JTAG configuration
  • Four GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT
  • Supports JTAG and SSPI programming SPI Flash directly and other modes programming SPI Flash via IP
  • Data stream file encryption and security bit settings

Product Resources

Package Options and Max I/O (* Refer to the latest datasheet for details)

Note!

• The package types in this data sheet are written with abbreviations. See 1Part Name for further information.
• JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by For further detailed information, please refer to UG975, GW2AN-55 Package and Pinout Guide.

GW2ANRシリーズ

パッケージオプションと最大I / O（*詳細は最新のデータシートを参照してください）

 GW2ANR-18

GW2ARシリーズ

注記：

(1) ”P”はPSRAMを示します。 ”F”はセカンダリ・ピンアウトを示します。

パッケージオプションと最大I / O（*詳細は最新のデータシートを参照してください）

 GW2AR-18