Solving TDC Challenges with GOWIN FPGAs: Accurate, Scalable, and Cost-Effective Timing Solutions   1 Abstract   As time-domain applications continue to grow across sectors like 3D sensing, quantum optics, medical imaging, and LiDAR, the demand for high-resolution, scalable, and reliable Time-to-Digital Converter (TDC) solutions has surged. While FPGAs are a popular platform for TDC implementation, traditional approaches often suffer from inconsistent delay lines, environmental sensitivity, and limited channel scalability. This white paper introduces GOWIN Semiconductor’s innovative TDC architecture that leverages dedicated delay lines embedded in FPGA IO blocks. By circumventing the limitations of general-purpose logic fabric, GOWIN FPGAs offer superior timing precision, enhanced thermal and voltage stability, and support for high-density, multi-channel designs. The paper also explores real-world applications, including 3D Time-of-Flight cameras, digital oscilloscopes, and quantum photon counting systems, and demonstrates how GOWIN’s solution reduces cost and power while improving performance. Additionally, the paper presents a unique case study of a DIY Time-Based ADC, showcasing how GOWIN FPGAs enable creative, low-cost, high-resolution signal digitization. For engineers seeking accurate, efficient, and scalable TDC implementation, GOWIN’s FPGA-based solution sets a new standard in time-domain signal processing. 2 Introduction to TOF and TDC technology    Time-of-Flight (ToF)   In the age of smart devices, autonomous systems, and immersive reality, the ability to perceive depth with speed and precision has become essential. At the heart of many advanced sensing solutions lies Time-of-Flight (ToF) technology—an optical distance measurement technique that is revolutionizing fields from mobile photography to robotics and industrial automation. Time-of-Flight is a method for measuring distance by calculating the time it takes for a signal—typically a light pulse or modulated wave—to travel from a source to a target and back. By capturing this "flight time," the system can determine the exact distance to an object. The fundamental principle is simple, but its implementation relies on cutting-edge optoelectronics and timing technologies. A typical ToF system consists of: Light Source: Often a VCSEL (Vertical-Cavity Surface-Emitting Laser) that emits near-infrared light. Sensor: Usually a SPAD (Single-Photon Avalanche Diode) or CMOS sensor that detects returning photons.   Timing Circuitry: Includes a Time-to-Digital Converter (TDC) that measures the time delay with extreme precision. Concept of ToF from Wikipedia   There are two main types of ToF systems. One is Direct ToF (dToF). It measures the actual time delay between the emitted and received pulse. The other one is Indirect ToF (iToF). It measures the phase shift of a modulated light signal to estimate distance.   There are several Key Advantages of ToF. Real-time 3D Mapping: Generates depth maps at video frame rates. Compact & Low Power: Especially iToF, which is ideal for smartphones and AR glasses. High Accuracy & Range: Direct ToF can achieve centimeter to millimeter-level accuracy even over long distances. Versatile Integration: Easily embedded in consumer, automotive, and industrial systems.   As technology continues to evolve, ToF sensors are becoming smaller, faster, and more accurate. Future innovations will likely combine ToF with AI, edge computing, and multi-modal sensing (e.g., combining ToF with RGB or thermal imaging) to enable smarter, context-aware devices.   Time-to-Digital Converter (TDC)   A Time-to-Digital Converter (TDC) is an electronic circuit that measures the time interval between two events and converts it into a digital number. Unlike traditional ADCs (Analog-to-Digital Converters) that digitize voltage levels, TDCs focus on timing precision, offering exceptional performance for time-domain applications.   TDCs are essential in: Time-of-Flight (ToF) systems Particle detectors Optical communication LiDAR and 3D imaging Medical scanners (PET, CT) High-resolution oscilloscopes   TDCs measure the time between a start and stop signal. Depending on the architecture, they can achieve resolutions from nanoseconds down to tens of picoseconds or even lower.   Common Architectures: Delay Line TDC: Uses a chain of logic gates or buffers with known delay. Captures which stage the signal reaches when stopped. Simple and fast, but limited in resolution and sensitive to process/temperature. Vernier TDC: Uses two delay lines with slightly different delays. The difference is used to interpolate timing more precisely. Higher resolution but more complex. Ring Oscillator or Counter-based TDC: Measures coarse time with a counter and fine time with a delay chain. Offers a wide dynamic range and scalable performance. Time Interleaving or Multi-phase Clock: Improves throughput by parallelizing the measurement process. Ideal for high-frequency, high-event-rate applications.     Schematic of TDC based on Vernier Deley Line   Many TDCs are implemented on-chip FPGA or ASIC for flexibility and reduced cost.   3 Implementing TDC in FPGA   Why Use FPGAs for TDC? FPGAs (Field-Programmable Gate Arrays) are ideal for implementing TDCs due to: High-speed internal logic and fine-grained delay elements Parallelism for multi-channel timing Customizability for application-specific requirements Lower cost and faster prototyping compared to ASICs FPGAs enable rapid development of TDCs for applications such as: Time-of-Flight sensors (e.g., LiDAR) Scientific instrumentation (e.g., photon timing, nuclear detectors) Communication systems (e.g., jitter measurement, time synchronization) Common TDC Implementation Techniques in FPGA Tapped Delay Line (TDL) with LUTs and Carry Chains Uses the FPGA’s carry-chain logic as a fine-grained delay line. A signal propagates through the chain; a fast sampling flip-flop array captures the position of the rising edge. The pattern of flip-flop outputs gives a “thermometer code” that’s translated to fine time.  Pros: Simple, high resolution (20–50 ps typically)             Cons: Sensitive to temperature, voltage, and placement variability Vernier Delay Line (VDL) Uses two delay chains with slightly different delays to create a “beat frequency” and interpolate time. Often implemented with carefully tuned LUTs or logic blocks. Pros: Higher resolution than TDL (sub-10 ps achievable) Cons: More complex, calibration-intensive Multiphase Clocking Leverages a PLL to generate multiple clock phases. Uses these clocks to sample the timing signal more finely than the system clock. Pros: Easy to implement, deterministic  Cons: Limited number of phases, coarse resolution (unless combined with other techniques)   One Example of Carry Chain based TDC   Limitations of FPGA-based TDC   Challenge Description Non-uniform delays Delay lines vary due to routing, logic placement, process variation Temperature/voltage drift Delay elements are sensitive to environmental changes Metastability Occurs when sampling fast-changing signals asynchronously Jitter Internal and external clock noise can limit accuracy   4 GOWIN TDC Solution    While implementing TDCs in FPGAs offers tremendous flexibility and performance, designers often face a set of persistent challenges tied to the nature of traditional FPGA fabric. Gowin Semiconductor addresses these issues with a unique architectural innovation, offering a more robust and scalable TDC solution. The Challenges of FPGA-Based TDCs While FPGAs are widely used for implementing TDCs, several technical limitations can impact timing accuracy and reliability: Routing and Placement Variability Traditional TDC designs in FPGAs rely on a general-purpose logic fabric and internal routing. As a result: Delay lines are non-uniform due to synthesis and routing differences. Fine-tuning the layout requires manual floorplanning and careful timing analysis. Achieving consistent results across devices and designs can be difficult. Environmental Sensitivity Standard FPGA delay elements are sensitive to: Temperature changes Voltage fluctuations Process variations This leads to timing drift and requires active calibration or thermal compensation, increasing complexity and design time. Gowin’s Solution: Dedicated IO-Based Delay Architecture To overcome these limitations, Gowin FPGAs integrate dedicated delay lines and registers directly into the IO blocks offering a new standard in accuracy and robustness for TDC design. Key Advantages Stable and Uniform Delay Lines Dedicated delay elements in the IOs are physically consistent and isolated from logic fabric. No dependency on random logic placement or FPGA routing. Ensures high linearity and repeatable measurements across multiple devices and temperature ranges. Reduced Environmental Sensitivity IO block architecture minimizes the impact of process, voltage, and temperature (PVT) variations. Significantly improves timing stability without requiring external calibration or complex compensation logic. High Channel Density Gowin FPGAs offer a high number of IOs per device, enabling the implementation of multi-channel TDCs at low cost. Ideal for applications such as LiDAR, SPAD arrays, and quantum experiments where many parallel timing channels are required. Low-Cost and Power-Efficient By moving the TDC function to dedicated IO resources, Gowin avoids overloading core logic, allowing for smaller and more power-efficient FPGA configurations. Enables system designers to reduce BOM cost while maintaining high performance. Benchmarks 8 bits TDC in GW1N-1K, resolution can be 30ps or less 16 bits TDC in GW1N-2K works well @ 960MHz (7.8cm TDC) 32 bits in GW5A-138K tested @1650MHz (4.54cm TDC) 16 bits in GW5A-138K tested @1600MHz (4.69cm TDC) Note, the clock frequency is the CLK in IOLogic driven by PLL. The resolution X C = distance, where C is the speed of light   Summary While traditional FPGA-based TDCs offer flexibility, they often fall short in terms of consistency, environmental stability, and scalability. Gowin’s dedicated IO-based delay architecture directly addresses these challenges, delivering a stable, accurate, and scalable TDC platform. By combining high IO count, reduced sensitivity to environmental variation, and low cost, Gowin FPGAs offer a differentiated solution for multi-channel TDC implementations—empowering designers to build faster, more reliable time-domain systems with confidence. 5 Device and IP Support  GOWIN TDC solution can be implemented in all Gowin FPGAs. The resolution will vary depending on the devices. Gowin EDA tools provide TDC IP and Guideline documents to help users to implement this solution. Please see IPUG1208-1.0E_Gowin TDC IP User Guide. Here is the EDA software view of this IP:   Here is the IP core generator view:   6 Real World Applications    3D Time-of-Flight (ToF) Cameras ▸ Use Case: ToF cameras are used in mobile devices, industrial automation, gesture control, and augmented reality systems. They emit a short light pulse (typically from a VCSEL) and measure the time it takes for light to bounce off an object and return to the sensor. ▸ Role of FPGA TDC: Each SPAD (Single Photon Avalanche Diode) pixel in a ToF image sensor detects individual photons. A TDC in the FPGA measures the arrival time of the first photon per pulse. Timing precision of 20–100 ps enables accurate depth resolution (down to millimeter scale). Multiple TDCs may run in parallel (one per pixel or pixel group) to support high-resolution, real-time depth maps. ▸ Why FPGA: FPGAs provide massive parallelism, essential for capturing data from hundreds or thousands of SPADs simultaneously. They also allow real-time histogramming and digital filtering, minimizing external processing and improving accuracy. Quantum Optics & Time-Correlated Photon Counting (TCSPC) ▸ Use Case: In quantum communication, quantum key distribution (QKD), and fluorescence lifetime imaging (FLIM), precise photon arrival time is critical. Researchers use these systems to study entanglement, photon correlations, and lifetimes at the single-photon level. ▸ Role of FPGA TDC: TDCs capture photon arrival timestamps with picosecond precision. Used in Time-Correlated Single Photon Counting (TCSPC) to build statistical histograms of photon events over time. Events are often random and sparse, requiring high-resolution, high-sensitivity, low-dead-time timing logic. ▸ Why FPGA: FPGA-based TDCs can be deeply customized for trigger logic, filtering, gating, and correlation algorithms. Researchers often use multi-channel TDCs to correlate events across different detectors. FPGA implementation offers real-time processing, eliminating the need for bulky post-processing steps. Digital Oscilloscopes and Signal Analysis ▸ Use Case: Modern oscilloscopes (especially digital sampling scopes and time interval analyzers) rely on high-precision time capture to measure jitter, edge timing, and propagation delays in high-speed circuits and communication interfaces. ▸ Role of FPGA TDC: TDCs measure time intervals between fast rising/falling edges far more precisely than typical clocked sampling (which is limited to ~200ps at 5 GHz). TDCs can enable interpolation between sample points, enhancing effective timing resolution. Used for jitter analysis, eye diagram generation, and signal integrity testing. ▸ Why FPGA: FPGA fabric is ideal for implementing custom trigger logic, cross-domain synchronization, and time-tagging systems with minimal latency. In portable or embedded scopes, TDCs in FPGAs can reduce BOM cost while still achieving professional-grade accuracy. Precision LiDAR Systems ▸ Use Case: In autonomous vehicles, drones, and surveying systems, LiDAR (Light Detection and Ranging) is used to build real-time 3D maps of the environment. Precision timing is key to converting photon return time into accurate distance. ▸ Role of FPGA TDC: Each laser pulse reflected off an object is captured by a detector (e.g., SPAD or APD). The TDC measures the time from laser emission to photon return. Timing resolution directly impacts ranging accuracy: e.g., 10 ps resolution ≈ 1.5 mm distance accuracy. ▸ Why FPGA: LiDAR often requires multi-beam systems with multiple detectors firing rapidly (up to millions of events per second). FPGA TDCs allow scalable parallelism and on-the-fly filtering to reject noise, ambient light, and invalid events. TDCs implemented in IOs (as in Gowin FPGAs) reduce latency and power, critical for embedded mobile LiDAR. A reconstructed 3D model by using 128-channel TDCs in the GW5A-138K device   7 A DIY Project Example   You can indeed build an ADC (Analog-to-Digital Converter) using TDC (Time-to-Digital Converter) principles. This method is often called a Time-Based ADC or Time-Encoding ADC, and it leverages the conversion of an analog voltage into a time interval, which is then measured by a TDC. Here’s how it works, how it's constructed, and where it's useful: Basic Idea: Instead of directly digitizing voltage levels (as in a traditional ADC), you convert the analog voltage into a time delay, and then measure that delay using a Time-to-Digital Converter. Voltage → Time → Digital This approach takes advantage of the high timing resolution of modern TDCs, often enabling very fine quantization steps with lower power and simpler analog front ends.     How It Works: Core Components Voltage-to-Time Converter (VTC) This circuit converts the analog input voltage into a time delay. Common implementations: Ramp Generator + Comparator: A reference voltage ramps linearly. When it crosses the input voltage, a comparator triggers the stop signal. The time from start of ramp to trigger = analog voltage. Current-Starved Delay Chain: Delay elements modulated by analog voltage control current (and therefore delay). Used in some VCO-based architecture. Time-to-Digital Converter (TDC) Once the analog voltage is converted into a delay (a time interval), a high-resolution TDC digitizes that time. The output is a digital code corresponding to the original input voltage. Timing Diagram (Conceptual): Timing Diagram of ADC based on TDC   ADC Performance Overview Reference implementation and performance validation were conducted on the TANG Nano 4K development board (Chip: GW1NSR-LV4CQN48PC7/I6). Testing Setup:     Results Resolution: 7-bit Sample Rate: 60 kSPS to 1 MSPS Linearity (INL): ±6 LSB @ 60 kSPS ±10 LSB @ 1 MSPS (1 LSB = 10 mV) Input Range: 0–0.8 V Effective Resolution: ~6.5 bits FPGA Resource Utilization (Per ADC Channel) Logic Registers: 160 Block SRAM (BSRAM): 1 block IDES8: 1 unit PLL: 1 LVDS Differential Pair: 1 Single-Ended I/O: 1 This makes the solution efficient for integration into small, cost-sensitive FPGAs while preserving sufficient logic and memory for additional system logic or control tasks Advantages High Resolution: TDCs can achieve ps-level resolution, translating to high-bit ADCs without expensive analog components. Low Power: Especially in applications that need low sampling rates (e.g., instrumentation). Digital-Friendly: Most of the system is digital, making it ideal for FPGA or ASIC implementation. Challenges Nonlinearity: VTCs (especially ramp generators) often suffer from nonlinearity and temperature drift. Calibration: Requires runtime or startup calibration to maintain accuracy. Speed Limitations: Faster input conversion needs faster ramp/delay control, which becomes challenging. Noise Sensitivity: Analog front-end still needs a careful design to reduce jitter and drift. Applications Low-speed, high-resolution sensors (e.g., temperature, pressure, bio-sensing) Time-domain signal processing FPGA-based instrumentation Neuromorphic or event-based processing Radiation-hardened or simplified ADC designs for harsh environments   8 Conclusion    Time-to-Digital Converters are at the heart of many emerging technologies, from high-resolution 3D imaging and LiDAR to quantum research and precision instrumentation. While FPGAs have long been a flexible platform for TDC design, traditional implementations often face limitations in timing accuracy, environmental stability, and scalability.   GOWIN Semiconductor addresses these challenges with a novel IO-based TDC architecture, delivering consistent and precise delay lines that are inherently less sensitive to temperature, voltage, and process variations. This architecture not only improves measurement linearity and timing resolution but also enables high channel density and efficient power utilization, critical for modern applications that demand real-time performance and compact form factors.   By integrating TDC functionality into dedicated IO resources, GOWIN FPGAs simplify design complexity, reduce calibration overhead, and lower total system cost. The result is a scalable, robust, and cost-effective timing solution ideal for engineers and system designers pushing the boundaries of time-domain performance.   As the need for precise timing grows across industries, GOWIN’s FPGA-based TDC solution provides a reliable foundation for innovation, empowering next-generation systems with the accuracy, flexibility, and efficiency required to meet tomorrow’s demands.   Support and Feedback GOWIN Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail：support@gowinsemi.com Revision History Date Version Description 2025/07/08 1.0E Initial draft  

Affordable, Robust, and Fast: GOWIN’s Industrial Gigabit LVDS Networking Solution   1 Abstract   In the era of Industry 4.0, reliable, low-latency communication is crucial for modern industrial systems, yet the high cost and complexity of existing industrial Ethernet solutions remain significant barriers, particularly for small and medium enterprises. This white paper introduces GOWIN Semiconductor’s Gigabit LVDS Datalink with Embedded Clock, a simplified, cost-effective alternative to traditional networking approaches.   Leveraging GOWIN’s EasyCDR® technology and FPGA-embedded resources, this solution supports high-speed, low-power, and deterministic data transmission ideal for PLC backplanes, EtherCAT® slave expansion, energy management systems, and robotic control. The paper outlines the technical architecture, packet protocol, and implementation examples in master/slave configurations, showcasing how GOWIN’s solution reduces wiring complexity, boosts throughput, and enhances noise immunity.   Targeting up to 64 nodes with support for gigabit data rates and integrated CRC and 8b/10b encoding, this scalable solution empowers engineers to build robust, flexible, and efficient industrial networks with minimal overhead.   2 Industry networking solution overview Networking is essential today in industrial control systems because it enables seamless communication, coordination, and efficiency in complex manufacturing environments.   Networks in industry automation    Here are just a few examples: Industrial Automation PLC Control Systems: Serves as an expansion unit for PLCs, connecting sensors and actuators. DCS Systems: Collects and outputs a large number of field signals for process control. Production Line Monitoring: Used for equipment status monitoring and product quality inspection. Building Automation Lighting Control Systems: Digital I/O modules for switch control. HVAC Systems: Interfaces for temperature and humidity sensors. Security Systems: Signal processing for access control and surveillance. Energy Management Power Monitoring Systems: Acquisition of voltage and current signals. New Energy Systems: Interfaces for photovoltaic inverters and wind power converters. Smart Grids: Remote terminal units (RTUs) for monitoring and control. Transportation Rail Transit Signaling Systems Intelligent Traffic Light Control Vehicle Detection and Control Systems Test and Measurement Systems Laboratory Data Acquisition Systems Automated Product Testing Platforms Environmental Monitoring Equipment   Addressing Limitations of Current Industry Network Solutions While current Industrial Ethernet solutions offer advanced capabilities for industrial automation and control systems, enabling real-time control, synchronization, and data exchange, there is still room to improve for even wider spread adoption. The primary barriers are the high costs of hardware, specialized switches, coupled with the complexity of integrating these systems into existing setups, managing latency, and ensuring cybersecurity. These factors limited them to many manufacturers, especially small to medium enterprises.   GOWIN Semiconductor Corp. proposes a simpler, low-cost industrial networking solutions that address these issues effectively. Our solution leverages GOWIN EasyCDR® technology with optimized communication protocols to achieve reliable, low-latency communication suitable for industrial automation production lines, smart factories, energy monitoring systems, and multi-axis robots. By simplifying network configuration, this approach lowers implementation costs and complexity while maintaining essential performance and latency, scalable architecture. This innovative solution could democratize advanced automation networking, making it accessible to a broader range of industries.   3 System Architecture   Network Topology One typical industry network is Sliced IO module on a backplane. The picture below is one example of PLC Module. A Modular Sliced IO system   The following diagram shows the network topology by using the backplane implementation as an example.     As the above diagram shows, the data links (the blue traces) forms a ring topology in the backplane. It includes 2 data stream links between the line cards with an FPGA on it and the wrap around at the end points. The number of line cards can be placed on the backplane, theoretically only limited by the size of the plane; however, the latency of data going through all the line cards will increase with more cards in place.    Though the topology is natural for each line card, this can be implemented with one of these cards as the Master card, while all the others as Slave cards. Beside this backplane example, cabling can also be support with this solution. There will be difference speed that can be achieved with different table and length. In general, we expect typically we can achieve Gigabit per second on 3-meter-long SATA or USB types of cables; 100MHz running on Twist wires CAT5 or CAT6 cables.   Electrical Signaling Backplane systems are critical infrastructure in data centers, telecom switches, industrial control systems, and military applications. These systems demand reliable, high-speed data transmission with minimal noise and low power. Low-Voltage Differential Signaling (LVDS) is a widely adopted interface standard that meets these stringent demands effectively.   High-Speed Performance LVDS supports data transmission rates exceeding 1–3 Gbps per channel, making it suitable for high-throughput applications. Combined with serialization techniques, it can aggregate multiple data channels over fewer lines, reducing routing complexity.   Low Power Operation One of LVDS's hallmark benefits is its low power consumption. The typical voltage swing of ~350 mV results in minimal current drawing, reducing overall system power and enabling dense, thermally efficient designs—an important factor in rack-mounted systems.   Excellent Noise Immunity Differential signaling provides inherent resistance to common-mode noise, ensuring robust operation in electrically noisy environments. In backplane systems, where multiple modules and cards operate in close proximity, this is a critical advantage.   Signal Integrity Over Distance LVDS maintains strong signal integrity over long traces, connectors, and through-plane vias. Its low EMI profile minimizes interference with adjacent channels, enabling high-density, multi-channel backplane architectures.   Compatibility and Ecosystem Support LVDS is supported by a wide range of FPGAs, ASICs, and SerDes transceivers. This wide ecosystem simplifies system design and integration, offering flexibility across generations of products.   Low Electromagnetic Interference (EMI) Because it uses tightly coupled differential pairs with small voltage swings, LVDS generates very low EMI. This not only aids in regulatory compliance but also reduces the likelihood of inter-channel interference in compact designs. LVDS combines speed, efficiency, and reliability, making it a strong choice for modern backplane applications.   Packet Data format The data is transmitted in the data link by packet. The Packet is consistent with Preamble, Command, ID, data, and parity bit to ensure a quick and reliable transmission. The details of the data packet can be defined in the following table: Definition Length Value Preamble 3 bytes 24'hAA _AA_AA Comma Symbol 1 byte 8'hBC/DC/FC/7C Frame type & Slave quantity 1 byte 2'hxx & 6'hxx Slave data length (bytes) 1 byte 8'hxx 2 bits Reserved & Slave lD 1 byte 2'h00 & 6'hxx Slave0 data 1~256 bytes 8'hxx…8'hxx Slave1 data 1~256 bytes 8'hxx…8'hxx …… …… 8'hxx…8'hxx SlaveN data 1~256 bytes 8'hxx…8'hxx CRC16 Checksum 2 bytes 8'hxx, 8'hxx Error Indication 1 byte 8'hxx   4 Module Architecture   When implemented in a Master/Slave type of data transmission application, the Master and Slave logic will be implemented differently. The following examples are utilizing the general IDES and OSER logic block in every IO of all GOWIN FPGAs to perform the downstream and upstream data transfer and utilize the FPGA fabric to implement the CRC16 and 8b10b encoder/decoder logics. The typical performance is 100MHz LVDS signaling. For the GW5A series FPGAs, GOWIN’s EasyCDR® technology can be utilized for downstream and upstream data transfer. Therefore, Gigabits per second data rate can be achieved. The Master Controller primarily consists of a control logic module, a CRC check module, an 8B/10B encoder/decoder module, a data serialization module, a data oversampling and recovery module, and a phase-locked loop (PLL). According to the data flow direction, these modules form the downlink and uplink transmission paths. The Slave Controller primarily consists of a control logic module, a CRC check module, an 8B/10B encoder/decoder module, a data serialization module, a data oversampling and recovery module, and a PLL. According to the data flow direction, these modules form the downstream (input from the upstream port and output to the downstream port) and upstream (input from the downstream port and output to the upstream port) transmission paths, respectively.     Typical Resource Utilization For Master controller LUT4 FF BSRAM Target Device 672 410 1 All GOWIN FPGAs   For Slave controller LUT4 FF BSRAM Target Device 1683 991 2 Device with 2K and above logic resource   Solution Highlights LVDS data is transmitted with an embedded clock. Clock Data Recovery uses hardened blocks such as IDES, OSER, or EasyCDR® blocks in every IO of the GOWIN FPGA Implemented 8b/10bencoding and decoding and CRC parity bits to improve the reliability of data communication The data rate can be up to Gigabits per second The current version of GOWIN IP can support 1 Master, up to 64 Slave modules The data packet size is up to 256 Bytes with the current version of IP The master module can support communication via Unicast Frames Supports the Slave synchronization function Master can identify the total Slave module number, and the last Slave module can self-wrap around Slave can self-diagnose when the data link is interrupted. Keeps the system online when performing such action, increasing system robustness   5 Typical Applications   (I) Simplifying Industrial Networking with GOWIN’s Gigabit LVDS solution   In the evolving landscape of industrial automation, system performance, wiring complexity, and cost are critical factors in network design, especially for fieldbus protocols like EtherCAT®. GOWIN Semiconductor addresses these demands with its Gigabit LVDS Datalink with Embedded Clock, a high-speed, low-latency communication solution designed to simplify network expansion and enhance performance.   A Smarter Way to Extend EtherCAT® Slave Networks Traditional methods of extending EtherCAT® slave node networks often rely on complex Ethernet-based cable and hardware, which can introduce latency, increase costs, and complicate installation in space-constrained or harsh industrial environments. GOWIN’s Gigabit LVDS Datalink provides a streamlined alternative.   By utilizing Low Voltage Differential Signaling (LVDS) with an embedded clock, this solution enables high-speed serial data transfer over simple point-to-point connections, eliminating the need for external clock routing and reducing pin count. This makes it ideal for expanding slave nodes in a compact, deterministic, and low-cost manner.     Shown above is a representative application of the LVDS bus system, which typically serves as a low-cost and efficient extension to Industrial Ethernet nodes, enabling simpler and more flexible physical-layer communication.   Key Advantages Simplicity in Wiring: The embedded clock feature removes the need for a separate clock signal line, reducing cable complexity and connector size. Ultra-Low Latency: The direct and deterministic nature of LVDS transmission ensures minimal delay, supporting real-time industrial control. Cost-Effective: With fewer components and simpler PCB and cable design, system costs are significantly reduced. High Throughput: Gigabit-level data rates support demanding industrial data exchange needs. Ideal for Industrial Applications Whether used in robotics, motion control, or factory automation systems, this solution enables manufacturers to extend EtherCAT® slave networks efficiently while maintaining strict performance and timing requirements.   (II) Multi-dimensional control in Humanoid Robotic Systems Humanoid robotic hands aim to replicate the dexterity and adaptability of human fingers, but this involves a series of complex challenges. Here's a brief look at the main hurdles engineers face:   Complex Mechanics Human fingers have multiple joints and degrees of freedom. Replicating this requires many actuators and precise coordination, making both design and control complicated. Miniaturization Fitting motors, sensors, and wiring into the small size of human-like fingers is technically demanding, often limiting design options. Tactile Feedback Accurate touch and force sensing is essential for manipulation but difficult to achieve at small scales with sufficient sensitivity and robustness. Control Algorithms Robotic fingers must handle nonlinear dynamics and tightly coupled joint motions. Advanced control strategies are needed to ensure stable, responsive movements. Dexterous Grasping Grasping varied objects reliably remains a tough problem. It demands smart integration of vision, touch, and motion planning in real time. Power Constraints High-performance actuators use significant energy, creating trade-offs between power, size, and battery life in humanoid designs. In Summary Humanoid robotic finger control requires solving intertwined problems in hardware, sensing, and control. A simplified, high efficiency, low power, low-cost network is required for such challenges. Here is our proposed network scheme that can meet these requirements.   In the above diagram, multiple motors need to be acting in Sync with the sensed data from the action point. The host is acting as a central command unit. Based on data feedback from the action fields, it sends out action commands to each motor. To carry out such tasks, a dual datalink network formed by multiple FPGAs, as mentioned in this article, are used. Each of the nodes is consistent with one motor, at least one sensor, and one FPGA connected to them. The FPGA is facilitating sensing, motor control, and data communication tasks. The ideal devices that can deal with all these tasks are probably GOWIN’s GW5AS-LV25 or a smaller one, GW1NS-LV4. The downstream datalink carries out the commands from the Host, and each node receives such a command, acting on it to control the motor to perform as designed tasks. The upstream datalink transfers the sensor’s data back to the host so that it can calculate what the next action needs to be sent out. In conclusion, such a solution provides low latency, high speed, low cost, low power, and simple wiring that can meet the challenges in this field. 6 Supported GOWIN Devices and IPs   This solution is available across the full range of: GW5A series with EasyCDR® running up to Gigabits per second GW1N series typically runs at 100MHz GW2A series typically runs at 100MHz GOWIN provides: Reference Designs and IP for rapid prototyping   7 Conclusion   GOWIN’s Gigabit LVDS Datalink with Embedded Clock solution offers a compelling alternative to traditional industrial networking methods. By addressing the key limitations of conventional systems, such as high costs, complex wiring, and integration challenges, this solution delivers substantial value to engineers and system designers working in industrial automation, robotics, energy systems, and intelligent transportation. Unlike conventional Ethernet-based solutions that often require specialized switches, bulky cabling, and intricate configuration, GOWIN’s approach simplifies implementation through embedded clocking, point-to-point LVDS signaling, and a scalable FPGA architecture. The result is a low-cost, low-latency, and high-speed communication platform that enables real-time data transfer with excellent noise immunity and minimal electromagnetic interference (EMI). With support for up to 64 slave nodes, packet-based transmission with CRC error checking, and gigabit-level throughput using EasyCDR® technology, this datalink architecture is well-suited for modern industrial environments that demand precision, reliability, and flexibility. Ultimately, GOWIN’s LVDS solution not only enhances system performance but also reduces time-to-market and total cost of ownership, making it an ideal fit for customers seeking efficient, robust, and future-ready connectivity in their next-generation industrial designs.   8 Reference   IPUG1219-1.0, 06/27/2025 LVDS Data Transmission System with Embedded Clock Design Guide-For Internal Use EasyCDR® White paper GW5AS-LV25UG256 data sheet Trademark Acknowledgments: EtherCAT® is a registered trademark and patented technology, licensed by Beckhoff Automation GmbH. EasyCDR® is a registered trademark of GOWIN Semiconductor Corp.   Support and Feedback GOWIN Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail：support@gowinsemi.com Revision History Date Version Description 2025/06/30 1.0E Initial draft   Copyright © 2025 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.   Gowin, LittleBee, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.   Disclaimer GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

Excited to announce our collaboration with @motsai research Inc. on their latest E-book: "MicroFPGA Advantages for System Integration." Explore how our LittleBee Device elevates #safety protocols, boasts 480 MBps #usb capabilities, integrates an ARM Microcontroller for seamless device setup, features rapid PLLs for precise clock generation, delivers short pulses, and facilitates high-speed ADC interfaces—all at a minimal cost to your BOM. These self-contained ICs are truly captivating.   Moreover, GOWIN FPGAs power high-speed, low-latency sensors, enabling them to capture intricate information streams effortlessly.   A heartfelt thank you to Motsai for spotlighting our LittleBee device in their comprehensive E-book on the advantages of MicroFPGAs.   To dive into this invaluable resource, download the Ebook for free here: https://motsai.us11.list-manage.com/subscribe?u=8285640e304be727aedd5b120&id=46d231e7fb

    1  範囲   このドキュメントは、ユーザーが設計に最適なデバイスを選択できるように、GOWINのMIPIソリューションの包括的な概要を提供することを目的としています。詳細な実装を行う際には、ユーザーは他のGOWINユーザーガイドとアプリケーションノートを参照する必要があることに注意してください。   2. MIPIの概要   モバイルプロセッサ インターフェース (MIPI®)規格は、スマートフォン、タブレット、ラップトップ、ハイブリッドデバイスなどのモバイルデバイスの設計に関する業界仕様を定義します。この規格は、モバイルエコシステム、特にモバイルに影響を受ける産業を含むスマートフォンのための技術仕様を開発するグローバルなビジネスアライアンスでによって開発され、維持されています。GOWINセミコンダクターはMIPI Allianceのメンバーです。   長年にわたり、MIPIは携帯電話の代名詞のような存在でした。しかし、高解像度のイメージセンサーがAI、IoT、オートモーティブ、医療機器に導入されることが増えるにつれ、MIPIへの関心は中核市場をはるかに超えて広がっています。標準化された信号プロトコルと特性が不可欠になりつつある一方で、ますます多くのアプリケーション向けに低コストで高性能のイメージセンサーが爆発的に普及し、MIPIインターフェースが多様な新しい市場に進出しています。   MIPI規格では、MIPI D-PHY®、C-PHY®、M-PHY®、およびA-PHY®の4つのユニークな物理 (PHY) 層仕様が定義されています。詳細情報と仕様は、MIPI Allianceのホームページからご覧いただけます。   MIPI®サービスマークおよびロゴマークはMIPI Alliance, Inc.に帰属しており、Gowinセミコンダクターによるかかるマークの使用はライセンスに基づいています。その他のサービスマークおよび商標名は、それぞれの所有者のものです。   3. GOWIN MIPIソリューションの概要   GOWINは最初のFPGAデバイスでMIPI D-PHYソリューションを開発しました。それ以来、ほぼすべてのGOWIN FPGAがさまざまな構成と速度のMIPI IPコアを提供してきました。GOWINは、FPGA(Arora V FPGA)でMIPI C-PHY IPコアを提供する業界初のFPGAメーカーです。GOWINは、前記のArora V FPGA用のM-PHYコアとA-PHYコアを間もなく提供する予定です。以下は、GOWIN MIPI PHYの概要です。パフォーマンスの詳細については、次のセクションで説明します。   ドキュメントに記載されているスペックの数字は、これまでの最良の情報に基づいたものです。これらは将来のバージョンのリリースで更新される可能性があります。   表1 Gowin MIPI D/C PHYのサポート(将来更新される可能性がある)   DPHY Rx DPHY Tx CPHY Rx CPHY Tx 備考   GW1N(X)シリーズとGW2A(X)シリーズ GPIOによるソフトコアIP すべて：最大1.2Gbps すべて：最大1.2Gbps N/A 最大1.0Gsps* C7スピードグレード以上で最大 ハードコアIP GW1N(X)-LV2：最大1.5Gbps N/A N/A N/A 1コア(4レーン)   GW5A(X)シリーズ(138K) GPIOによるソフトコアIP 最大1.5Gbps 最大1.6Gbps 最大1.1Gsps * 最大1.1Gsps * - ハードコアIP 最大2.5Gbps N/A N/A N/A 138K: 2コア(各コア4レーン)(Rx)   GW5A(X)シリーズ(60K/25K/15K) GPIOによるソフトコアIP 最大2.0Gbps 最大2.0Gbps 最大1.2Gsps * 最大1.2Gsps * - ハードコアIP 最大2.5Gbps 最大3Gbps 最大2.5Gsps 最大3Gsps 1コア(4レーン)(Rx/Tx) 1コア(3トリオ)(Rx/Tx) 注記： "*"は、配線長を最小限に抑えるために1つのトリオを構成するには、パッケージとPCB内で6本のGPIOを配線する必要があることを示します。 GW5A(X)は、最大5Gbpsの、GPIOによるM-PHY IPおよびA-PHY IPを提供します。 ここでの数値は、社内または現場でのさらなるテスト結果によって更新される可能性があります。   4. ハードコアMIPI PHY IP   GOWINは、そのGW1N-LV2デバイスにおいて、初のハードMIPI D-PHY Rxコアを自社開発しました。このIPコアはMIPI D-PHY Spec V2.1に準拠し、最大受信データレートは2Gbpsです。 次世代Arora V FPGAでは、GOWINは2.5GbpsのD-PHY V1.2と2.5Gsps（5.7Gbps）のC-PHY V1.1の両方を様々なデバイス向けに開発しました。詳細は下表の通りです： 表2 Arora Vデバイスの主な特徴 主な特徴 138K 75K 60K 45K 25K 15K デスキュー機能付きMIPI-DPHY RX/TX Rx Only Rx Only Y Y Y Y レシーバーイコライゼーション。SoT HS-Sync、ワードアライメントおよびレーンアライメント Y Y Y Y Y Y PHYは、MIPI以外の一般的なソース同期高速インターフェースとして構成可能 Y Y Y Y Y Y DPHY TX/RXパッドの共有。4データレーン、レーンごとに構成可能 Rx Only Rx Only Y Y Y Y CPHY RX/TXパッドの共有。最大3Gsps、3トリオ N N Y Y N Y     以下は、25KデバイスMG121Nパッケージのループバックテストのセットアップです。     以下は、25Kデバイスの3Gbpsでのテスト結果からのアイ・ダイアグラムです。     C-PHYについては、以下に60K C-PHYコアのシミュレーション結果を示します。テスト結果は、24年第2四半期に予定されているドキュメント更新で公表される予定です。     もうひとつ興味深いのは、より長距離のアプリケーションです。MIPI規格は、スマートフォンやその他の携帯機器向けに最適化されており、狭いスペースで短い距離が想定されていますGOWINのHard IPを使えば、より長い距離が必要な場合に、イコライゼーション機能によってユーザーを後押しすることができます。次のユーザー ケースが参考になります。 GW1N(X)-LV2デバイスの場合、長さ5mのSATA/HDMI/DP線、データレート500Mbps。 GW5A(X)デバイスの場合、長さ2mのCAT6線、データレート25Gbps。 カメラとディスプレイが別々の場所にあるアプリケーションの場合、この機能により、ワンチップソリューションが可能になります。     5. GPIOによるソフトコアMIPI PHY IP   FPGAのプログラマブルIOにより、外部受動抵抗ネットワークを利用して多くのインターフェースをエミュレートすることができます。GPIOによるMIPI PHYソリューションの最大の利点はその柔軟性です。このホワイトペーパーの冒頭で述べたように、MIPI規格は従来のスマートフォンという分野を超えています。この柔軟性とFPGAのプログラマビリティの組み合わせは、新しいアプリケーション分野の多様性によく適合しています。以下にいくつかの例を示します。電気自動車（EV）内のマルチディスプレイには6～8個のMIPI Txポートが必要になる場合があります。VRまたはドローンシステムでは、入力として12台のカメラが必要となり、データが1つの出力に集約される場合があります。今日のSoCの中で、このような要件に対応できるものはほとんどありません。以下は、3つのLCD方式を利用した3Dプリンティングシステムのユーザーケースです。     現在、多くのFPGAがMIPI D-PHYをサポートしていますが、GOWINのFPGA は、特許技術によりMIPI C-PHY、MIPI M-PHY、MIPI A-PHYをサポートできる最初のFPGAです。   MIPI D-PHY   以下の図は、MIPIシグナリングをエミュレートするための受動抵抗ネットワークの 1つの実装例を示しています。最高のパフォーマンスを達成するには、配線とシグナル・インテグリティを考慮することが非常に重要です。     Gowinデバイスでは、社内テストと顧客レポートから次の最大データレートが達成されています。 C6スピードグレードのGW1N(X)シリーズFPGAの場合、最大データレートは900Mbps ～ 950Mbps C7スピードグレードのGW1N(X)シリーズFPGAの場合、最大データレートは1Gbps ～ 1.2Gbps C8スピードグレードのGW2A(X)シリーズFPGAの場合、最大データレートは1Gbps ～ 1.2Gbps C0スピードグレードのGW5A(X)シリーズFPGAの場合、最大データレートは0 Gbps (社内の、生データのループバックテストで2.5 Gbpsが観測されました) 最大データレートは、GPIOよりも内部クロックの性能に関係しています。GW5AT-138/75デバイスの最大データレートは1.6Gbpsであり、大きなダイのローカルクロックが他のデバイスに比べて相対的に性能が低いためです。        b. MIPI C-PHY   GOWINは、革新的なGPIOシステムを通じてGPIOによるMIPI C-PHYソリューションを提供する業界初のFPGAベンダーです。これらのIPは、Arora V FPGAでのみ使用できます。次の図は、GOWINの特許取得済みのGPIOによるソフトMIPI C-PHY IPソリューションを示しています。次の図はそのシステムアーキテクチャを示しています。   以下は、GOWINのEasyCDR® IPを利用した、より詳細なRxシステムの実装です。     25Kデバイスでループバックテストがセットアップされて測定されました。以下はベンチのセットアップです。     テスト結果は、800Mspsでのループバックが達成されたことを示しています。以下は400Mspsと700Mspsでのアイ・ダイアグラムです。     これは、テストPCBの配線長の制限によるものです。より高速な速度が達成できると考えられます。近い将来、さらに多くのデータが収集される予定です。       c. MIPI M-PHY   従来のアナログSerDesベースのM-PHY設計と比較して、GPIOベースのM-PHY は消費電力、コストが大幅に低く、柔軟性が高くなります。これらのIPは開発中であり、Arora Vデバイスで利用できるようになる予定です。私たちの目標は次のとおりです。   HS-G1: 1.25, 1.45 Gb/s HS-G2: 2.5, 2.9 Gb/s       d. MIPI A-PHY   従来のアナログSerDesベースのA-PHY設計と比較して、GPIOベースのA-PHYは消費電力、コストが大幅に低く、柔軟性が高くなります。これらのIPは開発中であり、Arora Vデバイスで利用できるようになる予定です。私たちの目標は次のとおりです。   Gear Data rate G1 Uplink   6. GOWIN MIPI PHY IP、プロトコル層IP、およびそのリファレンス・デザイン   GOWINは、EDAツール上のIP Core Generatorを通じて、多くのPHY IPと、MIPI CSI-2やMIPI DSIなどのプロトコル層のソフトコアIPを提供します。 IP タイプ デバイス リファレンス・デザイン 文書 MIPI_DPHY (Tx/Rx) ハードコア GW5A(X) Gowinの営業担当者およびFAEにお問い合わせください。 http://cdn.gowinsemi.com.cn/UG296J.pdf MIPI_DPHY_RX ハードコア GW1N(X)-2 Gowinの営業担当者およびFAEにお問い合わせください。 http://cdn.gowinsemi.com.cn/IPUG778J.pdf MIPI_TX_Advance ソフトコア 文書参照 http://cdn.gowinsemi.com.cn/Gowin_MIPI_DPHY_Advance_refDesign.zip https://www.gowinsemi.com/en/support/ip_detail/59/ MIPI_RX_Advance ソフトコア 文書参照 http://cdn.gowinsemi.com.cn/Gowin_MIPI_DPHY_Advance_refDesign.zip https://www.gowinsemi.com/en/support/ip_detail/59/ MIPI_DSI/CSI-2_Receiver ソフトコア すべてのデバイス https://www.gowinsemi.com/upload/database_doc/2678/document/651543b559cd7.zip https://www.gowinsemi.com/en/support/ip_detail/143/ MIPI_DSI/CSI-2_Transmitter ソフトコア すべてのデバイス https://www.gowinsemi.com/upload/database_doc/2676/document/65153e70b71dd.zip https://www.gowinsemi.com/en/support/ip_detail/144/ MIPI_Byte-to-Pixel_Converter ソフトコア すべてのデバイス https://www.gowinsemi.com/upload/database_doc/2678/document/651543b559cd7.zip https://www.gowinsemi.com/en/support/ip_detail/141/ MIPI_Pixel-to-Byte_Converter ソフトコア すべてのデバイス https://www.gowinsemi.com/upload/database_doc/2676/document/65153e70b71dd.zip https://www.gowinsemi.com/en/support/ip_detail/142/     7. 結論   GOWINのMIPIソリューションは、ユーザーが設計ニーズに最適なソリューションを選択できるように支援することを目的としています。MIPI規格の進化に伴い、これらのインターフェースはスマートフォンの分野を超え、人工知能、IoT、オートモーティブ、医療機器など幅広いアプリケーションを網羅するようになっています。 MIPI統合の進展に対するGOWINの取り組みは、MIPI D-PHYソリューションの先駆的な開発と、Arora V FPGAでのC-PHY、M-PHY、および今後のA-PHY実装への拡張を通じて実証されています。この包括的なソリューションは、さまざまな性能要件とアプリケーションシナリオに対応します。 この文章では、GOWINが採用した2つの主要なアプローチ、つまりハードコアMIPI PHY IPおよびGPIOによるソフトコアMIPI PHY IPの開発について説明しました。ハードコアIPは標準への準拠と最適化された性能を保証し、ソフトコアIPはFPGAのプログラマビリティを活用して、多様なアプリケーションのニーズに適合する比類のない柔軟性を提供します。 さまざまなFPGAファミリにわたる性能ベンチマークは、拡張性と適応性を強調しており、さまざまな性能要求を満たすためのGOWINの取り組みを実証しています。さらに、GOWINは、EDAツール上のIP Core GeneratorによりMIPI CSI-2やMIPI DSIなどのプロトコル層のソフトコアIPを提供し、製品の広さを強化し、シームレスな統合と設計体験を可能にしています。 最終的に、このホワイトペーパーは、設計者がGOWINの多用途MIPI製品を効果的にナビゲートできるようにする実用的なガイドとなります。MIPIインターフェースのさまざまなアプリケーションへの統合を促進することで、GOWINは業界全体のイノベーションをサポートし推進することを目指しています。                                            

ホワイトペーパー       1  要約   バッテリー駆動でスペースが制約される環境におけるデータ・アグリゲーション通信は、特に複数のデバイスの同期が必要なシステムにおいて、特有の課題を引き起こします。GOWINのGW1NZ FPGAデバイスは、シームレスなデータ・アグリゲーションを実装するために、超低消費電力、コンパクトなフォーム・ファクタ、および多彩な機能を提供する革新的なソリューションを提供します。このホワイトペーパーでは、これらの課題に対処するためのGW1NZ FPGAデバイスの機能、アプリケーション、および利点について解説します。   2  はじめに   多くのアプリケーションでは、複数のサブシステムにまたがる複数のセンサーと同期する必要があります。通常、それぞれのサブシステムは独自のボードに搭載されています。これらのセンサーからのデータを収集し、それをベースシステムまたはメインSOCに統合する必要があります。同時に、ベースシステムまたはメインSOCは、これらのサブシステムに対してコマンドを送信したり、パラメータを設定したりする必要があります。これらの通信は通常、I2C、UART、SPIなどの低速プロトコルを使用し、システム内でサイドバンド通信チャネルとして機能します。従来の手法では、プロトコルに基づいているだけで、その結果、ベースシステムとサブシステム間で多くのワイヤが使用されてしまいます。 データ・アグリゲーションとは、異なるソースからの情報を統合するプロセスを指します。この手法により、通信システム間の多くの物理ネットワーク接続が最小限に抑えられます。アグリゲーション・データは、個々のデータを組み合わせて取得される上位レベルのデータです。低速なデータをまとめ、アグリゲーション・データを高速なチャネルを介して送信することで、ベースシステムとサブシステム間の配線の数を効果的に削減できます。これにより、冗長なデータが減り、システムの消費電力も削減されます。サーバーアプリケーション用のOCP DC-SCMプロジェクトは、その好例です。 限られたスペース内でバッテリー駆動でデータをアグリゲートする必要がある場合、従来のソリューションでは電力やスペースの制約により問題が生じることがよくあります。これらのアプリケーションには、AR/VRデバイスやスマートグラス、携帯電話など、様々なウェアラブルやポータブルデバイスが含まれます。GOWINのGW1NZ FPGAデバイスは、独自の機能と能力によってこれらの課題に立ち向かう先駆的なソリューションとして際立っています。.   3  GW1NZデバイスの特長   超低消費電力：GW1NZデバイスの優れた特長は、その極めて低い電力消費にあります。たったの28μWの待機電力と10mW未満の動作電力は、低消費電力が求められるバッテリー駆動のアプリケーションに最適です。   コスト効率性：大量購入の場合には1個あたり0.5ドルを下回る可能性があり、GW1NZデバイスは高い性能や機能を犠牲にすることなく、費用対効果の高いソリューションを提供します。   コンパクトなフォームファクタ：1.8mm x 1.8mmという極めて小型な寸法を誇るGW1NZデバイスは、優れた柔軟性と統合性を提供し、ハンドヘルド、ポータブル、ウェアラブルデバイスに最適です。   インスタントオン機能：LittleBeeファミリーのFlashベースのFPGAテクノロジーを備えたGW1NZは、シームレスなデータ同期とリアルタイム操作に不可欠なインスタント・アクティベーションを保証します。   柔軟なアップグレードオプション：GoConfig IPを活用することで、バックグラウンドプログラミングが可能となり、現地でのアップグレードが容易になり、適応性と将来性が保証されます。   製品情報一覧   リソース GW1NZ-1 GW1NZ-2 LUT4 1152 2304 フリップフロップ 864 2304 分散SRAM(SSRAM)の容量(ビット) 4K 18K ブロックSRAM(BSRAM)の容量(ビット) 72K 72K BSRAMの数 4 4 User Flash(ビット) 64K 96K PLLs 1 1 最大GPIO数 48 125 コア電圧(ZVバージョン) 0.9V/1.0V 0.9V/1.0V コア電圧(LVバージョン) 1.2V 1.2V    各パッケージの最大ユーザーI/O数、(True LVDSのペア数)   パッケージ ピッチ (mm) サイズ (mm) GW1NZ-1 GW1NZ-2 識別子 CG25 0.35 1.8 x 1.8 20 -   CS100H 0.4 4 x 4 - 88(27) H CS16 0.4 1.8 x 1.8 11 -   FN24 0.4 3 x 3 18 -   FN32 0.4 4 x 4 25 -   FN32F 0.4 4 x 4 25 - F QN48 0.4 6 x 6 41 41(12)     4  代表的な市場とアプリケーション   GW1NZデバイスはその多様な利用可能性により、様々な分野で活躍できます。   バッテリー駆動アプリケーション：GW1NZデバイスは超低消費電力であるため、バッテリー電源に頼るデバイスに最適です。これにより、性能を損なわずに長時間の動作が保証されます。   大量消費型家電製品：費用対効果が高いGW1NZデバイスは、大量消費型家電製品にとって機能性と手頃な価格のバランスが取れた魅力的な選択肢となります。   ンドヘルド、ポータブル、ウェアラブルデバイス：GW1NZデバイスは、フォームファクタが小さく、ハンドヘルド機器、ポータブル機器、ウェアラブル機器にシームレスに統合できるため、フットプリントが小さいデバイスにとって最適となります。   同期デバイスを必要とするシステム：複数のカメラやディスプレイ間の同期を必要とするアプリケーションは、GW1NZデバイスの機能を活用することで、システム全体のスムーズなデータ・アグリゲーションを実現できます。     5  実例   以下の図は、ポータブル機器システムを説明したものです。     このようなシステムの性能と消費電力を以下に示します。 デバイス GW1NZ-LV2CS100HC6 Master FPGAのリソース使用率 78% 周波数: 32KHz Slave FPGAのリソース使用率 56% 周波数: 32KHz 総消費電力 Master FPGAおよびSlave FPGA(VCCIO+VCCX+VCC): 3.261mW   デバイス GW1NZ-LV2CS100HC6 Master FPGAのリソース使用率 78% 周波数: 19.2MHz Slave FPGAのリソース使用率 55% 周波数: 19.2MHz 総消費電力 Master FPGAおよびSlave FPGA(VCCIO+VCCX+VCC): 7.9744mW   6  独自の利点と市場での位置付け   GOWINのGW1NZデバイスは、市場で強力な競争力を誇っています。   細い制御ワイヤ向けに最適化された設計：これらのFPGAは、特に分割画面にわたる細い制御ワイヤが必要なシナリオで、複雑な信号伝送を効率的に処理し、サイズを犠牲にすることなく信頼性のあるデータ・アグリゲーションを確実にします。   低消費電力と高性能で業界をリード：GW1NZデバイスは、携帯電話メーカーが効率的なデータ・アグリゲーションの解決策を模索する時代において、低コスト、コンパクトなサイズ、低消費電力、高性能により、競合他社をしのぎ、ASICや他のFPGA製品を凌駕する可能性さえあります。   複数のアプリケーションにおける多用途性：GW1NZデバイスの適応性は、携帯電話に限らず、他のマルチスクリーンデバイスでの潜在的な利用も考えられ、それが広範な市場適用性を示しています。   ゼロ電力デバイスと適応電力モード：特に、GOWINのゼロ電力デバイスと複数の電圧サポートにより、これらのFPGAはOpalデバイスのようなフルパワーの常時オン機能に優れつつ、休止モード動作にも適しています。   GOWINのGW1NZ FPGAは、バッテリー駆動でスペースが制約された環境におけるデータ・アグリゲーションの包括的な解決策を提供します。低消費電力、高いコスト効率性、コンパクトなフォームファクタ、高性能の卓越した組み合わせにより、シームレスなデータ同期とアグリゲーションを必要とするさまざまなアプリケーションにおいて主要な選択肢としての地位を確立しています。   7  結論   GW1NZ FPGAは、データ・アグリゲーションがバッテリー駆動のウェアラブルシステムやハンドヘルドシステムで不可欠な厳しい状況に最適な解決策となっています。さらに、これらのデバイスが低電力レベルで動作する適応性は、さまざまな用途に対する適性を一層高めています。 GW1NZシリーズFPGAは、55nmおよび同等のプロセス(40nm、45nm、65nm)で0.9V Vccをサポートする唯一のFPGAです。CS100HやCS42などのカスタマイズされたパッケージは、さまざまなシステムの複雑さに対応し、消費電力、コスト、サイズを削減した拡張可能なソリューションを提供しています。  

はじめに   フィールド・プログラマブル・ゲート・アレイ(FPGA)は今日の電子機器分野に不可欠 であり、比類のない柔軟性とコンフィギュアビリティを提供します。ただし、FPGA の コンフィギュレーションはSRAM に依存しているため、SEU が発生しやすくなります。本稿では、FPGA におけるSEU について検討し、SEU を防止しなければならない理 由と、SEU を迅速に修正することの重要性を明らかにします。   シングル・イベント・アップセットを理解する   a. SRAM セル: FPGA の心臓部   SRAM セルはFPGA の制御センターであり、FPGA の動作を制御するビットストリー ムを保存します。SRAM セルの状態が変化すると、致命的な機能障害が発生する可能 性があり、したがって、SEU は重大な懸念事項となります。   b. トランジスタ縮小とSEU   SRAM セルは古いテクノロジーを使用することが多いですが、ダイ面積を節約するた めにトランジスタのサイズが縮小するにつれて、SEU の影響を受けやすくなります。 このサイズの縮小により、データを保持する能力が低下し、特に航空宇宙用途において 、さまざまな外部要因に対して脆弱になります。   c. 宇宙線と地表   通常、宇宙線は地球の大気中で無害に消散し、地表居住者にはほとんど脅威を与えませ ん。しかし、SRAM セルのトランジスタサイズの縮小に り、宇宙線が減少しても SEU が発生し、FPGA の故障につながることが懸念されています。   d. 対象となる粒子   SEU を引き起こす2 つの主要な粒子は、中性子(宇宙線を模倣)とアルファ粒子で、通常 はパッケージ内のはんだボールから放出されます。材料を変更することは可能ですが、 多くの場合、SEU を効果的に処理する方が経済的です。   GOWIN FPGA ソリューションの利点   a. SRAM セルの強化   SEU の防止は、SRAM セルを強化することから始まります。GOWIN の革新的なアプ ローチには、カスタムSRAM セルの設計とその耐久性の強化が含まれます。この措置 により、22nm Arora V のような小さなダイサイズであっても、SEU 耐性が大幅に向上 します。 22nm BSRAM は依然としてTSMC によって製造されており、そのSER レポートには 顕著な違いがあります。ユーザーがBSRAM の内容を読み出すときにBSRAM のSEU エラーを修正できるように、ハードECC 回路が用意されています。   b. パフォーマンスの比較   GOWIN の22nm FPGA を競合他社(例えば、X 社)の28nm 6 および7 シリーズと比較 すると、GOWIN FPGA の優れたSEU 耐性が明らかになります。包括的なテストデー タにより、このパフォーマンス上の優位性が強調されます。   c. 管理されたテスト   SEU の耐久性を定量化するには、中性子およびアルファ粒子照射による制御されたテ ストが不可欠です。GOWIN の故障率データは、SEU に対する強力な保護を示し、競合 他社や前世代のFPGA を上回っています。以下は、TSMC 55nm GP プロセスによる GOWIN のGW2A 55nm コンフィギュレーションSRAM セルとの比較です。     迅速な誤り訂正   a. 誤り訂正の重要性   ミッションクリティカルなアプリケーションでは、誤り(エラー)訂正が最も重要です。 GOWIN は、データエラーを検出して訂正できるハミングコードベースの誤り訂正シス テムを採用しています。   b. 誤り訂正の比較   GOWIN のエラー訂正アルゴリズムはX 社と比べて優れています。X 社は1 フレーム内 の、シングルビット・エラーまたはダブルビット(隣接)エラー（拡張修復法）しか訂正 できませんが、GOWIN のGW5A はより多くのタイプ（1 フレーム内の異なる位置での、 2 ビット・エラーまたはマルチビット・エラー）を訂正し、訂正不可能なマルチビッ ト・エラーを報告することができ、システムの信頼性を高めています。   c. 効率的なフレームサイズ   GOWIN のFPGA フレームは効率を重視して設計されており、X 社のものと比較してフ レームあたりのビット数が大幅に少なくなります。フレームサイズが小さいため、複数 ビットエラーのリスクが軽減されます。 フレーム サイズに関する詳細情報: 138K：フレーム長：1,513 ビット 25k：フレーム長：469 ビット 60k：フレーム長：918 ビット 比較として、X 社の7 シリーズのフレーム長は3,232 ビットです   d. 専用Parabit   GOWIN は、SRAM フレーム内に専用のParabit を統合することでエラー訂正を簡素化 し、ファブリック機能は検出および訂正操作に関与しません。GOWIN は、ユーザーが SEU レポートおよび訂正機能に簡単にアクセスできるようにする、シンプルなラッパ ーIP の“SEU Handler”を提供します。このアプローチにより、信頼性と効率が向上しま す。   e. カスタマイズ可能なスキャン周波数   GOWIN のFPGA ソリューションは、カスタマイズ可能なスキャン周波数を提供するこ とにより、より高速なエラー検出と訂正を可能にし、これは特にクリティカルなサーバ ー環境での中断のない動作にとって重要です。アドバンスト・モードでは、スキャン周 波数は最大200MHz です。   効率と統合   GOWIN のFPGA ソリューションは、SEU 軽減機能をハードウェアに統合することで 、お客様による導入を簡素化します。このアプローチにより、効率的で信頼性の高い動 作が保証されます。   GOWIN 22nm FPGA SER テストレポート   a. テストの背景:   GOWIN のFPGA デバイスがSRAM ベースであるため、ユーザーロジックは内部のコ ンフィギュレーションSRAM セルによってプログラムおよび制御されます。アルファ 粒子または中性子粒子によって引き起こされるSRAM セルのシングル・イベント・ア ップセットは業界でよく理解されており、ミッションクリティカル、機能安全性、およ び高信頼性アプリケーションのシステム故障率の計算で考慮する必要があります。   b. テスト済みのSRAM:   SRAM セルの数はビットストリーム・ファイルから取得できます。ビットストリー ム・ファイルには、FPGA SRAM セルアレイにプログラムするために必要なすべての データが含まれています。したがって、アレイのサイズからSRAM セルの数を取得で きるはずです。このようなアレイには2 種類のSRAM セルが含まれています。1 つは コンフィギュレーションSRAM、もう1 つはブロックSRAM で、ブロックSRAM はロ ジック制御用ではなく、ユーザーデザインのメモリストレージとして使用されます。表 1 および表2 は、コンフィギュレーションSRAM およびブロックSRAM として使用さ れるメモリセルに影響を与えるシングル・イベント・アップセット(SEU)によって引き 起こされるソフト・エラー率を示しています。   c. テスト方法   中性子の断面積は、JESD89/6 加速高エネルギー中性子テスト手順に従ってCSNS ビー ムテストから決定され、熱中性子の断面積はJESD89/7 加速熱中性子テスト手順に従っ て決定されます。中性子ソフト・エラー率(FIT/Mb 単位)はニューヨーク市に対して訂 正されています。アルファ粒子の断面積は、JESD89/5 加速アルファ粒子テスト手順に 従ってアルファ線源としてのアメリシウム241 源によって決定され、アルファ粒子の ソフト・エラー率(FIT/Mb 単位)はアルファ放射率0.001 カウント/cm2/ 基づいて訂正 されます。   d. コンフィギュレーションSRAM のソフト・エラー率   以下の表2 は、コンフィギュレーションSRAM として使用されるメモリセルに影響を 与えるシングル・イベント・アップセット(SEU)によって引き起こされるソフト・エラ ー率を示しています。     e. ブロックSRAM のソフト・エラー率   以下の表3 は、ブロックSRAM として使用されるメモリセルに影響を与えるSEU によ って引き起こされるソフト・エラー率を示しています。     f. コンフィギュレーションSRAM のECC   GOWIN の22nm FPGA はECC 機能を提供し、ECC 機能の能力を検証するために実験 グループが設立されました。同じフラックス実験条件下で、SRAM リードバック周波 数が15MHz、リードバックと比較期間が44610us である場合に、リードバックプロセ ス中にSEU が観察されます。このプロセスでは、MBU が見つからなく、SBU が観察 されました。観察されたすべてのSBU はECC 回路によって訂正され、デバイスが正 常に動作できるようにビットストリーム全体が維持されています。   結論   GOWIN のGW5AT およびGW5A シリーズのFPGA は、SEU の防止と訂正に優れてお り、X 社などの競合他社を上回っています。強化されたSRAM セル、効率的な誤り訂 正、専用のParabits を備えたGOWIN は、ミッションクリティカルなアプリケーショ ン向けに、より信頼性が高く効率的なソリューションを提供します。当社のFPGA ソ リューションにより、お客様は最も困難な環境であっても、自信を持って堅牢なシステ ムを導入できるようになります。  

EasyCDR® - お客様の特定ニーズに合わせたカスタムソリューション   White Paper   Table of Contents SerDes の紹介 GPIO によるGowin EasyCDR®ベースのSerDes EasyCDR®ソリューションの利点 アプリケーション例 産業用フィールドバスにおける潜在的なアプリケーション 7:1 LVDS MIPI M-PHY LVDS バスアプリケーション 結論     1. SerDes の紹介 SerDes は、シリアライザ（Serializer）とデシリアライザ（Deserializer）の言葉を組み合わせたものです。同軸ケーブルまたはツイストペア・ケーブルを介して大量の情報を転送できます。今日の世界では、より高速なデータ転送が求められており、並列データ・フローでは対応できません。SerDes テクノロジーは、50Ω同軸または100Ωツイストペア・インターフェースのいずれかで使用できます。場合によっては、同軸ケーブルで電力を供給すること(POC)が可能で、これはカメラへの電力供給に最適です。 クロックを使用せずに1 本のケーブル（銅線またはファイバー）でデータ転送を可能にする重要なテクノロジーは、クロック・データ・リカバリ(CDR)と呼ばれます。データをケーブルに送信する際、データはソースからクロックに同期して送信されていますが、クロック信号は送信されません。その代わりに、データ・ストリームには、エンベデッド・クロックと呼ばれる、データ遷移によって示されるクロック情報が含まれています。重要なのは、受信側がCDR テクノロジーによってこのデータ・ストリームからクロック情報を回復し、正確なタイミングでデータを取得することです。一般的なアプローチは、送信機能とともに専用のアナログベースのCDRシステムを構築し、SerDes 機能全体を実現することです。   2. GPIO によるGowin EasyCDR®ベースのSerDes Easy Clock Data Recovery(EasyCDR®)は、複雑さ、消費電力、コストを大幅に削減しながら、データ受信プロセスを簡素化するように設計された画期的なテクノロジーです。GOWIN の新しいGW5Aシリーズには、クロック信号が埋め込まれたシリアル・データを受信できる高度なI/O 構造が実装されています。当社の新しいEasyCDR® IP は、シリアル入力データをデシリアライズして、10 ビットまたは16 ビットのパラレル・データとクロックを出力できます。このソリューションは完全にGPIO およびFPGA ファブリックにより実装されており、専用のアナログSerDes は必要ありません。   GOWIN は、GW5A シリーズFPGA で最大2.5Gbps の優れたパフォーマンスを備えているEasyCDR®機能を提供します。そのシンプルさと効率性により、EasyCDR®は、消費電力が高く、複雑で、高価になりがちなアナログSerDes ソリューションに代わる優れた選択肢となります。   下図は、SerDes のRx 機能として動作するEasyCDR®を示しています。     3. EasyCDR®ソリューションの利点 速度要件が2.5Gbps 未満のアプリケーションでは、GOWIN のEasyCDR®ソリューションは、従来のアナログSerDes ソリューションに代わる最新かつ効率的な代替品として際立っています。GOWIN のEasyCDR®の利点は次のとおりです。   a. 多用途性EasyCDR®ソリューションは、専用のアナログSerDes ブロックではなく、FPGA の一般的なリソースに基づいているため、柔軟性と汎用性が高くなります。高速トランシーバーが利用できるかどうかに関係なく、すべてのArora V デバイスで実装できます。ユーザーは、SerDes プロトコルを簡単に実装して、さまざまな状況に適応できます。したがって、この機能は、多くの最新の電子設計にとって大きな価値があります。   b. コストと電力効率アナログSerDes ブロックは高価であり、大量の電力を消費します。これが、一部のFPGA にトランシーバーがわずかしかないか、まったくSerDes ブロックがない理由です。一方で、GPIO の数は十分であり、消費電力と実装コストも低いです。EasyCDR®はFPGA のGPIO およびロジック・リソースを利用するため、コストと電力の効率を高めています。 c. 技術進歩の隙間を埋める今日の世界では、AI やスマートフォンなどの先端技術により、ウエハ・プロセス技術が急速に進歩しています。一方で、数十年前に定義されたテクノロジーは今でも広く使用されています。たとえば、USB2.0 は2000 年に導入され、現在でも多数のUSB2.0 デバイスが出荷されています。GPIO の速度は、現在ではUSB2.0 の480Mbps を軽く超えることができるため、このような低速プロトコルをサポートするために最新のテクノロジーで新規に設計することはまったく意味がありませんが、これは従来のFPGA GPIO でサポートできないSerDes ベースのプロトコルです。EasyCDR®テクノロジーは、このギャップを埋めました。 d. データ処理能力の向上より多くのアプリケーションをサポートするために、速度の範囲を拡張することが重要です。EasyCDR®は最大2.5Gbps を処理できるため、競合他社とは一線を画しています。多くのユーザー・ケースはすでにこの速度で満足できます。   4. アプリケーション例 a. 産業用フィールドバスにおける潜在的なアプリケーション産業用フィールドバスにおけるアプリケーションは、産業分野において、機器、コントローラ、アクチュエータ、フィールドデバイス間のデジタル通信に不可欠です。GOWIN のEasyCDR®は、PROFIBUS、PROFINET、SERCOS、Modbus、EtherCAT などの標準を含む、フィールド制御機器と高度な制御システムの間のデータ交換を処理するフィールド・バス・システムに応用可能です。     特にEtherCAT は、EtherCAT G(1Gbit/s)やEtherCAT G10(10 Gbit/s)などの高速データ・レートをサポートするように進化しました。EasyCDR®は、このような高速データ変換アプリケーションの処理において重要な役割を果たし、信頼性や費用対効果が高いソリューションを提供します。    b. 7:1 LVDS 7:1 LVDS は、LCD パネルの駆動信号の接続によく使用されます。EasyCDR®はデータ・レート要件を満たすことができますが、同期のためにはデータに遷移が必要です。これを解決するためには、8B10B エンコーディングやスクランブリングなどの手法が必要となる場合があります。ただし、eDP やV-by-One などのエンベデッドクロックを持つインターフェースが普及するにつれて、7:1 LVDSインターフェースの市場が縮小していることには注意が必要です。   c. MIPI M-PHY MIPI M-PHY はPWM 信号とEasyCDR®を使用します。エッジベースであるため、クロックを効果的に回復できます。MIPI M-PHY に同期機能を提供し、クロック・レートがデータ・レートの3 倍の場合でも信頼性の高いデータ受信を保証します。     d. LVDS バスアプリケーション LVDS バスアプリケーションでは、EasyCDR®は追加のクロック信号なしでデータ送信を可能にすることで接続を簡素化します。GOWIN のGW5A およびGW5AR デバイスは、強化された最大2Gbps の受信速度を提供します。この機能は、産業環境におけるより高いデータ転送要件に答えるために極めて重要です。     5. 結論 GOWIN のEasyCDR®は、利用可能な速度範囲で従来のアナログSerDes オプションを上回る、データ受信のための最先端ソリューションです。技術の進歩、より高いデータ処理能力、高い電力/コスト効率、および多用途性などの利点を備えたEasyCDR®は、産業用フィールドバス、LVDS インターフェース、MIPI M-PHY などのさまざまなアプリケーションに優れた選択肢を提供します。業界がより高速で効率的なデータ受信ソリューションを求め続ける中、EasyCDR®はこれらの課題に対応する準備ができており、電子システムの設計を簡素化し、コストを削減する方法を提供しています。   Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.   Gowin, GOWIN, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.   Disclaimer   GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

IoT has introduced a large variety of devices that have their own unique system attributes.  According to a 2018 Ericsson Mobility Report， 1B cellular IoT connections were made in 2018, which is expected to grow to 3.5B connections by 2023.  Most of these unique IoT hardware systems have brought a new generation of security threats.  These threats now provide attackers access to more than just data – they provide localized control and monitoring of devices directly in the public environment which, if compromised, can jeopardize the safety of an individual or even the global.   Product security has vulnerability at all stages of production and procurement.  At the component level, devices can be compromised in the factory during testing, handling or shipment.  At the board level, modifications and vulnerabilities can be found during end product development, testing or manufacturing.  After the connected product is manufactured, the device is susceptible to reverse engineering, hacking and cloning. All of these situations may lead to critical data being accessed, monitored or controlled.    In order to avoid these issues, one or more IC devices in the system need to establish a Root of Trust or RoT. These devices provide cryptographic capabilities to the system, which can be used for securely booting and authenticating firmware, generating or verifying keys, certificates and signatures, and encrypting or decrypting data.   The RoT device provides security capabilities to the rest of the system through a Chain of Trust.  As a result, it is the most critical device in the system from a security perspective since the entire system is vulnerable if it is compromised.  Evaluating the entire lifecycle of the RoT device from semiconductor manufacturing to product is important as a result.   Encryption functions use key pairs to identify and verify system functions.  Semiconductor manufacturers that produce IOT need to be able to establish a root key that matches the private key inside the IOT device, and the private key is inaccessible and never can leave the device.  If the private key is accessible in manufacturing, that device could be susceptible to cloning or hacking.  Additionally, if the private key is stored in the device’s flash or fuses, the key may be susceptible to retrieval in manufacturing or reverse in the design.   To solve these two problems, RoT devices should use a Physically Unclonable Function or SRAM PUF, which uses the intrinsic properties of an element in silicon as a truly random identifier.  This identifier can then be used to generate key pairs when the device powers up rather than storing it in a particular area which could potentially be reversed.  Additionally, to prevent cloning a certificate for the RoT, device should be issued on the manufacturing floor.  This certificate should have a signature based on the root key pair within the encrypted engine of the device.  With a signature from the manufacturer of the device as the certificate authority, the device can be validated as genuine to the system ensuring that the RoT device itself is not a clone.   Compliance to standards is also important to ensure that security elements in the RoT device are compatible with the rest of the system.  As a result, in addition to complying with the standards set by the National Institute of Standards and Technology, SP 800-90 compliance for random number generation and SP 800 193 for Platform Firmware Resiliency or PFR are important factors for both security and compatibility.   Security and RoT Device Options   Historically, there have been two options for security devices in a given system: MCU and FPGA.  Both of these systems have advantages and disadvantages.  MCU has the advantage of ease of use, and it is much easier to license libraries and APIs that are more easily transplanted from one device to another.  A good example of this would be something like FreeRTOS and MBED TLS, which has become widely used for embedded IoT systems to gain TCP/IP and TLS/SSL.  One disadvantage to the MCU is IO available, which can cause limitations to the number of interfaces needed to provide security features over the entire system.  Another disadvantage is the MCU’s ability to check its own boot memory during runtime.    FPGA has a large number of IOs, low latency and the ability to check system components in parallel. A large number of IOs allows you to control and monitor more components in the system, low latency allows you to check system components faster, and parallel computing allows you to faster check the overall system.  However, its main disadvantage is that it is not as easy to use as MCU.  For example, enabling TCP/IP and SSL stacks in the FPGA without a processor and significant memory would be extremely challenging and likely not a priority for the OEM.   Ultimately, the ideal device would integrate security features into devices with both an MCU and FPGA fabric at a low cost and lower power.  It would also have the right packaging needed for an array of applications from edge devices to the Server.  This would provide the advantages of both historical options and optimize the system based what’s required.  Fast power up and parallel checking can be achieved by taking advantage of the FPGA fabric, while the MCU’s ease of use and library integration can enable faster development time.   Gowin SecureFPGATM – Secure µSoC FPGA for RoT in Edge, IoT and Server Systems   The latest innovation in RoT device security is Gowin SecureFPGATM, which combines the advantages of the MCU and FPGA with the security functions needed for edge, IoT and Server applications.  SecureFPGA provides a security library based on SRAM PUF technology with Gowin genuine device authentication designed to eliminate attacks from the factory floor to the daily use of the end product.   The device has a wide range of packaging including BGA, QFN and TQFP to meet the needs of IoT and Server applications. There are different IoT packages. Server packaging is available such as QFN, BGA and TQFP depending on the application.     Full-Featured Security Library   Gowin SecureFPGATM intends to solve and eliminate issues with current security devices by providing a full-featured security library along with a secure component based on SRAM PUF technology and Elliptic Curve Cryptography or ECC. Additionally, Gowin has cooperated with Intrinsic ID to offer the BroadKey-Pro security library. Developers can use encryption tools to create a RoT for applications in Gowin SecureFPGA devices, or use proven and mature security solutions to provide a RoT for multi-device systems   Figure 1 GW1N-9C SecureFPGATM Device   Gowin SecureFPGATM Security Capabilities     Bitstream Lock - Removes the possibility of off-chip reading device bitstream Factory Provisioning - Activates code, UUID, CSR and Certificate Internal Dual Boot Flash - Online and remote upgradable with firmware signature checking SRAM PUF - Root devices keys generated at powerup; never stored in Flash UUID - Unique Device Identifier signed with the SRAM PUF root key pair Device Certificate - Validates device as a genuine Gowin device signed with SRAM PUF root key pair ECDH Encryption/decryption - AES128/192/256 Engine based on ECC Key Pair codes; SRAM PUF device unique or random. Asymmetric key pair generation - Based on SRAM PUF device, unique or random. ECDH Symmetric key generation - Based on SRAM PUF device, unique or random. ECDSA Signature - Generation and Verification Random Number Generator - Based on SRAM PUF and AES   Security Solution Maturity, Compliance, and Certificates   GOWINSEMI has cooperated with Intrinsic ID to offer the BroadKeyPro security library within Gowin SecureFPGA devices.  Intrinsic ID provides one of the most mature SRAM PUF technology solutions in the industry and has been adopted by many semiconductor device providers.     It has been recognized in the industry for several years and recently was named IoT Security Product of the Year in the 2019 IoT Breakthrough Awards. It has been shipped into over 125 Million IoT devices, and meets the requirements of FIPS 140-2 Appendix B and China’s OSCCA standards.  Lastly, it has been deployed in everything from banks to banks, setting a high standard for security in RoT capable devices. The certificates include EMVCo, Visa, and CC EAL6+.   Typical Applications Secure Boot and Secure Software Update Secure boot is the process of hashing and generating a signature using a key and then verifying it versus a signature created at an earlier time, then the device can check whether the firmware has been tampered  before executing it.    Figure 2 Secure Boot   For embedded applications, the secure boot starts by generating a signature over the firmware using the private key of a key pair. This signature is stored in the device for comparison at runtime. Once a signature is generated and stored, a small set of boot code can generate a signature using the public key and verify it versus the signature previously generated and stored in the device.   Figure 3 SecureFPGATM - Secure Boot Preparation   Figure 4 SecureFPGATM - Secure Boot Verification   It also can be applied for verifying firmware for multiple devices on a server.  Each firmware has a signature generated by the private key of the pair. Then at power up, Gowin SecureFPGA validates signatures of each firmware for each device.   Figure 5 Gowin SecureFPGATM for Secure Boot in Server Applications     In addition to device secure boot and server secure boot applications, it also can be used for secure firmware updating.  In this case, firmware is signed by the source and sent to a device over some medium such as the web or a cable.  The device can then use the public key to verify the firmware before switching to it or retain the use of its base image.   Figure 6 Secure Firmware Update   Data Encryption   There are many applications that have a need for encrypting data.  For example, a device can individually encrypt or decrypt data or firmware in its flash or ram so plaintext is never stored.  Another scenario is that a device can exchange encrypted or decrypted data with another device with exchanged keys so that the data will not be leaked during transmission.   Figure 7 Gowin SecureFPGATM Internal Device Encryption/Decryption Flow   Figure 8 Gowin SecureFPGATM Device to Device Encryption/Decryption Flow   Manufacturing    To ensure security over the entire manufacturing process, GOWINSEMI has special SecureFPGA equipment. SecureFPGAs are provided with an activation code during test time, which enables the device to always generate the same root key pair. The root private key that is generated with the SRAM PUF engine is never exposed to the user or outside the device.  It is only available to security functions in the device and called by the user through key codes.  During configuration, the root public key is exported from the device.  A Certificate Signing Request or CSR and UUID for the device are formed, which can be used with a third party CA.  Optionally, Gowin provides a Certificate Authority (CA) service to generate the certificate for each device in the factory.  Gowin CA service provides the ability to confirm a device is genuine by validating the devices unique certificate or repudiating; if not genuine, please contact Gowin technical support. These features provide assurance that the device has a unique identity; it is genuine and does not contain content in flash that may be vulnerable to be attacked from factory floor to end of product life.   Conclusion   Gowin SecureFPGA products provide a Root of Trust based on SRAM PUF technology. These devices are virtually impossible to duplicate, clone or predict. This makes them very suitable for applications such as secure key generation and storage, device authentication, flexible key provisioning and chip asset management.  Each device is provided with a unique key pair that is never exposed outside the device or during device development or manufacturing. The Intrinsic ID BroadKey-Pro security library is provided with Gowin SecureFPGA devices, allowing easy integration of common security features into user applications. Gowin SecureFPGA is used widely for a variety of applications such as consumer,  industrial IoT, edge, and server management.    Related Material     Columbus, Louis. “2018 Roundup Of Internet Of Things Forecasts And Market Estimates.” Forbes, Forbes Magazine, 18 Dec. 2018, www.forbes.com/sites/louiscolumbus/2018/12/13/2018-roundup-of-internetof-things-forecasts-and-market-estimates/#4b33a2747d83.   2. Lazich, Milan. “Intrinsic ID's BroadKey Named 'IoT Security Product of the Year' in 20.” PRWeb, 3 Jan. 2019, www.prweb.com/releases/intrinsic_ids_BroadKey_named_iot_security_product_of_the_year_in_2019_iot_breakthrough_awards/prweb16012275.htm.    Technical Support   Gowin Semiconductor provides customers with comprehensive technical support assistance. If you have any questions, comments, or suggestions, please feel free to contact us.   Website: www.gowinsemi.com E-mail: support@gowinsemi.com   Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.   GOWIN, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI..   Disclaimer   GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

The amount of responsibility given to and expected from edge devices is growing rapidly in all types of automotive, IoT, industrial, and consumer applications. Edge inference is becoming a common capability in these devices to provide localized decision making, reduced latency and cost reduction of connected nodes.   These solutions often struggle to meet the next set of customer demands on cost, power, size as well as the flexibility to adapt and integrate over time. Additionally, the heavy computational needs of neural networks often push beyond the performance of standard microcontrollers. They also struggle from meeting time to market pressure while being expected to incorporate the latest technology advancements.   Low density FPGAs can be used to address common customer constraints on cost, power and size by providing flexible and scalable solutions dependent on the network size.    GOWIN FPGA’s specifically address this by providing scalable device densities from 1k to 55K LUTs in variety of wafer level, QFN, and BGA package options as small as 3.24mm2 on both low power and high performance process technologies.     To improve performance and time to market of developing edge solutions for artificial intelligence GOWIN has created a new acceleration IP and solution suite called “GoAI” targeting their FPGA devices. The GoAI solution suite integrates GOWIN’s AI acceleration IP into existing machine learning frameworks to improve performance by over 78x compared to using a Cortex-M class microcontroller alone.     Usage of Edge AI in the System     Artificial intelligence at the edge is typically used for one of two purposes in a system. The first is to perform inference with devices that have no connectivity to the internet. These systems use machine learning to detect some information about an input and utilize it to control outputs of the system that are connected to it.       The second purpose is used to perform some pre-detection before sending data to the cloud for further processing. This can be done for various reasons such as saving power by shutting off the wireless transceiver or cost by only sending data to cloud AI services when some pre-detection has occurred.     Deploying AI at the Edge   Artificial intelligence today uses the machine learning techniques centered around convolutional neural networks. These networks are essentially sets of many filters or “neurons” with coefficients or weights that are trained to identify certain key attributes of an input. These weights are calculated through a process called “training” where a set of inputs are provided, the output is known and the weights are updated to identify it.   Training a convolutional neural network often consumes a significant amount of computational power. However, since it is only used to generate the weights to infer certain attributes about the input it generally does not need to run in real time. Once a network is trained the weights can be loaded into a network to detect attributes related to the input.  This inference often requires significantly less computing power than training.   While the computational power is significantly less for inferencing it often still exceeds the performance of microcontrollers. This is because microcontrollers process each computational instruction per processor clock cycle often in the sub-200Mhz range which is not enough performance to make detections of even small machine learning networks in real-time. Additionally, many use cases related to AI require specialized interfaces and buffering of data. For example, camera data often needs to be stored in RAM as a frame since filtering is performed over multiple pixels within the image at the same time.   Edge focused FPGAs address these problems easily. Parallel and pipelined computations of the network allow for real-time performance while operating the system more efficiently at 10’s of Mhz. Flexible interfacing allows the FPGA to connect to cameras, microphones, biometric sensors and other inputs easily. Configurable memories allow for buffering and retention of intermediate or layer data.   While FPGA’s provide a great avenue to make edge AI possible, a strong software stack is needed to make development and deployment easy. Modeling software for neural networks is available by several providers; Tensorflow, Caffe and Keras are common names.  These networks are often natively developed using floating point computations for training and testing by the software, which causes issues when attempting to deploy a cost and performance worthy solution at the edge.   As a result, common deployment tools such as Tensorflow Lite for microcontrollers and Arm CMSIS-NN use an optimization process to truncate and quantize trained weight data from floating point to 8-bit fixed point, making the resources more practical for edge focused hardware. However, the performance is often still significant and as result an accelerator design specifically to pipeline the convolutions and accumulations of layer data is common.  These accelerators can be designed in ASIC or FPGA to improve things further to real-time performance.     A System Example     To run through an entire development flow from model training to hardware design the GoAI platform was used to perform image detection on the CIFAR10 dataset. The performance of the GoAI accelerator was compared to an Arm Cortex-M microcontroller running the same network in CMISIS-NN. The CIFAR10 dataset is a common dataset of 10 classification objects used to measure various performance attributes of a machine learning system.   First, a network was trained for the system in Caffe. In this case, the network tested used three convolution layers with varying numbers of filters. After the network was trained, coefficients for weights and bias were obtained and the trained network was tested in Caffe over various inputs to ensure it behaved as expected.   After that the weight and bias coefficients were truncated and quantized using script utilities and the network was compiled to use CMISIS-NN function calls on an ARM Cortex-M1 and M3 processor. The optimized network was then deployed on the ARM Cortex-M1 processor with a camera interface and frame buffer connected to the AHB bus. The neural network took approximately 10 seconds to process one image from the camera.   Next, the GoAI accelerator was connected to the AHB bus and used to process the network. The Cortex-M1 was still used to pass image data initially to the accelerator, load weights and bias and configure the accelerator settings. The neural network took approximately 0.5 seconds to process using the GoAI accelerator with delays primarily associated with the results sent over UART.     Further analysis was performed on the Arm Cortex-M3 processor and the accelerator.  The difference between using the Arm Cortex-M3 processor by standalone versus with the GoAI accelerator showed an ~78x performance improvement.   GoAI 2.0     GoAI 2.0 focuses on: Integration of the FPGA accelerator with TensorFlow and TensorFlow Lite Targeting the GOWIN GW1NSR-4C uSoC FPGA with Cortex-M3 hard processor in 6x6mm QFN package Software compiling and deployment SDK’s Flexible architecture for supporting a variety of models with large number of layers and large layer depth   The GoAI 2.0 platform uses standard TensorFlow development environments to allow training and testing of any model. The final trained model then uses TFLiteConverter or TocoConverter to parse and quantize the model into a *.tflite flatbuffers file. The flatbuffers file is then parsed using the GoAI 2.0 SDK to extract model coefficients, layer parameters and model functions.   After extracting all the necessary information from the flatbuffers file, the GoAI 2.0 SDK loads coefficients to external SPI flash memory, C code to the embedded flash of the Cortex-M3 and bitstream to the FPGA in the GW1NSR-4C device or other supported GOWIN FPGA.     The architecture of the GoAI 2.0 platform allows for as deep of layers as there is PSRAM embedded in the GW1NSR-4C and as many convolution and pooling layers as there is memory to hold layer parameters. The GW1NSR4 has 8MB of PSRAM, which is split into a 4MB input layer buffer and 4MB output buffer layer. This means that a layer input and output can be up to 4MBs in size. The ITCM embedded flash within the Cortex-M3 is 32KB, which only needs to hold the control loop and the filter parameters for each layer. The external SPI flash holds the weight and bias coefficients for each layer and can be adjusted depending on the model size required.     Testing of the GoAI 2.0 platform was performed using Mobilenet v1.025 and the COCO dataset. Mobilenet is a fairly large convolutional neural network with 28 layers. 162ms inference latency was achieved using GoAI 2.0 with this model.     Conclusion   Various challenges arise while attempting to efficiently perform AI at the edge within a reasonable cost, power, size and time to market budget. Artificial intelligence at the edge is becoming increasingly important for both unconnected and connected devices. Edge AI solutions require an accelerator and complete software development flow to perform real time processing and integration into common machine learning model development software. GOWIN’s GoAI accelerator and software solution stack provides an ideal solution to address both performance and market environment constraints. 

Device connectivity at the edge has become a necessity. About 4 Billion devices in 2018 shipped with Bluetooth technology according to Bluetooth SIG, which is expected to continually grow at a compound annual growth rate of 12% over the next 10 years. This high continual growth is backed with new capabilities and use cases for the standard such as point of interest broadcasting, indoor navigation, transfer and recording of sensor and communication data, control, monitor and automation systems.   Most Bluetooth devices come in two forms. The first focuses on providing only a radio with an interface that can be controlled by a separate microprocessor. The second has a Bluetooth radio as well as a microcontroller in the same device that can be used for the Bluetooth stack as well as a limited amount user applications. These integrated solutions are often limited on what capabilities the microcontroller can offer as a result of specialized market needs.   Standalone Bluetooth Device   Intergrated Bluetooth Device   Additionally, both devices often lack flexible IO. For example, camera and display interfaces are rare at the microcontroller level and audio interfaces such as I2S may be extremely limited or non-existent. Sensor interfaces may be limited by the small number of IO available as well.     Performance can also be limited. Many times the processor in Bluetooth devices is limited to the lowest performance to save power. In cases, where the processor has more performance the power can be high for always-on use cases which require continual monitoring and control of the system such as data streaming or driving motors.   These deficiencies could be remedied by the benefits seen in edge focused FPGAs.  However, there is no FPGA to date with an integrated Bluetooth radio so a two-chip solution must be used. This has board area, cost and integration issues that the developer must be concerned about when developing a new product.   As a result, GOWIN Semiconductor has created the first FPGA with an integrated Bluetooth 5.0 Low Energy radio called the GW1NRF. This integration enables the flexible and high IO count, always-on low power, acceleration and pipelining capabilities of an FPGA with the wireless data transmission capabilities of a Bluetooth radio in a single chip.   GW1NRF High Level Block Diagram   Additionally, integration of several other key features has been developed within the GW1NRF device. The device features a 32-bit power optimized ARC processor, which can be used for both the Bluetooth stack as well as user applications. It also features a power management unit capable of various power modes as well as power gating, reducing the total power consumption of the device down to 5nA. Additionally, the device features a step up/step down regulator to better enable the entire device to operate off a 1.5V or 3.0V battery. Security features are also provided such as a random number generator, AES-128 and a key generator.    GW1NRF-4 Device Block Diagram   Use Cases   The GW1NRF is a completely new device which promotes the ability for end product manufactures to innovate in ways that were never before possible. As a result, some possible use cases are discussed to promote the unique capabilities the device has in order to stimulate new product ideas.   Camera to Bluetooth   Camera interfaces are often not available on most microcontrollers and Bluetooth devices. Flexible IO of FPGAs allows for many types of image sensors to be connected with interfaces such as parallel/single ended CMOS or a serialized MIPI CSI-2.     Audio hub to Bluetooth   Many microcontrollers and Bluetooth devices either do not have enough digital microphone interfaces such as I2S or PDM for microphone array applications. With the flexible FPGA IO interfacing many microphones along with data communication via Bluetooth becomes possible in a single chip.      Bluetooth to Motor Control    Motor control over Bluetooth can provide control of robotic and industrial equipment from battery powered devices such as a smartphone. Having FPGA resources and flexible FPGA IO promotes control of multiple motors over Bluetooth in a singular device.     Bluetooth to LED Control    Controlling multiple LED’s with FPGAs is common due to high current drive IO and IO count. Adding Bluetooth within the same device provides remote control of LED arrays along with adjustments for intensity, color and generation of sequencing patterns.     Conclusion   The need for connectivity at the edge with Bluetooth Low Energy is increasing.  Programmable heterogeneous computing needs are also increasing for machine learning, computer vision and embedded graphics use case. Integration of programmable capabilities along with SoC features is also increasing in need to meet new power, size and cost requirements. As a result, the Gowin GW1NRF4 provides new capabilities with embedded Bluetooth Low Energy to enable the next generation of embedded computing devices.