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企業情報
2014年に設立され、主要なR&Dを中国本社に置くGowinセミコンダクターは、当社のプログラマブル・ソリューションで世界的に顧客のイノベーションを加速するビジョンを持っています。当社は、プログラマブル・ロジック・デバイスで製品の最適化と利便性を実現することに焦点を当てます。当社の技術と品質へのこだわりにより、顧客はFPGAを量産ボードに使用することでトータルコストを削減できます。当社の製品には、プログラマブル・ロジック・デバイス、デザインソフトウェア、IPコア、リファレンスデザイン、および開発キットの幅広いポートフォリオが含まれています。当社はコンシューマ、インダストリアル、通信、医療、そしてオートモーティブ市場で世界中の顧客にサービスを提供することを目指しています。
製品

ARORA V:SRAMベースのFPGA ファミリー
GOWINセミコンダクターArora V FPGA製品は、SRAMベースのFPGAデバイスとして、豊富なリソースおよび向上したパフォーマンスを提供します。新しいアーキテクチャを備えたこのArora V FPGAは、AIコンピューティング対応の高性能DSP、高速LVDSインターフェース、豊富なBSRAMリソース、独自の研究開発によるDDR3、複数プロトコル対応の12.5Gbps SERDES、およびさまざまなパッケージタイプを提供し、低消費電力、高性能、および互換設計などのアプリケーションに最適です。
さらに、GOWINセミコンダクターは、合成、配置配線、ビットストリームファイルの生成およびダウンロードなどのワンストップサービスをサポートする、自社で研究開発した市場志向の新世代FPGAハードウェア開発環境を提供します。
さらに、GOWINセミコンダクターは、合成、配置配線、ビットストリームファイルの生成およびダウンロードなどのワンストップサービスをサポートする、自社で研究開発した市場志向の新世代FPGAハードウェア開発環境を提供します。

LITTLEBEE:FLASHベースのFPGA ファミリー
GOWINのLittleBee®製品ファミリーは、豊富なロジックリソース、複数のIO規格、組み込みRAM、DSP、PLL、組み込みセキュリティ、および追加のユーザーFlashを備えたFlashベースの不揮発性FPGAを提供します。インスタントオン、高IOカウント、高スループット、低レイテンシのプログラマブル コンピューティングが必要な低消費電力、低コスト、およびフットプリントの小さいアプリケーション向けに最適化されていますです。
その結果、LittleBee®ファミリーFPGAは、MIPI CSI-2、MIPI DSI、USB 2.0、イーサネット、HDMI、MIPI I3CなどのI/O集中型ソース同期インターフェースおよびブリッジング アプリケーションで業界をリードしています。
また、インスタントオン ブートと組み込みのセキュリティ機能を提供するハードウェア管理アプリケーションにも最適です。
LittleBee® ファミリーには、拡張メモリ、強化されたARM Cortex-Mプロセッサ コア、セキュリティ、Bluetooth LEなど、従来のFPGA製品と比較して機能と使用法を拡張する複数の革新的なサブ機能付き製品ラインがあります。
その結果、LittleBee®ファミリーFPGAは、MIPI CSI-2、MIPI DSI、USB 2.0、イーサネット、HDMI、MIPI I3CなどのI/O集中型ソース同期インターフェースおよびブリッジング アプリケーションで業界をリードしています。
また、インスタントオン ブートと組み込みのセキュリティ機能を提供するハードウェア管理アプリケーションにも最適です。
LittleBee® ファミリーには、拡張メモリ、強化されたARM Cortex-Mプロセッサ コア、セキュリティ、Bluetooth LEなど、従来のFPGA製品と比較して機能と使用法を拡張する複数の革新的なサブ機能付き製品ラインがあります。
マーケット

注目のソリューション
Open Logic now supports GOWIN
Open Logic open-source FPGA standard library now supports the GOWIN FPGA ecosystem. GOWIN support is not released just yet, check out the development branch to using it pre-release!
Follow along the GOWN Tutorial here:
Open Logic GOWIN Tutorial
The aim of this tutorial is give users a kick-start on creating Gowin projects using Open Logic.
The tutorial covers project setup and implementation up to the production of a running bitstream for a small design. The design is rather hardware independent but all examples and pinout constraints are given for a DK_START_GW1N-LV4LQ144C615_V1.1 evaluation board. If want to use it on some other hardware, just change pinout and the target device accordingly.
The steps should be very much independent of the GowinEDA version but all screenshots are taken with version 1.9.11.
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WHITE PAPERS

EOL REPLACEMENT GUIDE

製品ライフサイクル管理
通常、製品のライフサイクルは、導入期、成長期、成熟期、衰退期の4つの主要な段階に分けられます。
GOWINセミコンダクターは、初回の製品リリースから最低15年以上のライフサイクルをサポートすることを明確な意図として製品設計を行い、それを支えるサプライチェーンを構築します。GOWINセミコンダクターの部品は、長い運用寿命を必要とする多くのアプリケーションで広く使用されており、そのためGOWINセミコンダクターは製品のライフサイクルに対して強いコミットメントをしています。このコミットメントにより、最小ライフサイクルが15年であっても、顧客は多くの製品ファミリーがそれよりもずっと長くサポートされることを実感するでしょう。GOWINセミコンダクターの製品の寿命は、他の主要なFPGAサプライヤーと比較しても長いか、それ以上です。
最終オーダー(Last Time Buy)の場合、GOWIN セミコンダクターはJEDEC規格に準拠しています。

AIとエッジ コンピューティング
人間の知能のシミュレーションは、機械、特にコンピュータ システムによって処理されます。AIのアプリケーションとして、エキスパート システム、自然言語処理(NLP)、音声認識、およびマシン ビジョンなどが挙げられます。

通信
未来に接続。Gbpsイーサネットから5Gまで、GOWINは通信機器メーカーの製品化までの時間の要求を満たし、総所有コストを削減するために、低消費電力、高速インタフェース、および省スペースのFPGAの全製品ポートフォリオを提供します。

インダストリアル
スマートで、コネクテッド、そしてグリーン!インダストリー4.0では、マシンはインテリジェントで、コネクテッドで、そして省エネである必要があります。当社の低消費電力、エンべデッドDDR / SDRAMおよび高性能DSPなどの特徴を備えたGOWIN FPGAは...

オートモーティブ
インテリジェント、コネクテッド、そしてセーフ!スマートで安全な運転は今日のオートモーティブ市場の動向であり、高度運転支援システム(ADAS)はより多くの車内で接続されるセンサーを必要とします。Gowin FPGAは、スモールフォームファクタで豊富なIO数を提供します。

コンシューマ
Accelerate your Innovation!製品の差別化と製品化までの時間は、今日の競争の非常に激しいコンシューマ市場における重要な成功要因です。当社の既製IPソリューションを備えたGOWINの低コスト、高性能FPGAは、これらの要件に対する答えです。当社の...

医療
ビジュアル、ポータブル、そして信頼できる!医療機器や医療システムでは、MEMSやセンサー技術の発展とともに、半導体の含有量が増え続けています。画像センサのより高い解像度は...

LEDディスプレイ

クラウドコンピューティングとデータセンター
高性能とプログラマビリティ!新興のクラウドコンピューティング技術は、データセンター内のコンピューティングおよびストレージデバイスの高性能およびプログラマビリティを継続的に推進しています。それに対して...
ニュース

2024-11-29
GOWIN Semiconductor Introduces Educational EDA Version V1.9.10.03 with macOS Support
GOWIN Semiconductor Introduces Educational EDA Version V1.9.10.03 with macOS Support
San Jose, California, and Guangzhou, China — November 29, 2024
GOWIN Semiconductor Corporation, the world's fastest-growing FPGA company, is thrilled to announce the release of GOWIN Educational EDA Version V1.9.10.03, a significant update to its license-free software platform. Designed for students, educators, and hobbyists, the educational version allows users to dive into FPGA programming without the need for a licensing process.
In a groundbreaking first, this new version extends support to macOS, alongside Windows and Linux, making FPGA development accessible across all major operating systems.
"A lot of university students and hobbyists are starting their college journey using a Mac, and I think we will see more CS students graduating and using macOS in the real world," said Jason Zhu, CEO of GOWIN Semiconductor. "We want GOWIN to be accessible for everyone, and we're excited to extend macOS support to our full EDA in the near future."
GOWIN Educational EDA is tailored to remove barriers for entry-level users, offering reduced features in a lightweight, user-friendly environment. With macOS compatibility, GOWIN continues its mission to provide cutting-edge FPGA solutions that align with modern user needs.
For more information and to download the educational EDA, visit www.gowinsemi.com.
About GOWIN Semiconductor Corporation
Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide.
Copyright 2024 GOWIN Semiconductor Corp. GOWIN, LittleBee®, GW1N/NR/NS/1NSR/1NZ®, Arora®, Arora V®, GW2A/AR®, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries. All other trademarks are the property of their respective owners. For more information, please email info@gowinsemi.com
Media Contact:
Andrew Dudaronek
andrew@gowinsemi.com
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2024-10-29
Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
By Jason Zhu
CEO, GOWIN Semiconductor
When a designer of telecoms equipment such as a server or switch specifies an FPGA for a high-speed data interfacing function, performance is the most important criterion for choosing the preferred device. If the rule of thumb in specifying an electronics component is that the designer can have one or two of high speed, low power consumption, small size and low cost, but not three or all four of these attributes, the telecoms equipment manufacturer will prioritize high speed above the other factors.
This has given the manufacturers of high-end, high-density FPGAs a strong incentive to develop products which are packed with high-performance SerDes capabilities, and which support the high-speed communications protocols – PCIe, Ethernet, Infiniband and so on – on which communications service providers’ fiber networks are based.
These FPGAs might be large, they might be expensive, and they might be power-hungry – but this is of little importance to equipment manufacturers serving the telecoms market, as long as they are fast.
How different it is in the market for portable and wearable consumer devices, where the cost, power consumption and size of an FPGA are impossible to overlook. This has meant that the FPGA’s role in consumer devices has generally been limited to functions which basic FPGAs – small, low-power, low-density and low-cost products – can perform, such as:
Glue logic integration
Simple counter
Basic state machine
Control logic
I/O and interface bridging
I/O expansion
Aggregation of multiple sensor inputs
Voltage monitoring
For anything more demanding, the FPGA market did not in the past provide products which could meet the consumer market’s speed/cost/size requirements.
In fact, there was no demand for the FPGA’s high-speed data interfacing capabilities for as long as consumer devices were handling relatively small amounts of data to support undemanding input and output devices such as a basic camera or a small display.
But the consumer world is changing: technology and consumer demand are driving data throughput off the scale. We are discovering that there is almost no limit to people’s appetite for vivid, ultra high-definition (UHD) video and AI-enhanced high-resolution imaging, even in space- and power-deprived wearable products such as AR/VR headsets and smart glasses
(see Figure 1).
For instance, a VR headset will typically be required to cram the type of UHD content more normally viewed on a large TV screen on to two synchronized displays. Not only must the output achieve 4K or even 8K resolution, it must also be rendered at a higher frame rate – typically 128 frames/s – than a standard TV achieves, to avoid the risk of motion blur.
Fig. 1: to create immersive experiences, a VR headset requires ultra high-definition display capability, and the internal data bandwidth to support it
This is leading device manufacturers to migrate from interfaces such as MIPI D-PHY or DisplayPort for video to higher-speed alternatives such as MIPI C-PHY. And this calls for the type of high-speed SerDes capability that the telecoms equipment designer uses an FPGA to provide.
But we know that the high-speed FPGAs developed for the telecoms market are not suitable for consumer devices.
This is why I foresee the emergence of a new category of FPGA at the low-density, low-cost end of the market that has previously been limited to basic logic functions.
This new-generation FPGA will be optimized for high-speed SerDes functions: it will offer not only raw high-speed SerDes capability, but will also specifically support the protocols that the new consumer devices is using, such as MIPI C-PHY and PCIe, either as soft-coded IP or even hard-coded into the silicon (see Figure 2). This SerDes capability will be backed by more generous provision of high-speed memory than is usual in low-end FPGAs.
Fig. 2: examples of video bridging and processing use cases in the latest consumer devices
Optimized for data-interfacing and data-bridging functions, this new generation of FPGA will provide limited scope for implementing other logic functions, with few general-purpose logic elements available to the application, in order to minimize die size and cost.
GOWIN Semiconductor’s view is that such an FPGA demands a strategic shift from the manufacturers of low-density FPGAs. To date, they have met the requirement for low cost by stretching out the life of legacy process nodes used to fabricate their products, using a 40nm process or older, for which the investment in equipment and mask sets is relatively small.
GOWIN itself has a strong position in consumer devices with its LittleBee family of low-density FPGAs, which are themselves built on a legacy process. The LittleBee FPGAs perform a data aggregation function in many wearable and mobile devices. Without data aggregation, sensor data would be transferred to the main microcontroller or system-on-chip (SoC), and commands or configuration data transferred from the SoC to sensors, over low-speed interfaces such as I2C, UART or SPI working as sideband communication channels. This results in the proliferation of wires between the SoC and sensor sub-systems, which are often mounted on a separate board from the main controller board.
By implementing data aggregation in an FPGA, data from multiple sensors can be combined into a single high-speed data stream, reducing the number of physical network connections between the host and the various sub-systems. An example of the implementation of data aggregation is the OCP DC-SCM project in servers.
While legacy fabrication processes might be adequate for the aggregation of low-speed I2C, UART or SPI interfaces, however, they are not going to meet the requirement for advanced SerDes circuitry: the MIPI C-PHY specification, for instance, supports a data rate of up to 13.7Gbps [1], offering as much as three times the bandwidth of the earlier MIPI D-PHY standard.
This is why GOWIN took the radical decision to move to an advanced node – a TSMC 22nm ultra low-power process – for its Arora V family of low-density FPGAs. This 22nm process has allowed GOWIN to include a high-speed transceiver on-chip in the Arora V FPGAs. It has also enabled much larger memory provision: in the shift from the 55nm node used for LittleBee FPGAs to 22nm, the size of the memory cell shrinks by 90%.
The practical consequence of the decision to adopt 22nm fabrication can be seen in the specifications of the Arora V GW5AT-60 product. It features four transceivers supporting a data-rate range of 270Mbps up to 12.5Gbps. A hardcore MIPI D-PHY interface offers four data lanes, and a hardcore MIPI C-PHY has three data lanes. Softcore interfaces include PCIe 2.0 (with 1, 2 and 4 lanes), and LVDS at up to 1.25Gbps, as well as a DDR3 interface operating at up to 1,333Mbps. Memory provision includes 118 blocks of 2,124kb block SRAM, and 468kb of shadow SRAM. The FPGA also includes 60k LUT4 logic elements. The device’s core voltage is 0.9V/1.0V/1.2V.
This illustrates the way that, by fabricating at an advanced node, it becomes possible to create a low-density, low-power FPGA that provides for very high-speed data interfacing. And because of the small size of this FPGA, it can be offered at a unit cost which is affordable in wearable and portable consumer devices. In fact, the cost is attractive enough that OEMs can retain the FPGA in high-volume production, without having to contemplate replacing it with a custom ASIC, a step which is time consuming and risky, and which OEMs prefer to avoid.
The commitment to an advanced silicon process in a product family which includes low-end FPGAs is now pointing the market in a new direction, one which combines the high-speed transceiver capabilities of traditional telecoms FPGAs with the low cost and low power consumption of traditional low-end FPGAs.
There is a ready market for this new generation of FPGAs in consumer devices which use new high-speed transceiver capabilities to meet the needs, today, of ultra high-definition cameras and displays – and in future, potentially of additional high-speed peripherals supporting a new set of features and use cases driven by AI, AR and VR systems.
Reference:
[1] MIPI C-PHY maximum data rate, from: https://www.mipi.org/specifications/c-phy
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2024-10-15
How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
By Danny Fisher
Director of International Marketing, GOWIN Semiconductor
FPGAs are at home in the world of multi-gigabit-per-second signal conversion and bridging.
In high-bandwidth telecoms, network and data center equipment, the FPGA is a mainstay of system designs, offering a valuable combination of high-speed SerDes capability, extensive logic resources, and programmability, giving designers the flexibility to modify features and functions without changing their board layout.
Indeed, FPGA manufacturers have a long track record of creating products which are well suited to the telecoms central office or the data center environment: very fast and large chips which provide hundreds of I/Os, huge bandwidth, and built-in standard interfaces. The fact that they are also expensive and power-hungry is a bearable trade-off for telecoms and network equipment manufacturers.
Increasingly, however, the need for multi-gigabit-per-second rates in signal bridging systems is extending from telecoms and network equipment into consumer and industrial devices. Here, too, the FPGA offers valuable benefits. But large, expensive, power-hungry ICs are a poor fit for sleek, battery-powered consumer devices in the ultra-competitive markets for products such as tablets, laptop computers, and augmented/virtual reality (AR/VR) headsets.
This new demand in consumer electronics is forcing FPGA manufacturers to rethink the architecture of their products in a bid to provide high-speed SerDes functionality at lower cost and low power.
Gamers lead the way
The change which has precipitated a new wave of competition in the low-cost FPGA market has been led by demand from gamers: tablets and laptop computers have become the latest devices in which users want to play games in 4K resolution and – for smooth rendition of fast motion – at high frame rates of up to 160 frames/s.
The requirement for high-speed video signal transmission to support 4K displays stretches the capability of the interfaces that have previously been used in consumer devices to shuttle data from the central system-on-chip (SoC) to a display. Older MIPI D-PHY interface technology is giving way to the newer MIPI C-PHY standard for the most demanding 4K display applications in tablets and laptop computers. The doubling of the data rate in the migration from D-PHY to C-PHY technology poses a demanding challenge for low-end FPGAs.
Following the lead of the latest gaming tablets and computers, other use cases are now also starting to demand increased bandwidth in the link between an SoC and one or more displays, or between image sensors and an SoC. Examples include:
Point-of-sale systems which split a single output from an SoC (typically in MIPI DSI format) to dual displays, one facing the consumer, one facing the sales counter. The FPGA typically converts the single DSI input to one DSI and one eDP output, with image processing to rescale the output and adjust the frame rate (see Figure 1)
VR/AR headsets and goggles, splitting and converting a DisplayPort-over-USB Type-C® input from a host device such as a PC or smartphone to separate MIPI outputs to a left and right display in the headset
Industrial machine vision systems, converting an image sensor’s MIPI D-PHY or C-PHY input to a high-speed USB 3.0 output to a host computer.
Fig. 1: using the GW5AT-15 FPGA, a single MIPI DSI video input from an external SoC can be converted to feed two displays requiring one MIPI output and one eDP output
Higher-speed SerDes at lower power and cost
In all these use cases, an FPGA can provide the raw SerDes throughput for one or multiple display screens or image sensors, while enabling changes in the input or output specifications to be made just by changing the VHDL or Verilog programming of the device. The question the consumer and industrial markets are asking is, how far can power consumption, size and cost be reduced while providing the high SerDes bandwidth these applications require?
GOWIN has provided a new answer to the question by combining application-specific optimizations at both the silicon and circuit design level in a way that no low-density FPGA has ever before attempted.
In silicon, scaling provides PPAC benefits (power, performance, area and cost) for low-end FPGAs as much as for other semiconductors. In the past, however, low-density FPGAs have tended not to take advantage of more advanced process nodes – FGPA manufacturers have preferred to extend the life of IP developed for legacy processes.
But high-speed video bridging places extreme demands on the FPGA. That is why for its Arora® V products, GOWIN shifted production from the 55nm process used in its Arora II products to TSMC’s ultra-low power 22nm process.
Use of this process has enabled GOWIN to gain performance, power and cost benefits in low-density Arora V products such as the GW5AT-15, available in a compact 4.9mm x 5.3mm WLCSP package. Despite its small size, this FPGA combines various hard-core SerDes transceivers offering maximum SerDes throughput of 12.5Gbps, together with 15,120 logic elements alongside high-speed memory resources including:
118kb of shadow SRAM
630kb of block SRAM (BSRAM) arranged as 35 x 18kb
Optional 64Mb (in MG132P package) or 128Mb (in CM90P package) of pseudo SRAM (pSRAM)
Optional 8Mb of NOR Flash
By limiting the programmable logic provision to 15,120 logic elements, GOWIN can produce a smaller die at a lower unit cost, while providing sufficient digital capability to perform important image processing functions such as frame scaling and frame rate adaptation.
The application-specific circuit design optimizations in the Arora V family provide the higher SerDes throughput required for instance by the gamers viewing 4K content at 160 frames/s on a tablet. For instance, the GW5AT-15 features hardcore implementations of important SerDes interfaces:
Three-lane MIPI C-PHY (5.7Gbps/lane)
Four-lane MIPI D-PHY (2.5Gbps/lane)
x4 PCIe 2.0
Alongside these circuit features, the GW5AT-15 includes various built-in softcore interfaces suitable for video bridging applications: a USB 2.0 PHY, USB 3.0 PHY, PCIe 3.0, and up to four lanes of 12.5Gbps/lane SerDes suitable for DisplayPort, eDP, SLVS-EC, LVDS and other types of video traffic.
These capabilities are what is required for the gaming tablet rendering 4K video at a high frame rate, converting a typical SoC’s MIPI output to a tablet display’s eDP input (see Figure 2).
Fig. 2: conversion of video data from MIPI to eDP format in a gaming tablet requires high SerDes throughput
The implementation of fast video bridging and image processing is as important when interfacing to a camera as when rendering video on a display. In industrial machine vision systems, for instance, a GOWIN GW5AT-15 or -60 can connect to a camera’s MIPI D-PHY or C-PHY interface and bridge the video to a host PC’s high-speed USB Type-C interface (see Figure 3). The FPGA’s softcore USB 3.0 PHY and USB 3.0 controller enables a single-chip implementation that can interface directly to the host controller without an external USB 3.0 PHY.
This solution has an extremely small footprint which can be integrated into the camera enclosure.
The GW5AT-60, which offers 59,950 logic elements, provides sufficient resources to support image preprocessing and machine vision-related algorithms. It also provides high-speed four-channel SerDes transceivers, hardcore MIPI C-PHY and D-PHY interfaces, and softcore LVDS interfaces to support a wide variety of sensors.
Fig. 3: in an industrial machine vision system, use of an Arora V FPGA enables the USB 3.0 interface to a host PC to be integrated into the camera enclosure
A new direction for the low-density FPGA
The optimization of an FPGA product for video bridging and image processing applications points this segment of the low-density FPGA market in a new direction: in pursuit of greater size, power and cost reduction, FPGA products are evolving to include more application-specific SerDes functionality hard-wired into small devices.
And where previously FPGAs achieved low cost by maintaining older, legacy silicon fabrication processes, a new generation of low-density FPGAs are using advanced processes to provide the valuable advantages of low power and small footprint while reducing cost by limiting the provision of logic elements that are not required in the target applications.
This brings the FPGA to center stage in the consumer device market, enabling a new generation of devices to benefit from improved display and camera performance without sacrificing battery power or competitive cost.
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