DK_START_GW5AT-LV138FPG676A

The DK_START_GW5AT-LV138FPG676A_V2.0 development board is designed for various applications, including high-speed data storage using DDR3, high-speed communication tests based on MIPI, LVDS, SERDES, FMC, and the evaluation of the GW5AT-138 series of FPGA functions. It is also suitable for hardware verification, software learning, and debugging.

The board uses the GW5AT-LV138FPG676A FPGA device, which is a part of the Gowin GW5AT series of FPGA products. This series includes abundant internal resources, high-performance DSP with a new architecture that supports AI operations, high-speed LVDS interface, and abundant BSRAM resources. The FPGA device also integrates self-developed DDR3 and 12.5Gbps SERDES, which support multiple protocols and come in a variety of packages. With its low power consumption, high performance, and compatibility design, the Arora V FPGA products, which are manufactured using 22nm process technology, are suitable for low-cost, high-speed applications.

FEATURES

FPGA Device
- The development board uses the GW5AT-LV138FPG676A FPGA device, which is the fifth generation products of Gowin Arora family.
- Max. user I/O: 376
Download and Boot
- Integrate download module on the board, download through USB 2.0 cable
- External Flash boot
- The DONE light is on after loading
Power
- External DC 12V 2A Power
- The POWER light is on after power on
- The board generates 0.9V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V power supplies
- The board generates power supplies required for FMC interfaces, MIPI interfaces, and SFP interfaces.
Clock System
- 50MHz clock, 100MHz clock, 200MHz clock, programmable clock
Memory Device
- 4Gbit DDR3 SDRAM
- 128Mbit Quad SPI FLASH Memory

SFP/SFP+ Interface
- 2 compact pluggable SFP+ connectors that receives SFP or SFP+ modules
MIPI Interface
- The interface includes 10 pairs of differential signals including 2 pairs for clock and 8 pairs for data, 34 single-ended signals, power supply, and GND.
- Use connector with 80 contacts and 0.5mm pitch
FMC Interface
- 58 pairs of differential signals: 34 pairs of LA (LA00-LA33); 24 pairs of HA (HA00-HA23)
- 4 pairs of GTP transceivers
- 2 pairs of GTP transceiver reference clocks
- 2 pairs of external input differential reference clocks
- 159 GNDs and 15 power connections
- Use 400pin HPC FMC connector with 1.27mm pitch
- Differential signals of 3 lanes are channeled to the 20pin double rows with 2.00mm pitch
XADC Module
- The interface uses 2*4pin pin
- The XADC differential input is designed with an anti-aliasing filter
PCIe x4 Interface
- The overall dimension of the PCIe card conforms to the standard PCIe card electromechanical specification and can be used directly on a normal PCIe x4 slot
- The transceiver signals of PCIe interface are directly connected to the GTP transceivers of FPGA

Debug Module
- 4 Keys
- 4 LEDS

Buy from our Distributors Contact GOWIN

Documents Download

User Guide	DK_START_GW5AT-LV138FPG676A_V2.0 Development Board User Guide	Download
Schematic	DK_START-GW5AT-LV138FPG676A_V2.0_SCH	Download