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Documentation Database
IP and Reference Design

Previous Name: DK-START-GW2A55-PG484 V1.3


DK_START_GW2A-LV55PG484C8I7_V1.3 applies to high speed data storage based on DDR3, high-speed communication test based on MIPI, LVDS and GbE, 55k series of FPGA products functions evaluation, the verification of hardware reliability, software learning and debugging, etc.


The development board uses the GW2A- LV55PG484 FPGA device, which is the first generation product of Gowin Arora family. The GW2A series of FPGA products offer a range of features and rich resources like high-performance DSP, high-speed LVDS interface and BSRAM. These embedded resources combine a streamlined FPGA architecture with a 55nm process to make the GW2A series of FPGA products ideal for high-speed and low-cost applications.


DK_START_GW2A-LV55PG484C8I7_V1.3 development board includes a DDR3 chip with 2Gbit, 16-bit bus width. Its two Gigabit Ethernet interfaces support 10M, 100M, 1000M Ethernet communication. It has abundant peripheral interfaces, including LVDS interfaces, a SD card socket, CAN bus interface, MIPI CSI, MIPI DSI, AD/DA interface and GPIO interfaces. RTC module is designed to provide real-time clock for MCU IP. Besides that, it also offers an external Flash, switches, keys, LED, etc.

Documents Download
Schematic DK_START_GW2A-LV55PG484C8I7_V1.3 Schematic Download
BSDL BSDL Download
Schematic Gowin Minimum FPGA System SCH Download
SCH Symbol Gowin FPGA SCH Symbol Download
User Guide DK_START_GW2A-LV55PG484C8I7_V1.3 Development Board User Guide Download