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PRODUCTS
Low Power, High Performance, High Reliability
Arora V SRAM Based FPGAs

GOWINSEMI’s Arora V FPGA series provides SRAM-based FPGA devices with increased logic resources, interfaces and performance.  Arora V FPGAs include DDR3 memory interfacing, 12.5Gbps CDR-based SERDES supporting multiple protocols and flexible packaging options making it the ideal choice for communications, server, imaging, and automotive applications requiring high interface and computing throughput by providing best performance/watt.

 

Arora V is supported by GOWIN EDA providing an efficient and easy-to-use FPGA hardware development environment support multiple RTL-based programming languages, synthesis, placement & routing, bitstream generation and download, power analysis and in-device logic analyzer.

 

Arora V FPGA Product Features:

 

FPGA Fabric Architecture

  • Up to 138K LUTs(GW5A(S)(T)-138)
  • Up to 23K LUTs(GW5A-25)
  • Block SRAM with multiple modes
    • Single Port, Semi-Dual Port, True Dual Port, and Semi Dual Port with ECC function
    • Byte write enable
    • ECC error detection and correction
  • High performance DSP
    • Multipliers support 12x12, 27x36, 27x18-bit modes
    • Includes 48-bit accumulator
    • Supports DSP cascading
    • Embedded pipeline and bypass registers
    • Pre-addition operation for filter function
    • Internal feedback loop and barrel shifter
  • Advanced Clocking
    • Up to 16 global clocks
    • Up to 6/12 high-performance PLLs
    • Up to 16/24 high speed edge clocks

 

Flexible GPIO

 

  • Adjustable drive strength
    • 4mA, 8mA, 12mA, 16mA, 24mA drive
  • Bus keeper, pull up/down, and open drain
  • Hot Socket and input hysteresis
  • Slew Rate option for output signal

 

ADC

 

  • 60dB SNR and 1kHz Signal Bandwidth
  • Flexible X-channel oversampling ADC
  • No external voltage source required

 

Configuration & Programming

 

  • JTAG, SSPI, MSPI, CPU, and SERIAL
    • Background programming
    • SPI Flash Programming and Boot
    • Multi-boot
  • Bitstream encryption and Security
  • Configuration Memory Soft Error Recovery(CMSER)
  • mDRP(GW5A)
  • Supports OTP, each device has a unique 64-bit DNA identifier

 

High Speed Interfaces

 

  • SERDES(GW5AT, GW5AST)
    • 270Mbps-12.5Gbps operation
    • CDR (Clock Data Recovery)
    • Dedicated RX and TX Channels
    • Integrated 8b/10b encoder/decoder
    • PCI 2.0 hardcore
      • x1, x2, x4, x8 lanes
      • Supports root complex and end point
  • GW5AST series of FPGA products provide a hardcore processor RiscV AE350_SOC

  • MIPI D-PHY RX hardcore(GW5A(S)(T)-138)
    • 20Gbps D-PHY RX Hard PHY
    • 8 data lanes + 2 clock lanes
    • 2.5Gbps/lane
    • Built-in SoT HS-Sync, word and lane alignment
    • MIPI DSI and MIPI CSI-2 RX link layer IPs
  • MIPI D-PHY RX/TX hardcore(GW5A-25)
    • 4 data lanes + 1 clock lane
    • 2.5Gbps/lane(RX/TX)
    • Built-in SoT HS-Sync, word and lane alignment
    • MIPI DSI and MIPI CSI-2 RX link layer IPs
  • GPIOs support MIPI C-PHY RX/TX and D-PHY RX/TX(GW5A-25)
    • 1.2Gbps/lane
    • GPIOs can be configured as MIPI DSI and MIPI CSI-2 RX/TX device interface
  • GPIOs support MIPI D-PHY RX(GW5A(S)(T)-138)
    • 1.5Gbps/lane
    • GPIOs can be configured as MIPI DSI and MIPI CSI-2 RX device interface
  • External DRAM Interfaces
    • Supports various memory types
      • DDR2, DDR3, PSRAM, HyperRAM, RPC
    • Up to 1333 Mbps (GW5A(S)(T)-138) or 1066 Mbps (GW5A-25)

GW5A Series Table

 

 

Device GW5A-25 GW5A-138
LUT4 23040 138240
REG 23040 138240
Shadow SRAM SSRAM (kb) 180 1080
Block SRAM BSRAM (kb) 1008 6120
Number of BSRAM 56 340
DSP 28 298
PLLs 6 12
Global Clock 16 16
HCLK 16 24
Transceivers 0 0
Transceivers Rate N/A N/A
PCle 2.0 0 0
LVDS Gbps 1.25 1.25
DDR3 Mbps 1066 1333
MIPI D-PHY Hardcore

2.5Gbps(Rx/Tx)

4 Data Lanes

1 Clock Lane

2.5Gbps(Rx)

8 Data Lanes

2 Clock Lanes

ADC 1 2
Number of GPIO Banks 9 6
Max I/O 236 376
Core Voltage 0.9V/1.0V 0.9V/1.0V

 

 


 

Package Options and Availible User I/O (LVDS Pairs):

 

Package Pitch (mm)

Size(mm)

GW5A-25 GW5A-138
MG121N 0.5 6 x 6 86(38) -
UG324S 0.8 15 x 15 239(116) -
UG256C 0.8 14 x 14 191(90) -
PG256C 1.0 17 x 17 191(90) -
UG324 0.8 15 x 15 222(104) -
UG324A 0.8 15 x 15 - 222(106)

MG196S

0.5

8 x 8

114(53)

-

UG225S

0.8

13 x 13

168(80)

-

 

Note!

  • The number of PLLs supported by different packages is different, here is the maximum value.
  • In addition to the GPIO Bank, it also includes a JTAG Bank with 4 I/Os and a Config Bank with 1 I/O.
  • The EV version has a built-in LDO, and VCC can support 1.2V.

GW5AT Series Table

 

 

Device GW5AT-60 GW5AT-138
LUT4 57600 138240
REG 57600 138240
Shadow SRAM SSRAM (kb) 450 1080
Block SRAM BSRAM (kb) 2322 6120
Number of BSRAM 129 340
DSP 120 298
PLLs 10 12
Global Clock 16 16
HCLK 20 24
Transceivers 4 8
Transceivers Rate

270Mbps-

12.5Gbps

270Mbps-

12.5Gbps

PCle 2.0

1,

x1, x2, x4 PCIe 2.0

1,

x1, x2, x4, x8 PCIe 2.0

LVDS Gbps 1.25 1.25
DDR3 Mbps 1333 1333
MIPI D-PHY Hardcore

2.5Gbps(RX/TX)

8 Data Lanes

2 Clock Lanes

2.5Gbps(RX)

8 Data Lanes

2 Clock Lanes

MIPI C-PHY Hardcore

2.5Gsps
(=5.75Gbps,RX/TX),

3-trios data lanes

-

ADC 1 2
Number of GPIO Banks 5 6
Max I/O 250 376
Core Voltage 0.9V/1.0V 0.9V/1.0V

 

 


 

Package Options and Availible User I/O (LVDS Pairs):

 

Package Pitch (mm)

Size(mm)

GW5AT-60 GW5AT-138
FPG676A(Flip Chip) 1.0 27 x 27 - 312(150)
PG484A 1.0 23 x 23 - 297(143)

PG484

1.0

23 x 23

-

277(133)

 

Note!

  • The number of PLLs supported by different packages is different, here is the maximum value.
  • The EV version has a built-in LDO, and VCC can support 1.2V.

 

GW5AST Series Table

 

 

Device GW5AST-138
LUT4 138240
REG 138240
Shadow SRAM SSRAM (kb) 1080
Block SRAM BSRAM (kb) 6120
Number of BSRAM 340
DSP 298
PLLs 12
Global Clock 16
HCLK 24
Transceivers 8
Transceivers Rate

270Mbps-

12.5Gbps

PCle 2.0

1,

x1, x2, x4, x8 PCIe 2.0

LVDS Gbps 1.25
DDR3 Mbps 1333
MIPI D-PHY Hardcore

2.5Gbps(RX)

8 Data Lanes

2 Clock Lanes

Hard-core Processor

RiscV AE350_SOC

ADC 2
Number of GPIO Banks 6
Max I/O 376
Core Voltage 0.9V/1.0V

 

 


 

Package Options and Availible User I/O (LVDS Pairs):

 

Package Pitch (mm)

Size(mm)

GW5AST-138
FPG676A(FC) 1.0 27 x 27 312(150)
PG484A 1.0 23 x 23 297(143)

 

Note!

  • The number of PLLs supported by different packages is different, here is the maximum value.